summaryrefslogtreecommitdiffstats
path: root/gas/config/bfin-parse.y
Commit message (Collapse)AuthorAgeFilesLines
* gas/Jie Zhang2011-12-151-17/+20
| | | | | | | | | | | | | | | | | | | 2011-12-14 Stuart Henderson <shenders@gcc.gnu.org> * config/bfin-parse.y (asm_1): set SRCx fields to all 1s for dspalu32 instrs that don't use them. gas/testsuite/ 2011-12-14 Stuart Henderson <shenders@gcc.gnu.org> * gas/bfin/move.d: Update SRCx field expectations. * gas/bfin/move2.d: Likewise. * gas/bfin/parallel.d: Likewise. * gas/bfin/parallel2.d: Likewise. * gas/bfin/parallel3.d: Likewise. * gas/bfin/parallel4.d: Likewise. * gas/bfin/video.d: Likewise. * gas/bfin/video2.d: Likewise.
* gas: blackfin: gas: blackfin: reject invalid BYTEUNPACK insnsMike Frysinger2011-03-291-0/+2
| | | | | | | The destination registers must be different with BYTEUNPACK insns, otherwise the hardware throws up an exception. So reject them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: gas: blackfin: reject invalid BYTEOP16M insnsMike Frysinger2011-03-291-0/+2
| | | | | | | The destination registers must be different with BYTEOP16M insns, otherwise the hardware throws up an exception. So reject them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: gas: blackfin: reject invalid BYTEOP16P insnsMike Frysinger2011-03-291-0/+2
| | | | | | | The destination registers must be different with BYTEOP16P insns, otherwise the hardware throws up an exception. So reject them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: reject invalid 16bit acc add insnsMike Frysinger2011-03-291-0/+3
| | | | | | | The 16bit acc add insn cannot assign the two results to the same dreg, so make sure gas rejects attempts to use this insn variant. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: reject invalid register destinations for vector add/subMike Frysinger2011-03-241-1/+6
| | | | | | | The destination registers with vector add/sub insns must be different, so make sure gas rejects attempt to write these. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: catch invalid dest dregs in dsp mult insnsMike Frysinger2011-03-241-4/+8
| | | | | | | | | While we were catching a few mismatches in vectorized dsp mult insns, the error we displayed was misleading. Once we fix that up, we can convert previously dead code into proper checking for destination dreg matching. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: catch invalid register combinations with SEARCH/BITMUXMike Frysinger2011-03-241-0/+6
| | | | | | | The destination registers for SEARCH cannot be the same. Same rule for the source registers for BITMUX. Signed-off-by: Mike Frsyinger <vapier@gentoo.org>
* gas/opcodes: blackfin: punt BYTEOP2M insn supportMike Frysinger2011-02-131-17/+1
| | | | | | | The BYTEOP2M insn was part of the initial Blackfin designs, but never made it into any actual silicon. So punt support for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: reject FP/SP with TESTSETMike Frysinger2011-02-111-0/+3
| | | | | | The TESTSET insn does not work with the FP/SP Pregs, so reject them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: fix encoding of BYTEOP2M insnMike Frysinger2010-10-151-2/+2
| | | | | | | | The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode. Once we've fixed that, it's easy to see that the disassembler also likes to decode this insn incorrectly. So fix that and then add some tests. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: support numeric local labels with LOOP_BEGIN/LOOP_END pseudo ↵Mike Frysinger2010-10-111-0/+22
| | | | | | | | | | insns The current LOOP_BEGIN/LOOP_END pseudo insns hit parser errors when trying to use numeric local labels. So add support for them. Signed-off-by: David Gibson <david.gibson@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: fix typo in BYTEOP16P commentMike Frysinger2010-09-221-1/+1
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: reject multiple store insns in parallel insnsMike Frysinger2010-09-221-0/+33
| | | | | | | | Check for & reject attempts to use multiple store insns in a single parallel insn combination. These are illegal per the Blackfin ISA. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: add missing register move insnsMike Frysinger2010-09-221-2/+4
| | | | | | | | The Blackfin ISA supports moving just about anything to/from EMUDAT, so make sure the assembler accepts these insns too. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: clarify some errors with register usage in insnsMike Frysinger2010-09-221-3/+3
| | | | | | | | Using "Register mismatch" everywhere can be a bit vague, so clarify why exactly we're barfing on these unsupported insns. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: fix DBG/DBGCMPLX insn encodingMike Frysinger2010-09-221-2/+2
| | | | | | | | | Some extended registers when given to the DBG/DBGCMPLX pseudo insns are not encoded properly. So fix them, fix the display of them when being disassembled, and add testcases. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* opcodes/gas: blackfin: support OUTC debug insnMike Frysinger2010-09-221-0/+16
| | | | | | | | | The disassembler has partial (but incomplete/broken) support already for the pseudo debug insn OUTC, so let's fix it up and finish it. And now that the disassembler can handle it, make sure our assembler can output it too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas: blackfin: support ABORT debug insnMike Frysinger2010-09-221-0/+6
| | | | | | | | There is a pseudo debug insn named ABORT that is commonly used in simulation, so support it in the assembler too. The disassembler already supports it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* strip trailing whitespace in Blackfin filesMike Frysinger2010-03-101-74/+74
|
* * config/bfin-aux.h: Remove argument names in functionJie Zhang2010-01-141-4/+4
| | | | | | | | | | declarations. * config/bfin-lex.l (parse_int): Fix shadowed variable name warning. * config/bfin-parse.y (value_match): Remove argument names in declaration. (notethat): Likewise. (yyerror): Likewise.
* Add -Wshadow to the gcc command line options used when compiling the binutils.Nick Clifton2009-12-111-5/+5
| | | | Fix up all warnings generated by the addition of this switch.
* gas/Jie Zhang2009-09-041-4/+10
| | | | | | | | | | | | | | | | | | | | | * config/bfin-parse.y (asm_1): Implement HLT instruction. Fix comments for DBGA, DBGAH and DBGAL. * config/tc-bfin.c (bfin_gen_pseudodbg_assert): Change according to the new encoding of DBGA, DBGAH, and DBGAL. include/ * opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): Adjust accordingly. (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and PseudoDbg_Assert_grp_mask. opcodes/ * bfin-dis.c (decode_pseudodbg_assert_0): Change according to the new encoding of DBGA, DBGAH, and DBGAL. (_print_insn_bfin): Likewise.
* gas/Jie Zhang2009-09-031-13/+13
| | | | | | | | | | | | | | * config/bfin-parse.y: Remove trailing whitespace. (ccstat): Indent. * config/tc-bfin.c (struct bfin_reg_entry): Remove. (bfin_reg_info[]): Remove. opcodes/ * bfin-dis.c (_print_insn_bfin): Don't declare. (print_insn_bfin): Don't declare. (dregs_pair): Remove. (ignore_bits): Remove. (ccstat): Remove.
* * config/bfin-parse.y (gen_multi_instr_1): Check anomalyJie Zhang2009-09-031-0/+1
| | | | | | | | 05000074 only when both slot1 and slot2 are filled. testsuite/ * gas/bfin/parallel5.s: New test. * gas/bfin/error.exp: New test.
* gas/Jie Zhang2009-09-031-2/+11
| | | | | | | | | | | | | | | | | | | | | | * config/bfin-defs.h (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. * config/bfin-parse.y (asm_1): Check illegal register move instructions. gas/testsuite/ * gas/bfin/expected_move_errors.s, gas/bfin/expected_move_errors.l: Add "LC1 = I0;". * gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W". opcodes/ * bfin-dis.c (IS_DREG): Define. (IS_PREG): Define. (IS_AREG): Define. (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. (decode_REGMV_0): Check illegal register move instructions.
* * config/bfin-parse.y (asm_1): Fix a typo.Jie Zhang2009-09-031-1/+1
| | | | | testsuite/ * gas/bfin/expected_comparison_errors.l: Expect error on Line 13.
* * config/bfin-parse.y (asm_1): Add LOOP_BEGIN and LOOP_END.Jie Zhang2009-09-031-0/+21
| | | | | | | | | | | | | | * config/tc-bfin.c (bfin_start_line_hook): Remove. (bfin_loop_beginend): New. * config/tc-bfin.h (bfin_start_line_hook): Don't declare. (md_start_line_hook): Don't define. * config/bfin-aux.h (bfin_loop_beginend): Declare. testsuite/ * gas/bfin/loop.s, gas/bfin/loop.d: New test. * gas/bfin/loop2.s, gas/bfin/loop2.d: New test. * gas/bfin/loop3.s, gas/bfin/loop3.d: New test. * gas/bfin/bfin.exp: Add the new tests.
* * config/bfin-parse.y (value_match): Use int instead of long.Jie Zhang2009-09-021-4/+4
| | | | | | From Michael Frysinger <michael.frysinger@analog.com> * config/bfin-defs.h (Expr_Node_Value): Declare the i_value member as long long.
* From Bernd Schmidt <bernd.schmidt@analog.com>Jie Zhang2009-09-021-115/+185
| | | | | | | | | | | * config/gas/bfin-parse.y (asm_1): Clean up and unify error handling for load and store insns. (neg_value): Delete function. testsuite/ From Bernd Schmidt <bernd.schmidt@analog.com> * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Check error messages for invalid load/store insns.
* update copyright datesAlan Modra2009-09-021-1/+1
|
* * config/bfin-parse.y (asm_1): Only PREG and DREG are allowedJie Zhang2009-09-011-21/+21
| | | | | | | | in comparison. testsuite/ * gas/bfin/expected_comparison_errors.s: Add more cases. * gas/bfin/expected_comparison_errors.l: Update accordingly.
* From Jie Zhang <jie.zhang@analog.com>Bernd Schmidt2009-08-111-0/+10
| | | | | | | | | | | | | | | | | | | | | | * config/tc-bfin.h (bfin_anomaly_checks): Declare. (AC_05000074): Define. (ENABLE_AC_05000074): Define. * config/tc-bfin.c (enum bfin_cpu_type): New. (bfin_cpu_t): Typedef. (bfin_cpu_type): Define. (bfin_si_revision): Define. (bfin_anomaly_checks): Define. (struct bfin_cpu): New. (bfin_cpus[]): New. (struct bfin_cpu_isa): Define. (bfin_isa): New global variable. (OPTION_MCPU): Define. (md_longopts[]): Add -mcpu option. (md_parse_option): Deal with -mcpu option and initialize bfin_anomaly_checks. * doc/c-bfin.texi: Rename BFIN to Blackfin throughout. Document -mcpu option. * config/bfin-parse.y (gen_multi_instr_1): Check anomaly 05000074.
* gas/Bernd Schmidt2009-08-111-12/+24
| | | | | | | | | | | | | | | | | | | | * config/bfin-parse.y (gen_multi_instr_1): New function. (asm): Use it instead of bfin_gen_multi_instr. (error): Add a format string when calling as_bad. * config/bfin-defs.h (insn_regmask): Declare. * config/tc-bfin.c (DREG_MASK, DREGH_MASK, DREGL_MASK, IREG_MASK): New macros. (decode_ProgCtrl_0, decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, decode_dsp32mac_0, decode_dsp32mult_0, decode_dsp32alu_0, decode_dsp32shift_0, decode_dsp32shitimm_0, insn_regmask): New functions. gas/testsuite/ * gas/bfin/parallel.s: Add more test cases. * gas/bfin/parallel.d: Update accordingly. * gas/bfin/resource_conflict.l: New test. * gas/bfin/resource_conflict.s: New test. * gas/bfin/bfin.exp: Add resource_conflict.
* fix typo in gas error output (this is an assembler, not a compiler)Mike Frysinger2009-08-111-2/+2
|
* PR 10143Nick Clifton2009-05-261-2/+2
| | | | | * config/bfin-parse.y (error): Use "%s" as format string for error message.
* * config/bfin-parse.y: Use C style comments.Alan Modra2008-10-201-2/+2
| | | | | | * config/tc-bfin.c: Likewise. * config/tc-m68k.c: Likewise. * config/tc-mips.c: Likewise.
* * config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.Jie Zhang2008-09-261-12/+10
|
* * config/bfin-parse.y (check_macfunc_option): Fix instructionJie Zhang2008-08-261-12/+15
| | | | | | | | | | | | mode checking. (asm_1): Check mode for 16-bit multiply instructions. testsuite/ * gas/bfin/arith_mode.d: New test. * gas/bfin/arith_mode.s: New test. * gas/bfin/invalid_arith_mode.l: New test. * gas/bfin/invalid_arith_mode.s: New test. * gas/bfin/bfin.exp: Add arith_mode and invalid_arith_mode.
* * config/bfin-parse.y (asm_1): Error if plain symbol is usedJie Zhang2008-07-241-0/+5
| | | | as load/store offset.
* gas/Bernd Schmidt2008-03-261-19/+21
| | | | | | | | | | | | | | | | | | | | | * config/bfin-parse.y (check_macfunc_option): Allow (IU) option for multiply and multiply-accumulate to data register instruction. (check_macfuncs): Don't check if accumulator matches the data register here. (assign_macfunc): Check if accumulator matches the data register in each rule that moves to the data register. gas/testsuite/ * gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check for IU option. * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add check for mismatch of accumulator and data register. opcodes/ * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for multiply and multiply-accumulate to data register instruction.
* gas/:Bernd Schmidt2008-03-261-6/+47
| | | | | | | | | | | | | | | | | | | | | * config/bfin-parse.y (check_macfunc_option): New. (check_macfuncs): Check option by calling check_macfunc_option. Fix comparison always true warnings. Both scalar instructions of vector instruction must share the same mode option. Only allow option mode at the end of the second instruction of the vector. (asm_1): Check option by calling check_macfunc_option. gas/testsuite/: * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add tests for bad options of "multiply and multipy-accumulate to accumulator" instructions. Add new vector instruction option mode tests. * gas/bfin/vector2.s: Add new vector instruction option mode test. * gas/bfin/vector2.d: Adjust accordingly. * gas/bfin/expected_errors.s, gas/bfin/expected_errors.l: Add test for mismatched half registers in vector multipy-accumulate instructions.
* gas/Bernd Schmidt2008-03-261-7/+9
| | | | | | | | | | | | From Jie Zhang <jie.zhang@analog.com> * config/bfin-parse.y (asm_1): Check AREGS in comparison instructions. And call yyerror () when comparing PREG with DREG. gas/testsuite/: * gas/bfin/expected_comparison_errors.l: New test. * gas/bfin/expected_comparison_errors.s: New test. * gas/bfin/bfin.exp: Add expected_comparison_errors.
* * config/bfin-parse.y (asm_1): Slightly improve error messagesBernd Schmidt2007-09-181-0/+2
| | | | for "reg += const;".
* Switch to GPLv3Nick Clifton2007-07-031-2/+2
|
* * config/bfin-parse.y (binary): Change sub of const to add of negatedBernd Schmidt2006-09-181-0/+6
| | | | const.
* * config/bfin-parse.y (binary): Do some more constant folding forBernd Schmidt2006-09-151-6/+21
| | | | additions.
* remove some duplicate #include's.Alan Modra2006-06-071-3/+2
|
* * config/bfin-parse.y (check_macfunc): Loose the condition ofJie Zhang2006-05-281-2/+3
| | | | calling check_multiply_halfregs ().
* * config/bfin-parse.y (asm_1): Better check and deal withJie Zhang2006-05-251-38/+38
| | | | vector and scalar Multiply 16-Bit Operands instructions.
OpenPOWER on IntegriCloud