diff options
Diffstat (limited to 'sim')
35 files changed, 14758 insertions, 121 deletions
diff --git a/sim/testsuite/sim/h8300/addb.s b/sim/testsuite/sim/h8300/addb.s new file mode 100644 index 0000000000..f1e4ebf726 --- /dev/null +++ b/sim/testsuite/sim/h8300/addb.s @@ -0,0 +1,778 @@ +# Hitachi H8 testcase 'add.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.b #xx:8, rd ; 8 rd xxxxxxxx + # add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx + # add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx + # add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx + # add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx + # add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx + # add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx + # add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx + # add.b rs, rd ; 0 8 rs rd + # add.b reg8, @erd ; 7 d rd ???? 0 8 rs ???? + # add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs + # add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs + # add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs + # add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs + # add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16 + # add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32 + # add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ???? + # add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ???? + # add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ???? + # + + # Coming soon: + # add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx + # add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8 + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0 +post_byte: .byte 0 + + start + +add_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.b #xx:8,Rd + add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd + mov #byte_dest, er0 + add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #5, r0l + beq .L1 + fail +.L1: + +add_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd+ + mov #byte_dest, er0 + add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #10, r0l + beq .L2 + fail +.L2: + +add_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@eRd- + mov #byte_dest, er0 + add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #15, r0l + beq .L3 + fail +.L3: + +add_b_imm8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@+eRd + mov #pre_byte, er0 + add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #20, r0l + beq .L4 + fail +.L4: + +add_b_imm8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@-eRd + mov #post_byte, er0 + add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #25, r0l + beq .L5 + fail +.L5: + +add_b_imm8_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@(dd:16, eRd) + mov #post_byte, er0 + add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest. +;;; .word 0x0174 +;;; .word 0x6e08 +;;; .word 0xffff +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #30, r0l + beq .L6 + fail +.L6: + +add_b_imm8_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@(dd:32, eRd) + mov #pre_byte, er0 + add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest. +;;; .word 0x7804 +;;; .word 0x6a28 +;;; .word 0x0000 +;;; .word 0x0001 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #35, r0l + beq .L7 + fail +.L7: + +add_b_imm8_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:8 + ;; NOTE: for abs8, we will use the SBR register as a base, + ;; since otherwise we would have to make sure that the destination + ;; was in the zero page. + ;; + mov #byte_dest-100, er0 + ldc er0, sbr + add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest +;;; .word 0x7f64 +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-100, er0 ; reg 0 has base address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #40, r0l + beq .L8 + fail +.L8: + +add_b_imm8_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@aa:16 + add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #45, r0l + beq .L9 + fail +.L9: + +add_b_imm8_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b #xx:8,@aa:32 + add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x8005 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #50, r0l + beq .L10 + fail +.L10: + +.endif + +add_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.b Rs,Rd + mov.b #5, r0h + add.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x05aa r0 ; add result: a5 + 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd ; Add to register indirect + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x0890 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #55, r0l + beq .L11 + fail +.L11: + +add_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd+ ; Add to register post-increment + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #60, r0l + beq .L12 + fail +.L12: + +add_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@eRd- ; Add to register post-decrement + mov #byte_dest, er0 + mov #5, r1l + add.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #65, r0l + beq .L13 + fail +.L13: + +add_b_reg8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@+eRd ; Add to register pre-increment + mov #pre_byte, er0 + mov #5, r1l + add.b r1l, @+er0 ; reg8 src, reg pre-incr dest +;;; .word 0x0179 +;;; .word 0x9019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #70, r0l + beq .L14 + fail +.L14: + +add_b_reg8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@-eRd ; Add to register pre-decrement + mov #post_byte, er0 + mov #5, r1l + add.b r1l, @-er0 ; reg8 src, reg pre-decr dest +;;; .word 0x0179 +;;; .word 0xb019 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #75, r0l + beq .L15 + fail +.L15: + +add_b_reg8_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement + mov #pre_byte, er0 + mov #5, r1l + add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest +;;; .word 0x0179 +;;; .word 0xc019 +;;; .word 0x0001 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #80, r0l + beq .L16 + fail +.L16: + +add_b_reg8_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement + mov #post_byte, er0 + mov #5, r1l + add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest +;;; .word 0x0179 +;;; .word 0xd819 +;;; .word 0xffff +;;; .word 0xffff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #85, r0l + beq .L17 + fail +.L17: + +add_b_reg8_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:8 + ;; NOTE: for abs8, we will use the SBR register as a base, + ;; since otherwise we would have to make sure that the destination + ;; was in the zero page. + ;; + mov #byte_dest-100, er0 + ldc er0, sbr + mov #5, r1l + add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest +;;; .word 0x7f64 +;;; .word 0x0890 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest-100, er0 ; reg 0 has base address + test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #90, r0l + beq .L18 + fail +.L18: + +add_b_reg8_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:16 + mov #5, r0l + add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest +;;; .word 0x6a18 +;;; .word byte_dest +;;; .word 0x0880 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #95, r0l + beq .L19 + fail +.L19: + +add_b_reg8_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.b reg8,@aa:32 + mov #5, r0l + add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest +;;; .word 0x6a38 +;;; .long byte_dest +;;; .word 0x0880 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the add to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #100, r0l + beq .L20 + fail +.L20: + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/addl.s b/sim/testsuite/sim/h8300/addl.s new file mode 100644 index 0000000000..586fcf64f2 --- /dev/null +++ b/sim/testsuite/sim/h8300/addl.s @@ -0,0 +1,1865 @@ +# Hitachi H8 testcase 'add.l' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.l xx:3, erd + # add.l xx:16, erd + # add.l xx:32, erd + # add.l xx:16, @erd + # add.l xx:16, @erd+ + # add.l xx:16, @erd- + # add.l xx:16, @+erd + # add.l xx:16, @-erd + # add.l xx:16, @(dd:2, erd) + # add.l xx:16, @(dd:16, erd) + # add.l xx:16, @(dd:32, erd) + # add.l xx:16, @aa:16 + # add.l xx:16, @aa:32 + # add.l xx:32, @erd+ + # add.l xx:32, @erd- + # add.l xx:32, @+erd + # add.l xx:32, @-erd + # add.l xx:32, @(dd:2, erd) + # add.l xx:32, @(dd:16, erd) + # add.l xx:32, @(dd:32, erd) + # add.l xx:32, @aa:16 + # add.l xx:32, @aa:32 + # add.l ers, erd + # add.l ers, @erd + # add.l ers, @erd+ + # add.l ers, @erd- + # add.l ers, @+erd + # add.l ers, @-erd + # add.l ers, @(dd:2, erd) + # add.l ers, @(dd:16, erd) + # add.l ers, @(dd:32, erd) + # add.l ers, @aa:16 + # add.l ers, @aa:32 + # add.l ers, erd + # add.l @ers, erd + # add.l @ers+, erd + # add.l @ers-, erd + # add.l @+ers, erd + # add.l @-ers, erd + # add.l @(dd:2, ers), erd + # add.l @(dd:16, ers), erd + # add.l @(dd:32, ers), erd + # add.l @aa:16, erd + # add.l @aa:32, erd + # add.l @ers, @erd + # add.l @ers+, @erd+ + # add.l @ers-, @erd- + # add.l @+ers, +@erd + # add.l @-ers, @-erd + # add.l @(dd:2, ers), @(dd:2, erd) + # add.l @(dd:16, ers), @(dd:16, erd) + # add.l @(dd:32, ers), @(dd:32, erd) + # add.l @aa:16, @aa:16 + # add.l @aa:32, @aa:32 + + start + + .data + .align 4 +long_src: + .long 0x12345678 +long_dst: + .long 0x87654321 + + .text + + ;; + ;; Add long from immediate source + ;; + +.if (sim_cpu == h8sx) +add_l_imm3_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:3, erd + add.l #0x3:3, er0 ; Immediate 16-bit operand +;;; .word 0x0ab8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a5a8 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_imm16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, erd + add.l #0x1234, er0 ; Immediate 16-bit operand +;;; .word 0x7a18 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5b7d9 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +add_l_imm32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, erd + add.l #0x12345678, er0 ; Immediate 32-bit operand +;;; .word 0x7a10 +;;; .long 0x12345678 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_l_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd + mov.l #long_dst, er1 + add.l #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x010e +;;; .word 0x0110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext11 + fail +.Lnext11: + mov.l #0x87654321, @long_dst ; Initialize it again for the next use. + +add_l_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd+ + mov.l #long_dst, er1 + add.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x010e +;;; .word 0x8110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext12 + fail +.Lnext12: + mov.l #0x87654321, @long_dst ; initialize it again for the next use. + +add_l_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @erd- + mov.l #long_dst, er1 + add.l #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x010e +;;; .word 0xa110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext13 + fail +.Lnext13: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @+erd + mov.l #long_dst-4, er1 + add.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x010e +;;; .word 0x9110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext14 + fail +.Lnext14: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @-erd + mov.l #long_dst+4, er1 + add.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x010e +;;; .word 0xb110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext15 + fail +.Lnext15: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x010e +;;; .word 0x3110 +;;; .word 0xdead + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext16 + fail +.Lnext16: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010e +;;; .word 0xc110 +;;; .word 0xdead +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext17 + fail +.Lnext17: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010e +;;; .word 0xc910 +;;; .word 0xdead +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext18 + fail +.Lnext18: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @aa:16 + add.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4010 +;;; .word 0xdead +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext19 + fail +.Lnext19: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:16, @aa:32 + add.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4810 +;;; .word 0xdead +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x876621ce, @long_dst + beq .Lnext20 + fail +.Lnext20: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1 ; Register indirect operand +;;; .word 0x010e +;;; .word 0x0118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext21 + fail +.Lnext21: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_postinc: ; post-increment from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd+ + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. +;;; .word 0x010e +;;; .word 0x8118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext22 + fail +.Lnext22: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_postdec: ; post-decrement from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @erd- + mov.l #long_dst, er1 + add.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. +;;; .word 0x010e +;;; .word 0xa118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext23 + fail +.Lnext23: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @+erd + mov.l #long_dst-4, er1 + add.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands +;;; .word 0x010e +;;; .word 0x9118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext24 + fail +.Lnext24: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @-erd + mov.l #long_dst+4, er1 + add.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands +;;; .word 0x010e +;;; .word 0xb118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext25 + fail +.Lnext25: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand +;;; .word 0x010e +;;; .word 0x3118 +;;; .long 0xcafedead + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext26 + fail +.Lnext26: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010e +;;; .word 0xc118 +;;; .long 0xcafedead +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext27 + fail +.Lnext27: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010e +;;; .word 0xc918 +;;; .long 0xcafedead +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext28 + fail +.Lnext28: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @aa:16 + add.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4018 +;;; .long 0xcafedead +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext29 + fail +.Lnext29: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_imm32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l #xx:32, @aa:32 + add.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010e +;;; .word 0x4818 +;;; .long 0xcafedead +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x526421ce, @long_dst + beq .Lnext30 + fail +.Lnext30: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. +.endif + + ;; + ;; Add long from register source + ;; + +add_l_reg32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, erd + mov.l #0x12345678, er1 + add.l er1, er0 ; Register 32-bit operand +;;; .word 0x0a90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; add result + test_h_gr32 0x12345678 er1 ; add src unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +add_l_reg32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd + mov.l #long_dst, er1 + add.l er0, @er1 ; Register indirect operand +;;; .word 0x0109 +;;; .word 0x0110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext44 + fail +.Lnext44: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd+ + mov.l #long_dst, er1 + add.l er0, @er1+ ; Register post-incr operand +;;; .word 0x0109 +;;; .word 0x8110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext49 + fail +.Lnext49: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @erd- + mov.l #long_dst, er1 + add.l er0, @er1- ; Register post-decr operand +;;; .word 0x0109 +;;; .word 0xa110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext50 + fail +.Lnext50: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @+erd + mov.l #long_dst-4, er1 + add.l er0, @+er1 ; Register pre-incr operand +;;; .word 0x0109 +;;; .word 0x9110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext51 + fail +.Lnext51: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @-erd + mov.l #long_dst+4, er1 + add.l er0, @-er1 ; Register pre-decr operand +;;; .word 0x0109 +;;; .word 0xb110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext48 + fail +.Lnext48: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:2, erd) + mov.l #long_dst-12, er1 + add.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0109 +;;; .word 0x3110 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext52 + fail +.Lnext52: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:16, erd) + mov.l #long_dst-4, er1 + add.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x0109 +;;; .word 0xc110 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext45 + fail +.Lnext45: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @(dd:32, erd) + mov.l #long_dst-8, er1 + add.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x0109 +;;; .word 0xc910 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext46 + fail +.Lnext46: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @aa:16 + add.l er0, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x0109 +;;; .word 0x4110 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext41 + fail +.Lnext41: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + +add_l_reg32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l ers, @aa:32 + add.l er0, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x0109 +;;; .word 0x4910 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=1 C=1 + test_neg_clear + test_zero_clear + test_ovf_set + test_carry_set + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x2d0ae8c6, @long_dst + beq .Lnext42 + fail +.Lnext42: + mov.l #0x87654321, @long_dst ; Re-initialize it for the next use. + + ;; + ;; Add long to register destination. + ;; + +add_l_indirect_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers, Rd + mov.l #long_src, er1 + add.l @er1, er0 ; Register indirect operand +;;; .word 0x010a +;;; .word 0x0110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_postinc_to_reg32: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers+, erd + mov.l #long_src, er1 + add.l @er1+, er0 ; Register post-incr operand +;;; .word 0x010a +;;; .word 0x8110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src+4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_postdec_to_reg32: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers-, erd + mov.l #long_src, er1 + add.l @er1-, er0 ; Register post-decr operand +;;; .word 0x010a +;;; .word 0xa110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_preinc_to_reg32: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @+ers, erd + mov.l #long_src-4, er1 + add.l @+er1, er0 ; Register pre-incr operand +;;; .word 0x010a +;;; .word 0x9110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_predec_to_reg32: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @-ers, erd + mov.l #long_src+4, er1 + add.l @-er1, er0 ; Register pre-decr operand +;;; .word 0x010a +;;; .word 0xb110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +add_l_disp2_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:2, ers), erd + mov.l #long_src-4, er1 + add.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand +;;; .word 0x010a +;;; .word 0x1110 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_disp16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:16, ers), erd + mov.l #long_src+0x1234, er1 + add.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand +;;; .word 0x010a +;;; .word 0xc110 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_disp32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:32, ers), erd + mov.l #long_src+65536, er1 + add.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand +;;; .word 0x010a +;;; .word 0xc910 +;;; .long -65536 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_abs16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:16, erd + add.l @long_src:16, er0 ; 16-bit address-direct operand +;;; .word 0x010a +;;; .word 0x4010 +;;; .word @long_src + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +add_l_abs32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:32, erd + add.l @long_src:32, er0 ; 32-bit address-direct operand +;;; .word 0x010a +;;; .word 0x4810 +;;; .long @long_src + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xb7d9fc1d er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + + ;; + ;; Add long from memory to memory + ;; + +add_l_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers, @erd + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1, @er0 +;;; .word 0x0104 +;;; .word 0x691c +;;; .word 0x0010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst ; FIXME + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +add_l_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers+, @erd+ + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1+, @er0+ +;;; .word 0x0104 +;;; .word 0x6d1c +;;; .word 0x8010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst+4 er0 + test_h_gr32 long_src+4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +add_l_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @ers-, @erd- + mov.l #long_src, er1 + mov.l #long_dst, er0 + add.l @er1-, @er0- +;;; .word 0x0106 +;;; .word 0x6d1c +;;; .word 0xa010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-4 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +add_l_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @+ers, @+erd + mov.l #long_src-4, er1 + mov.l #long_dst-4, er0 + add.l @+er1, @+er0 +;;; .word 0x0105 +;;; .word 0x6d1c +;;; .word 0x9010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +add_l_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @-ers, @-erd + mov.l #long_src+4, er1 + mov.l #long_dst+4, er0 + add.l @-er1, @-er0 +;;; .word 0x0107 +;;; .word 0x6d1c +;;; .word 0xb010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +add_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:2, ers), @(dd:2, erd) + mov.l #long_src-4, er1 + mov.l #long_dst-8, er0 + add.l @(4:2, er1), @(8:2, er0) +;;; .word 0x0105 +;;; .word 0x691c +;;; .word 0x2010 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-8 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +add_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:16, ers), @(dd:16, erd) + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + add.l @(1:16, er1), @(2:16, er0) +;;; .word 0x0104 +;;; .word 0x6f1c +;;; .word 0x0001 +;;; .word 0xc010 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +add_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @(dd:32, ers), @(dd:32, erd) + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + add.l @(1:32, er1), @(2:32, er0) +;;; .word 0x7894 +;;; .word 0x6b2c +;;; .word 0xc9c8 +;;; .long 1 +;;; .word 0xc810 +;;; .long 2 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +add_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:16, @aa:16 + add.l @long_src:16, @long_dst:16 +;;; .word 0x0104 +;;; .word 0x6b0c +;;; .word @long_src +;;; .word 0x4010 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +add_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; add.l @aa:32, @aa:32 + add.l @long_src:32, @long_dst:32 +;;; .word 0x0104 +;;; .word 0x6b2c +;;; .long @long_src +;;; .word 0x4810 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0x99999999, @long_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.l #0x87654321, @long_dst + cmp.l #0x99999999, @long_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/addw.s b/sim/testsuite/sim/h8300/addw.s new file mode 100644 index 0000000000..c38bf69f12 --- /dev/null +++ b/sim/testsuite/sim/h8300/addw.s @@ -0,0 +1,87 @@ +# Hitachi H8 testcase 'add.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # add.w xx:3, rd ; 0 a 0xxx rd (sx only) + # add.w xx:16, rd ; 7 9 1 rd imm16 + # add.w rs, rd ; 0 9 rs rd + # + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +add_w_imm3: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w #xx:3,Rd ; Immediate 3-bit operand + add.w #7, r0 ; FIXME will not assemble yet +; .word 0x0a70 ; Fake it until assembler will take it. + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7 + test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +add_w_imm16: + ;; add.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w #xx:16,Rd + add.w #0x111, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 + test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +add_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.w Rs,Rd + mov.w #0x111, r1 + add.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111 + test_h_gr16 0x0111 r1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111 + test_h_gr32 0xa5a50111 er1 +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/allinsn.exp b/sim/testsuite/sim/h8300/allinsn.exp index 23e2cc9e21..9f3351bbc7 100644 --- a/sim/testsuite/sim/h8300/allinsn.exp +++ b/sim/testsuite/sim/h8300/allinsn.exp @@ -3,40 +3,43 @@ set all "h8300 h8300h h8300s h8sx" if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then { - run_sim_test add.b.s $all - run_sim_test add.w.s $all - run_sim_test add.l.s $all + run_sim_test addb.s $all + run_sim_test addw.s $all + run_sim_test addl.s $all run_sim_test adds.s $all run_sim_test addx.s $all - run_sim_test and.b.s $all - run_sim_test and.w.s $all - run_sim_test and.l.s $all + run_sim_test andb.s $all + run_sim_test andw.s $all + run_sim_test andl.s $all run_sim_test bfld.s h8sx + run_sim_test brabc.s h8sx run_sim_test bra.s $all run_sim_test bset.s $all - run_sim_test cmp.b.s $all - run_sim_test cmp.w.s $all - run_sim_test cmp.l.s $all + run_sim_test cmpb.s $all + run_sim_test cmpw.s $all + run_sim_test cmpl.s $all run_sim_test daa.s $all run_sim_test das.s $all run_sim_test dec.s $all - run_sim_test ext.w.s $all - run_sim_test ext.l.s $all + run_sim_test extw.s $all + run_sim_test extl.s $all run_sim_test inc.s $all run_sim_test jmp.s $all run_sim_test ldc.s $all + run_sim_test ldm.s $all run_sim_test mac.s $all - run_sim_test mov.b.s $all - run_sim_test mov.w.s $all - run_sim_test mov.l.s $all + run_sim_test mova.s h8sx + run_sim_test movb.s $all + run_sim_test movw.s $all + run_sim_test movl.s $all run_sim_test movmd.s h8sx run_sim_test movsd.s h8sx run_sim_test neg.s $all run_sim_test nop.s $all run_sim_test not.s $all - run_sim_test or.b.s $all - run_sim_test or.w.s $all - run_sim_test or.l.s $all + run_sim_test orb.s $all + run_sim_test orw.s $all + run_sim_test orl.s $all run_sim_test rotl.s $all run_sim_test rotr.s $all run_sim_test rotxl.s $all @@ -46,10 +49,10 @@ if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then { run_sim_test shll.s $all run_sim_test shlr.s $all run_sim_test stc.s $all - run_sim_test sub.b.s $all - run_sim_test sub.w.s $all - run_sim_test sub.l.s $all - run_sim_test xor.b.s $all - run_sim_test xor.w.s $all - run_sim_test xor.l.s $all + run_sim_test subb.s $all + run_sim_test subw.s $all + run_sim_test subl.s $all + run_sim_test xorb.s $all + run_sim_test xorw.s $all + run_sim_test xorl.s $all } diff --git a/sim/testsuite/sim/h8300/andb.s b/sim/testsuite/sim/h8300/andb.s new file mode 100644 index 0000000000..33776748a7 --- /dev/null +++ b/sim/testsuite/sim/h8300/andb.s @@ -0,0 +1,491 @@ +# Hitachi H8 testcase 'and.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # and.b #xx:8, rd ; e rd xxxxxxxx + # and.b #xx:8, @erd ; 7 d rd ???? e ???? xxxxxxxx + # and.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx + # and.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx + # and.b rs, rd ; 1 6 rs rd + # and.b reg8, @erd ; 7 d rd ???? 1 6 rs ???? + # and.b reg8, @erd+ ; 0 1 7 9 8 rd 6 rs + # and.b reg8, @erd- ; 0 1 7 9 a rd 6 rs + # and.b reg8, @+erd ; 0 1 7 9 9 rd 6 rs + # and.b reg8, @-erd ; 0 1 7 9 b rd 6 rs + # + # andc #xx:8, ccr ; 0 6 xxxxxxxx + # andc #xx:8, exr ; 0 1 4 1 0 6 xxxxxxxx + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +and_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.b #xx:8,Rd + and.b #0xaa, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a0 r0 ; and result: a5 & aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; and result: a5 & aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +and_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd + mov #byte_dest, er0 + and.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L1 + fail +.L1: + +and_b_imm8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd+ + mov #byte_dest, er0 + and.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xe055 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L2 + fail +.L2: + +and_b_imm8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@eRd- + mov #byte_dest, er0 + and.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L3 + fail +.L3: + +and_b_imm8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@+eRd + mov #pre_byte, er0 + and.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xe055 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L4 + fail +.L4: + +and_b_imm8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b #xx:8,@-eRd + mov #post_byte, er0 + and.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xe0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L5 + fail +.L5: + + +.endif + +and_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.b Rs,Rd + mov.b #0xaa, r0h + and.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xaaa0 r0 ; and result: a5 & aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5aaa0 er0 ; and result: a5 & aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +and_b_reg8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd ; And to register indirect + mov #byte_dest, er0 + mov #0x55, r1l + and.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1690 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L6 + fail +.L6: + +and_b_reg8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd+ ; And to register post-incr + mov #byte_dest, er0 + mov #0xaa, r1l + and.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8069 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L7 + fail +.L7: + +and_b_reg8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@eRd- ; And to register post-decr + mov #byte_dest, er0 + mov #0x55, r1l + and.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa069 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L8 + fail +.L8: + +and_b_reg8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@+eRd ; And to register post-incr + mov #pre_byte, er0 + mov #0xaa, r1l + and.b r1l, @+er0 ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x9069 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L9 + fail +.L9: + +and_b_reg8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; and.b rs8,@-eRd ; And to register post-decr + mov #post_byte, er0 + mov #0x55, r1l + and.b r1l, @-er0 ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xb069 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the and to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x05, r0l + beq .L10 + fail +.L10: + +andc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; andc #xx:8,ccr + set_ccr 0xff + + test_neg_set + andc #0xf7, ccr ; Immediate 8-bit operand (neg flag) + test_neg_clear + + test_zero_set + andc #0xfb, ccr ; Immediate 8-bit operand (zero flag) + test_zero_clear + + test_ovf_set + andc #0xfd, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_clear + + test_carry_set + andc #0xfe, ccr ; Immediate 8-bit operand (carry flag) + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/andl.s b/sim/testsuite/sim/h8300/andl.s new file mode 100644 index 0000000000..ac09edc121 --- /dev/null +++ b/sim/testsuite/sim/h8300/andl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'and.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +and_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l #xx:16,Rd + and.l #0xaaaa:16, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +and_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l #xx:32,Rd + and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +and_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.l Rs,Rd + mov.l #0xaaaaaaaa, er1 + and.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa + test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/andw.s b/sim/testsuite/sim/h8300/andw.s new file mode 100644 index 0000000000..42671790d7 --- /dev/null +++ b/sim/testsuite/sim/h8300/andw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'and.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +and_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.w #xx:16,Rd + and.w #0xaaaa, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +and_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; and.w Rs,Rd + mov.w #0xaaaa, r1 + and.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa0a0 r0 ; and result: a5a5 & aaaa + test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a0a0 er0 ; and result: a5a5 & aaaa + test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/bra.s b/sim/testsuite/sim/h8300/bra.s index 7da26110d4..2ec10dc2f5 100644 --- a/sim/testsuite/sim/h8300/bra.s +++ b/sim/testsuite/sim/h8300/bra.s @@ -72,8 +72,8 @@ bra_reg8: ;; bra rn.b ; 8-bit register indirect sub.l #src8, @disp8 mov.l @disp8, er5 -;;; bra er5.b - .word 0x5955 + bra r5l.b +;;; .word 0x5955 src8: fail tgt_reg8: @@ -94,8 +94,8 @@ bra_reg16: ;; bra rn.w ; 16-bit register indirect sub.l #src16, @disp16 mov.l @disp16, er5 -;;; bra er5.w - .word 0x5956 + bra r5.w +;;; .word 0x5956 src16: fail tgt_reg16: @@ -116,8 +116,8 @@ bra_reg32: ;; bra ern ; 32-bit register indirect sub.l #src32, @disp32 mov.l @disp32, er5 -;;; bra er5.l - .word 0x5957 + bra er5.l +;;; .word 0x5957 src32: fail tgt_reg32: @@ -134,8 +134,8 @@ tgt_reg32: bra_s: set_grs_a5a5 set_ccr_zero -;;; bra/s tgt_post_delay - .word 0x4017 + bra/s tgt_post_delay +;;; .word 0x4017 ;; The following instruction is in the delay slot, and should execute. mov.b #1, @dslot ;; After this, the next instructions should not execute. diff --git a/sim/testsuite/sim/h8300/cmpb.s b/sim/testsuite/sim/h8300/cmpb.s new file mode 100644 index 0000000000..1a4f23c8b2 --- /dev/null +++ b/sim/testsuite/sim/h8300/cmpb.s @@ -0,0 +1,1086 @@ +# Hitachi H8 testcase 'cmp.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # cmp.b #xx:8, rd ; a rd xxxxxxxx + # cmp.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx + # cmp.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx + # cmp.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx + # cmp.b rs, rd ; 1 c rs rd + # cmp.b reg8, @erd ; 7 d rd ???? 1 c rs ???? + # cmp.b reg8, @erd+ ; 0 1 7 9 8 rd 2 rs + # cmp.b reg8, @erd- ; 0 1 7 9 a rd 2 rs + # cmp.b reg8, @+erd ; 0 1 7 9 9 rd 2 rs + # cmp.b reg8, @-erd ; 0 1 7 9 b rd 2 rs + # cmp.b rsind, rdind ; 7 c 0rs 5 0 ?rd 2 ???? + # cmp.b rspostinc, rdpostinc ; 0 1 7 4 6 c 0rs c 8 ?rd 2 ???? + # cmp.b rspostdec, rdpostdec ; 0 1 7 6 6 c 0rs c a ?rd 2 ???? + # cmp.b rspreinc, rdpreinc ; 0 1 7 5 6 c 0rs c 9 ?rd 2 ???? + # cmp.b rspredec, rdpredec ; 0 1 7 7 6 c 0rs c b ?rd 2 ???? + # cmp.b disp2, disp2 ; 0 1 7 01dd:2 6 8 0rs c 00dd:2 ?rd 2 ???? + # cmp.b disp16, disp16 ; 0 1 7 4 6 e 0rs c dd:16 c 0rd 2 ???? dd:16 + # cmp.b disp32, disp32 ; 7 8 0rs 4 6 a 2 c dd:32 c 1rd 2 ???? dd:32 + # cmp.b indexb16, indexb16 ; 0 1 7 5 6 e 0rs c dd:16 d 0rd 2 ???? dd:16 + # cmp.b indexw16, indexw16 ; 0 1 7 6 6 e 0rs c dd:16 e 0rd 2 ???? dd:16 + # cmp.b indexl16, indexl16 ; 0 1 7 7 6 e 0rs c dd:16 f 0rd 2 ???? dd:16 + # cmp.b indexb32, indexb32 ; 7 8 0rs 5 6 a 2 c dd:32 d 1rd 2 ???? dd:32 + # cmp.b indexw32, indexw32 ; 7 8 0rs 6 6 a 2 c dd:32 e 1rd 2 ???? dd:32 + # cmp.b indexl32, indexl32 ; 7 8 0rs 7 6 a 2 c dd:32 f 1rd 2 ???? dd:32 + # cmp.b abs16, abs16 ; 6 a 1 5 aa:16 4 0??? 2 ???? aa:16 + # cmp.b abs32, abs32 ; 6 a 3 5 aa:32 4 1??? 2 ???? aa:32 + # + + # Coming soon: + + # ... + +.data +byte_src: .byte 0x5a +pre_byte: .byte 0 +byte_dst: .byte 0xa5 +post_byte: .byte 0 + + start + +cmp_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.b #xx:8,Rd + cmp.b #0xa5, r0l ; Immediate 8-bit src, reg8 dest + beq .Leq1 + fail +.Leq1: cmp.b #0xa6, r0l + blt .Llt1 + fail +.Llt1: cmp.b #0xa4, r0l + bgt .Lgt1 + fail +.Lgt1: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +cmp_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xa0a5 + beq .Leq2 + fail +.Leq2: set_ccr_zero + cmp.b #0xa6, @er0 +;;; .word 0x7d00 +;;; .word 0xa0a6 + blt .Llt2 + fail +.Llt2: set_ccr_zero + cmp.b #0xa4, @er0 +;;; .word 0x7d00 +;;; .word 0xa0a4 + bgt .Lgt2 + fail +.Lgt2: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L2 + fail +.L2: + +cmp_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd+ + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0+ ; Immediate 8-bit src, reg postinc dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq3 + fail +.Leq3: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa6, @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt3 + fail +.Llt3: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa4, @er0+ +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt3 + fail +.Lgt3: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L3 + fail +.L3: + +cmp_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@eRd- + mov #byte_dst, er0 + cmp.b #0xa5:8, @er0- ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq4 + fail +.Leq4: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa6, @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt4 + fail +.Llt4: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst, er0 + set_ccr_zero + cmp.b #0xa4, @er0- +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt4 + fail +.Lgt4: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L4 + fail +.L4: + +cmp_b_imm8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@+eRd + mov #pre_byte, er0 + cmp.b #0xa5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq5 + fail +.Leq5: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte, er0 + set_ccr_zero + cmp.b #0xa6, @+er0 +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt5 + fail +.Llt5: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte, er0 + set_ccr_zero + cmp.b #0xa4, @+er0 +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt5 + fail +.Lgt5: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L5 + fail +.L5: + +cmp_b_imm8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b #xx:8,@-eRd + mov #post_byte, er0 + cmp.b #0xa5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a5 + beq .Leq6 + fail +.Leq6: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte, er0 + set_ccr_zero + cmp.b #0xa6, @-er0 +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a6 + blt .Llt6 + fail +.Llt6: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte, er0 + set_ccr_zero + cmp.b #0xa4, @-er0 +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xa0a4 + bgt .Lgt6 + fail +.Lgt6: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L6 + fail +.L6: + + +.endif + +cmp_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.b Rs,Rd + mov.b #0xa5, r0h + cmp.b r0h, r0l ; Reg8 src, reg8 dst + beq .Leq7 + fail +.Leq7: mov.b #0xa6, r0h + cmp.b r0h, r0l + blt .Llt7 + fail +.Llt7: mov.b #0xa4, r0h + cmp.b r0h, r0l + bgt .Lgt7 + fail +.Lgt7: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa4a5 r0 ; r0l unchanged. +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a4a5 er0 ; r0l unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +cmp_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b rs8,@eRd ; cmp reg8 to register indirect + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1c90 + beq .Leq8 + fail +.Leq8: set_ccr_zero + mov #0xa6, r1l + cmp.b r1l, @er0 +;;; .word 0x7d00 +;;; .word 0x1c90 + blt .Llt8 + fail +.Llt8: set_ccr_zero + mov #0xa4, r1l + cmp.b r1l, @er0 +;;; .word 0x7d00 +;;; .word 0x1c90 + bgt .Lgt8 + fail +.Lgt8: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 still contains address + test_h_gr32 0xa5a5a5a4 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (no change). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L8 + fail +.L8: + +cmp_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@eRd+ + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0+ ; Immediate 8-bit src, reg post-incr dst +;;; .word 0x0179 +;;; .word 0x8029 + beq .Leq9 + fail +.Leq9: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @er0+ +;;; .word 0x0179 +;;; .word 0x8029 + blt .Llt9 + fail +.Llt9: test_h_gr32 post_byte er0 ; er0 contains address plus one + mov #byte_dst er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @er0+ +;;; .word 0x0179 +;;; .word 0x8029 + bgt .Lgt9 + fail +.Lgt9: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L9 + fail +.L9: + +cmp_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@eRd- + mov #byte_dst, er0 + mov #0xa5, r1l + cmp.b r1l, @er0- ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0179 +;;; .word 0xa029 + beq .Leq10 + fail +.Leq10: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @er0- +;;; .word 0x0179 +;;; .word 0xa029 + blt .Llt10 + fail +.Llt10: test_h_gr32 pre_byte er0 ; er0 contains address minus one + mov #byte_dst er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @er0- +;;; .word 0x0179 +;;; .word 0xa029 + bgt .Lgt10 + fail +.Lgt10: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L10 + fail +.L10: + +cmp_b_reg8_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@+eRd + mov #pre_byte, er0 + mov #0xa5, r1l + cmp.b r1l, @+er0 ; Immediate 8-bit src, reg post-incr dst +;;; .word 0x0179 +;;; .word 0x9029 + beq .Leq11 + fail +.Leq11: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @+er0 +;;; .word 0x0179 +;;; .word 0x9029 + blt .Llt11 + fail +.Llt11: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #pre_byte er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @+er0 +;;; .word 0x0179 +;;; .word 0x9029 + bgt .Lgt11 + fail +.Lgt11: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L11 + fail +.L11: + +cmp_b_reg8_rdpredec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; cmp.b reg8,@-eRd + mov #post_byte, er0 + mov #0xa5, r1l + cmp.b r1l, @-er0 ; Immediate 8-bit src, reg postdec dst +;;; .word 0x0179 +;;; .word 0xb029 + beq .Leq12 + fail +.Leq12: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte er0 + mov #0xa6, r1l + set_ccr_zero + cmp.b r1l, @-er0 +;;; .word 0x0179 +;;; .word 0xb029 + blt .Llt12 + fail +.Llt12: test_h_gr32 byte_dst er0 ; er0 contains destination address + mov #post_byte er0 + mov #0xa4, r1l + set_ccr_zero + cmp.b r1l, @-er0 +;;; .word 0x0179 +;;; .word 0xb029 + bgt .Lgt12 + fail +.Lgt12: + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dst er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5a4 er1 ; er1 contains test load + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the cmp to memory (memory unchanged). + sub.b r0l, r0l + mov.b @byte_dst, r0l + cmp.b #0xa5, r0l + beq .L12 + fail +.L12: + +cmp_b_rsind_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1, @er2 + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.if 1 ; ambiguous +cmp_b_rspostinc_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1+, @er2+ +;;; .word 0x0174 +;;; .word 0x6c1c +;;; .word 0x8220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src+1 er1 + test_h_gr32 byte_dst+1 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif +.if 1 ; ambiguous +cmp_b_rspostdec_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src, er1 + mov #byte_dst, er2 + set_ccr_zero + cmp.b @er1-, @er2- +;;; .word 0x0176 +;;; .word 0x6c1c +;;; .word 0xa220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-1 er1 + test_h_gr32 byte_dst-1 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_rspreinc_rdpreinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-1, er1 + mov #byte_dst-1, er2 + set_ccr_zero + cmp.b @+er1, @+er2 +;;; .word 0x0175 +;;; .word 0x6c1c +;;; .word 0x9220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_rspredec_predec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src+1, er1 + mov #byte_dst+1, er2 + set_ccr_zero + cmp.b @-er1, @-er2 +;;; .word 0x0177 +;;; .word 0x6c1c +;;; .word 0xb220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src er1 + test_h_gr32 byte_dst er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp2_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-1, er1 + mov #byte_dst-2, er2 + set_ccr_zero + cmp.b @(1:2, er1), @(2:2, er2) +;;; .word 0x0175 +;;; .word 0x681c +;;; .word 0x2220 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-1 er1 + test_h_gr32 byte_dst-2 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp16_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src-3, er1 + mov #byte_dst-4, er2 + set_ccr_zero + cmp.b @(3:16, er1), @(4:16, er2) +;;; .word 0x0174 +;;; .word 0x6e1c +;;; .word 3 +;;; .word 0xc220 +;;; .word 4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src-3 er1 + test_h_gr32 byte_dst-4 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_disp32_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #byte_src+5, er1 + mov #byte_dst+6, er2 + set_ccr_zero + cmp.b @(-5:32, er1), @(-6:32, er2) +;;; .word 0x7814 +;;; .word 0x6a2c +;;; .long -5 +;;; .word 0xca20 +;;; .long -6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 byte_src+5 er1 + test_h_gr32 byte_dst+6 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_indexb16_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffffff01, er1 + mov #0xffffff02, er2 + set_ccr_zero + cmp.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r2.b) +;;; .word 0x0175 +;;; .word 0x6e1c +;;; .word byte_src-1 +;;; .word 0xd220 +;;; .word byte_dst-2 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffffff01 er1 + test_h_gr32 0xffffff02 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.if 1 ; ambiguous +cmp_b_indexw16_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffff0003, er1 + mov #0xffff0004, er2 + set_ccr_zero + cmp.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r2.w) +;;; .word 0x0176 +;;; .word 0x6e1c +;;; .word byte_src-3 +;;; .word 0xe220 +;;; .word byte_dst-4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffff0003 er1 + test_h_gr32 0xffff0004 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_indexl16_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0x00000005, er1 + mov #0x00000006, er2 + set_ccr_zero + cmp.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er2.l) +;;; .word 0x0177 +;;; .word 0x6e1c +;;; .word byte_src-5 +;;; .word 0xf220 +;;; .word byte_dst-6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000005 er1 + test_h_gr32 0x00000006 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_indexb32_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffffff01, er1 + mov #0xffffff02, er2 + set_ccr_zero + cmp.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r2.b) +;;; .word 0x7815 +;;; .word 0x6a2c +;;; .long byte_src-1 +;;; .word 0xda20 +;;; .long byte_dst-2 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffffff01 er1 + test_h_gr32 0xffffff02 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +.if 1 ; ambiguous +cmp_b_indexw32_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0xffff0003, er1 + mov #0xffff0004, er2 + set_ccr_zero + cmp.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r2.w) +;;; .word 0x7816 +;;; .word 0x6a2c +;;; .long byte_src-3 +;;; .word 0xea20 +;;; .long byte_dst-4 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0xffff0003 er1 + test_h_gr32 0xffff0004 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 +.endif + +cmp_b_indexl32_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov #0x00000005, er1 + mov #0x00000006, er2 + set_ccr_zero + cmp.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er2.l) +;;; .word 0x7817 +;;; .word 0x6a2c +;;; .long byte_src-5 +;;; .word 0xfa20 +;;; .long byte_dst-6 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_gr_a5a5 0 + test_h_gr32 0x00000005 er1 + test_h_gr32 0x00000006 er2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_abs16_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + cmp.b @byte_src:16, @byte_dst:16 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_grs_a5a5 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +cmp_b_abs32_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + cmp.b @byte_src:32, @byte_dst:32 + + test_neg_clear ; N=0, Z=0, V=1, C=0 + test_zero_clear + test_ovf_set + test_carry_clear + + test_grs_a5a5 + cmp.b #0x5a, @byte_src:16 + bne fail1 + cmp.b #0xa5, @byte_dst:16 + bne fail1 + +.endif + pass + + exit 0 + +fail1: fail diff --git a/sim/testsuite/sim/h8300/cmpl.s b/sim/testsuite/sim/h8300/cmpl.s new file mode 100644 index 0000000000..55f235a2ee --- /dev/null +++ b/sim/testsuite/sim/h8300/cmpl.s @@ -0,0 +1,106 @@ +# Hitachi H8 testcase 'cmp.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +cmp_l_imm3: ; + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l #xx:3,eRd ; Immediate 3-bit operand + mov.l #5, er0 + cmp.l #5, er0 + beq eq3 + fail +eq3: + cmp.l #6, er0 + blt lt3 + fail +lt3: + cmp.l #4, er0 + bgt gt3 + fail +gt3: + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x00000005 er0 ; er0 unchanged + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +cmp_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l #xx:8,Rd + cmp.l #0xa5a5a5a5, er0 ; Immediate 16-bit operand + beq eqi + fail +eqi: cmp.l #0xa5a5a5a6, er0 + blt lti + fail +lti: cmp.l #0xa5a5a5a4, er0 + bgt gti + fail +gti: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +cmp_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.l Rs,Rd + mov.l #0xa5a5a5a5, er1 + cmp.l er1, er0 ; Register operand + beq eqr + fail +eqr: mov.l #0xa5a5a5a6, er1 + cmp.l er1, er0 + blt ltr + fail +ltr: mov.l #0xa5a5a5a4, er1 + cmp.l er1, er0 + bgt gtr + fail +gtr: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged + test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/cmpw.s b/sim/testsuite/sim/h8300/cmpw.s new file mode 100644 index 0000000000..2c69dbda37 --- /dev/null +++ b/sim/testsuite/sim/h8300/cmpw.s @@ -0,0 +1,110 @@ +# Hitachi H8 testcase 'cmp.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +cmp_w_imm3: ; + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w #xx:3,Rd ; Immediate 3-bit operand + mov.w #5, r0 + cmp.w #5, r0 + beq eq3 + fail +eq3: + cmp.w #6, r0 + blt lt3 + fail +lt3: + cmp.w #4, r0 + bgt gt3 + fail +gt3: + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0xa5a50005 er0 ; er0 unchanged + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +cmp_w_imm16: ; cmp.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w #xx:8,Rd + cmp.w #0xa5a5, r0 ; Immediate 16-bit operand + beq eqi + fail +eqi: cmp.w #0xa5a6, r0 + blt lti + fail +lti: cmp.w #0xa5a4, r0 + bgt gti + fail +gti: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +cmp_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; cmp.w Rs,Rd + mov.w #0xa5a5, r1 + cmp.w r1, r0 ; Register operand + beq eqr + fail +eqr: mov.w #0xa5a6, r1 + cmp.w r1, r0 + blt ltr + fail +ltr: mov.w #0xa5a4, r1 + cmp.w r1, r0 + bgt gtr + fail +gtr: + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a5 r0 ; r0 unchanged. + test_h_gr16 0xa5a4 r1 ; r1 unchanged. +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged + test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/extl.s b/sim/testsuite/sim/h8300/extl.s new file mode 100644 index 0000000000..001f6d3545 --- /dev/null +++ b/sim/testsuite/sim/h8300/extl.s @@ -0,0 +1,1146 @@ +# Hitachi H8 testcase 'exts.l, extu.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +pos: .long 0xffff0001 +neg: .long 0x00008000 + +pos2: .long 0xffffff01 +neg2: .long 0x00000080 + + .text + +exts_l_reg32_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l ern32 + mov.w #1, r0 + exts.l er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x00000001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_reg32_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l ern32 + mov.w #0xffff, r0 + exts.l er0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_l_reg32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l ern32 + mov.w #0xffff, r0 + extu.l er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x0000ffff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +exts_l_ind_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32 + mov.l #pos, er1 + exts.l @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslindp + fail +.Lslindp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32 + mov.l #neg, er1 + exts.l @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslindn + fail +.Lslindn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32 + mov.l #neg, er1 + extu.l @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulindn + fail +.Lulindn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_postinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32+ + mov.l #pos, er1 + exts.l @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpostincp + fail +.Lslpostincp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32+ + mov.l #neg, er1 + exts.l @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpostincn + fail +.Lslpostincn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32+ + mov.l #neg, er1 + extu.l @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpostincn + fail +.Lulpostincn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_postdec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32- + mov.l #pos, er1 + exts.l @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpostdecp + fail +.Lslpostdecp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @ern32- + mov.l #neg, er1 + exts.l @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpostdecn + fail +.Lslpostdecn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @ern32- + mov.l #neg, er1 + extu.l @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-4 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpostdecn + fail +.Lulpostdecn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_preinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @+ern32 + mov.l #pos-4, er1 + exts.l @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpreincp + fail +.Lslpreincp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @+ern32 + mov.l #neg-4, er1 + exts.l @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpreincn + fail +.Lslpreincn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @+ern32 + mov.l #neg-4, er1 + extu.l @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpreincn + fail +.Lulpreincn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +exts_l_predec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @-ern32 + mov.l #pos+4, er1 + exts.l @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos + beq .Lslpredecp + fail +.Lslpredecp: + mov.l #0xffff0001, @pos ; Restore initial value + +exts_l_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l @-ern32 + mov.l #neg+4, er1 + exts.l @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffff8000, @neg + beq .Lslpredecn + fail +.Lslpredecn: +;;; Note: leave the value as 0xffff8000, so that extu has work to do. + +extu_l_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @-ern32 + mov.l #neg+4, er1 + extu.l @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulpredecn + fail +.Lulpredecn: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:2, ern32) + mov.l #neg-8, er1 + extu.l @(8:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-8 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp2n + fail +.Luldisp2n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:16, ern32) + mov.l #neg-44, er1 + extu.l @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-44 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp16n + fail +.Luldisp16n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_disp32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @(dd:32, ern32) + mov.l #neg+444, er1 + extu.l @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+444 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Luldisp32n + fail +.Luldisp32n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_abs16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @aa:16 + extu.l @neg:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulabs16n + fail +.Lulabs16n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + +extu_l_abs32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l @aa:32 + extu.l @neg:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00008000, @neg + beq .Lulabs32n + fail +.Lulabs32n: +;;; Note: leave the value as 0x00008000, so that extu has work to do. + + + + # + # exts #2, nn + # + +exts_l_reg32_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, ern32 + mov.b #1, r0l + exts.l #2, er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x00000001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_reg32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, ern32 + mov.b #0xff, r0l + exts.l #2, er0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 0xffffffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_l_reg32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, ern32 + mov.b #0xff, r0l + extu.l #2, er0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0x000000ff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_l_ind_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32 + mov.l #pos2, er1 + exts.l #2, @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslindp2 + fail +.Lslindp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_ind_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32 + mov.l #neg2, er1 + exts.l #2, @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslindn2 + fail +.Lslindn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_ind_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32 + mov.l #neg2, er1 + extu.l #2, @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulindn2 + fail +.Lulindn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_postinc_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32+ + mov.l #pos2, er1 + exts.l #2, @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2+4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpostincp2 + fail +.Lslpostincp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_postinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32+ + mov.l #neg2, er1 + exts.l #2, @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2+4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpostincn2 + fail +.Lslpostincn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_postinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32+ + mov.l #neg2, er1 + extu.l #2, @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2+4 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpostincn2 + fail +.Lulpostincn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_postdec_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32- + mov.l #pos2, er1 + exts.l #2, @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2-4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpostdecp2 + fail +.Lslpostdecp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_postdec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @ern32- + mov.l #neg2, er1 + exts.l #2, @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2-4 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpostdecn2 + fail +.Lslpostdecn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_postdec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @ern32- + mov.l #neg2, er1 + extu.l #2, @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-4 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpostdecn2 + fail +.Lulpostdecn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_preinc_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @+ern32 + mov.l #pos2-4, er1 + exts.l #2, @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpreincp2 + fail +.Lslpreincp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_preinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @+ern32 + mov.l #neg2-4, er1 + exts.l #2, @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpreincn2 + fail +.Lslpreincn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_preinc_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @+ern32 + mov.l #neg2-4, er1 + extu.l #2, @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpreincn2 + fail +.Lulpreincn2: +;;; Note: leave the value as 0x00000080, like it started out. + +exts_l_predec_2_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @-ern32 + mov.l #pos2+4, er1 + exts.l #2, @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000001, @pos2 + beq .Lslpredecp2 + fail +.Lslpredecp2: + mov.l #0xffffff01, @pos2 ; Restore initial value + +exts_l_predec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.l #2, @-ern32 + mov.l #neg2+4, er1 + exts.l #2, @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_ovf_clear + test_zero_clear + test_carry_clear + + test_h_gr32 neg2 er1 ; result of sign extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0xffffff80, @neg2 + beq .Lslpredecn2 + fail +.Lslpredecn2: +;;; Note: leave the value as 0xffffff80, so that extu has work to do. + +extu_l_predec_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @-ern32 + mov.l #neg2+4, er1 + extu.l #2, @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulpredecn2 + fail +.Lulpredecn2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp2_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:2, ern32) + mov.l #neg2-8, er1 + extu.l #2, @(8:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-8 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp2n2 + fail +.Luldisp2n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp16_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:16, ern32) + mov.l #neg2-44, er1 + extu.l #2, @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2-44 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp16n2 + fail +.Luldisp16n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_disp32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @(dd:32, ern32) + mov.l #neg2+444, er1 + extu.l #2, @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg2+444 er1 ; result of zero extend + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Luldisp32n2 + fail +.Luldisp32n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_abs16_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @aa:16 + extu.l #2, @neg2:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulabs16n2 + fail +.Lulabs16n2: +;;; Note: leave the value as 0x00000080, like it started out. + +extu_l_abs32_2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.l #2, @aa:32 + extu.l #2, @neg2:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.l #0x00000080, @neg2 + beq .Lulabs32n2 + fail +.Lulabs32n2: +;;; Note: leave the value as 0x00000080, like it started out. + +.endif + + pass + + exit 0 + + + + diff --git a/sim/testsuite/sim/h8300/extw.s b/sim/testsuite/sim/h8300/extw.s new file mode 100644 index 0000000000..b1eb491b42 --- /dev/null +++ b/sim/testsuite/sim/h8300/extw.s @@ -0,0 +1,580 @@ +# Hitachi H8 testcase 'exts.w, extu.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 2 +pos: .word 0xff01 +neg: .word 0x0080 + + .text + +exts_w_reg16_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w rn16 + mov.b #1, r0l + exts.w r0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0xa5a50001 er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +exts_w_reg16_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w rn16 + mov.b #0xff, r0l + exts.w r0 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5ffff er0 ; result of sign extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +extu_w_reg16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w rn16 + mov.b #0xff, r0l + extu.w r0 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 0xa5a500ff er0 ; result of zero extend + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +exts_w_ind_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern + mov.l #pos, er1 + exts.w @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswindp + fail +.Lswindp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern + mov.l #neg, er1 + exts.w @er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswindn + fail +.Lswindn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_ind_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern + mov.l #neg, er1 + extu.w @er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwindn + fail +.Luwindn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_postinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern+ + mov.l #pos, er1 + exts.w @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpostincp + fail +.Lswpostincp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern+ + mov.l #neg, er1 + exts.w @er1+ + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg+2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpostincn + fail +.Lswpostincn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_postinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern+ + mov.l #neg, er1 + extu.w @er1+ + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpostincn + fail +.Luwpostincn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_postdec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern- + mov.l #pos, er1 + exts.w @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpostdecp + fail +.Lswpostdecp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @ern- + mov.l #neg, er1 + exts.w @er1- + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpostdecn + fail +.Lswpostdecn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_postdec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @ern- + mov.l #neg, er1 + extu.w @er1- + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpostdecn + fail +.Luwpostdecn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_preinc_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @+ern + mov.l #pos-2, er1 + exts.w @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpreincp + fail +.Lswpreincp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @+ern + mov.l #neg-2, er1 + exts.w @+er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpreincn + fail +.Lswpreincn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_preinc_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @+ern + mov.l #neg-2, er1 + extu.w @+er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpreincn + fail +.Luwpreincn: + ;; Note: leave the value as 0x0080, like it started out. + +exts_w_predec_p: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @-ern + mov.l #pos+2, er1 + exts.w @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 pos er1 ; er1 still contains target address plus 2 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0001, @pos + beq .Lswpredecp + fail +.Lswpredecp: + mov.w #0xff01, @pos ; Restore initial value + +exts_w_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; exts.w @-ern + mov.l #neg+2, er1 + exts.w @-er1 + + ;; Test ccr H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0xff80, @neg + beq .Lswpredecn + fail +.Lswpredecn: + ;; Note: leave the value as 0xff80, so that extu has work to do. + +extu_w_predec_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @-ern + mov.l #neg+2, er1 + extu.w @-er1 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwpredecn + fail +.Luwpredecn: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp2_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:2, ern) + mov.l #neg-2, er1 + extu.w @(2:2, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-2 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp2n + fail +.Luwdisp2n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:16, ern) + mov.l #neg-44, er1 + extu.w @(44:16, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg-44 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp16n + fail +.Luwdisp16n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_disp32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @(dd:32, ern) + mov.l #neg+444, er1 + extu.w @(-444:32, er1) + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_h_gr32 neg+444 er1 ; er1 still contains target address + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwdisp32n + fail +.Luwdisp32n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_abs16_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @aa:16 + extu.w @neg:16 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwabs16n + fail +.Luwabs16n: + ;; Note: leave the value as 0x0080, like it started out. + +extu_w_abs32_n: + set_grs_a5a5 + set_ccr_zero + ;; extu.w @aa:32 + extu.w @neg:32 + + ;; Test ccr H=0 N=0 Z=0 V=0 C=0 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + cmp.w #0x0080, @neg + beq .Luwabs32n + fail +.Luwabs32n: + ;; Note: leave the value as 0x0080, like it started out. + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/ldc.s b/sim/testsuite/sim/h8300/ldc.s index 4e9765a8e2..3712a6c49e 100644 --- a/sim/testsuite/sim/h8300/ldc.s +++ b/sim/testsuite/sim/h8300/ldc.s @@ -270,8 +270,8 @@ ldc_postinc_ccr: ldc @er1+, ccr ; postinc src stc ccr, r0l ; copy into general reg - test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. - test_h_gr32 byte_post, er1 ; er1 still contains address + test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere. + test_h_gr32 byte_src+2, er1 ; er1 still contains address test_gr_a5a5 2 ; Make sure other general regs not disturbed test_gr_a5a5 3 test_gr_a5a5 4 @@ -288,8 +288,8 @@ ldc_postinc_exr: ldc @er1+, exr ; postinc src stc exr, r0l ; copy into general reg - test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. - test_h_gr32 byte_post, er1 ; er1 still contains address + test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere. + test_h_gr32 byte_src+2, er1 ; er1 still contains address test_gr_a5a5 2 ; Make sure other general regs not disturbed test_gr_a5a5 3 test_gr_a5a5 4 diff --git a/sim/testsuite/sim/h8300/ldm.s b/sim/testsuite/sim/h8300/ldm.s new file mode 100644 index 0000000000..c26349fe61 --- /dev/null +++ b/sim/testsuite/sim/h8300/ldm.s @@ -0,0 +1,234 @@ +# Hitachi H8 testcase 'ldm', 'stm' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + .data + .align 4 +_stack: .long 0,1,2,3,4,5,6,7,8,9,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + .long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 +_stack_top: + + start + +.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr +stm_2reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #2, er2 + mov #3, er3 + + set_ccr_zero + stm er2-er3, @-sp + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_h_gr32 2 er2 + test_h_gr32 3 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack_top-8, er7 + + mov @_stack_top-4, er0 + cmp #2, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #3, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #0, er0 + bne fail1 + +stm_3reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #4, er4 + mov #5, er5 + mov #6, er6 + + set_ccr_zero + stm er4-er6, @-sp + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 4 er4 + test_h_gr32 5 er5 + test_h_gr32 6 er6 + test_h_gr32 _stack_top-12, er7 + + mov @_stack_top-4, er0 + cmp #4, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #5, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #6, er0 + bne fail1 + + mov @_stack_top-16, er0 + cmp #0, er0 + bne fail1 + +stm_4reg: + set_grs_a5a5 + mov #_stack_top, er7 + mov #1, er0 + mov #2, er1 + mov #3, er2 + mov #4, er3 + + set_ccr_zero + stm er0-er3, @-sp + test_cc_clear + + test_h_gr32 1 er0 + test_h_gr32 2 er1 + test_h_gr32 3 er2 + test_h_gr32 4 er3 + test_gr_a5a5 4 ; Make sure other general regs not disturbed + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack_top-16, er7 + + mov @_stack_top-4, er0 + cmp #1, er0 + bne fail1 + + mov @_stack_top-8, er0 + cmp #2, er0 + bne fail1 + + mov @_stack_top-12, er0 + cmp #3, er0 + bne fail1 + + mov @_stack_top-16, er0 + cmp #4, er0 + bne fail1 + + mov @_stack_top-20, er0 + cmp #0, er0 + bne fail1 + +ldm_2reg: + set_grs_a5a5 + mov #_stack, er7 + + set_ccr_zero + ldm @sp+, er2-er3 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_h_gr32 1 er2 + test_h_gr32 0 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack+8, er7 + +ldm_3reg: + set_grs_a5a5 + mov #_stack+4, er7 + + set_ccr_zero + ldm @sp+, er4-er6 + test_cc_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_h_gr32 3 er4 + test_h_gr32 2 er5 + test_h_gr32 1 er6 + test_h_gr32 _stack+16, er7 + +ldm_4reg: + set_grs_a5a5 + mov #_stack+4, er7 + + set_ccr_zero + ldm @sp+, er0-er3 + test_cc_clear + + test_h_gr32 4 er0 + test_h_gr32 3 er1 + test_h_gr32 2 er2 + test_h_gr32 1 er3 + test_gr_a5a5 4 ; Make sure other general regs not disturbed + test_gr_a5a5 5 + test_gr_a5a5 6 + test_h_gr32 _stack+20, er7 +.endif + +.if (sim_cpu == h8300) + set_grs_a5a5 + mov #_stack_top, r7 + mov #12, r1 + mov #34, r2 + mov #56, r3 + push r1 + push r2 + push r3 + pop r4 + pop r5 + pop r6 + + test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed + test_h_gr16 12 r1 + test_h_gr16 34 r2 + test_h_gr16 56 r3 + test_h_gr16 56 r4 + test_h_gr16 34 r5 + test_h_gr16 12 r6 + mov #_stack_top, r0 + cmp.w r0, r7 + bne fail1 +.else +pushpop: + set_grs_a5a5 + mov #_stack_top, er7 + mov #12, er1 + mov #34, er2 + mov #56, er3 + push er1 + push er2 + push er3 + pop er4 + pop er5 + pop er6 + + test_gr_a5a5 0 ; Make sure other general _reg_ not disturbed + test_h_gr32 12 er1 + test_h_gr32 34 er2 + test_h_gr32 56 er3 + test_h_gr32 56 er4 + test_h_gr32 34 er5 + test_h_gr32 12 er6 + test_h_gr32 _stack_top, er7 +.endif + + pass + + exit 0 + +fail1: fail diff --git a/sim/testsuite/sim/h8300/mova.s b/sim/testsuite/sim/h8300/mova.s new file mode 100644 index 0000000000..03c6adca0e --- /dev/null +++ b/sim/testsuite/sim/h8300/mova.s @@ -0,0 +1,209 @@ +# Hitachi H8 testcase 'mova' +# mach(): h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +movabl16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa5a6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movabl32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/b.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0xa5a6 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b4b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movawl32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/w.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x14b4b er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall16_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:16, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x295 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall16_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:16, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x29695 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall32_reg8: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:32, r2l.b), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x295 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +movall32_reg16: + set_grs_a5a5 + set_ccr_zero + + mova/l.l @(1:32, r2.w), er3 + + test_cc_clear + test_gr_a5a5 0 ; Make sure other regs not affected + test_gr_a5a5 1 + test_gr_a5a5 2 + test_h_gr32 0x29695 er3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/movb.s b/sim/testsuite/sim/h8300/movb.s new file mode 100644 index 0000000000..87dcdf3fc4 --- /dev/null +++ b/sim/testsuite/sim/h8300/movb.s @@ -0,0 +1,2221 @@ +# Hitachi H8 testcase 'mov.w' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +byte_src: + .byte 0x77 +byte_dst: + .byte 0 + + .text + + ;; + ;; Move byte from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_b_imm8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, rd + mov.b #0x77:8, r0l ; Immediate 3-bit operand +;;; .word 0xf877 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +mov_b_imm4_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:4, @aa:16 + mov.b #0xf:4, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x6adf +;;; .word @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xf, @byte_dst + beq .Lnext21 + fail +.Lnext21: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm4_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:4, @aa:32 + mov.b #0xf:4, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x6aff +;;; .long @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xf, @byte_dst + beq .Lnext22 + fail +.Lnext22: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x017d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext1 + fail +.Lnext1: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd+ + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x017d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst+1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext2 + fail +.Lnext2: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @erd- + mov.l #byte_dst, er1 + mov.b #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x017d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext3 + fail +.Lnext3: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @+erd + mov.l #byte_dst-1, er1 + mov.b #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x017d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext4 + fail +.Lnext4: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @-erd + mov.l #byte_dst+1, er1 + mov.b #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x017d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext5 + fail +.Lnext5: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:2, erd) + mov.l #byte_dst-3, er1 + mov.b #0xa5:8, @(3:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x017d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-3, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext6 + fail +.Lnext6: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:16, erd) + mov.l #byte_dst-4, er1 + mov.b #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x017d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext7 + fail +.Lnext7: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @(dd:32, erd) + mov.l #byte_dst-8, er1 + mov.b #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x017d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext8 + fail +.Lnext8: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, rd.b) + mov.b #0xa5:8, @(byte_dst-1:16, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffffff01, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, rd.w) + mov.b #0xa5:8, @(byte_dst-2:16, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffff0002, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:16, erd.l) + mov.b #0xa5:8, @(byte_dst-3:16, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0x00000003, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, rd.b) + mov.b #0xa5:8, @(byte_dst-4:32, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffffff04 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, rd.w) + mov.b #0xa5:8, @(byte_dst-5:32, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0xffff0005 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006, er1 + set_ccr_zero + ;; mov.b #xx:8, @(dd:32, erd.l) + mov.b #0xa5:8, @(byte_dst-6:32, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 0x00000006 er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @aa:16 + mov.b #0xa5:8, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x017d +;;; .word 0x40a5 +;;; .word @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext9 + fail +.Lnext9: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b #xx:8, @aa:32 + mov.b #0xa5:8, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x017d +;;; .word 0x48a5 +;;; .long @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b #0xa5, @byte_dst + beq .Lnext10 + fail +.Lnext10: + mov.b #0, @byte_dst ; zero it again for the next use. + +.endif + + ;; + ;; Move byte from register source + ;; + +mov_b_reg8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, erd + mov.b #0x12, r1l + mov.b r1l, r0l ; Register 8-bit operand +;;; .word 0x0c98 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr16 0xa512 r0 + test_h_gr16 0xa512 r1 ; mov src unchanged +.if (sim_cpu) + test_h_gr32 0xa5a5a512 er0 + test_h_gr32 0xa5a5a512 er1 ; mov src unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_b_reg8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd + mov.l #byte_dst, er1 + mov.b r0l, @er1 ; Register indirect operand +;;; .word 0x6898 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext44 + fail +.Lnext44: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd+ + mov.l #byte_dst, er1 + mov.b r0l, @er1+ ; Register post-incr operand +;;; .word 0x0173 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst+1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext49 + fail +.Lnext49: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @erd- + mov.l #byte_dst, er1 + mov.b r0l, @er1- ; Register post-decr operand +;;; .word 0x0171 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-1, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext50 + fail +.Lnext50: + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @+erd + mov.l #byte_dst-1, er1 + mov.b r0l, @+er1 ; Register pre-incr operand +;;; .word 0x0172 +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext51 + fail +.Lnext51: + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @-erd + mov.l #byte_dst+1, er1 + mov.b r0l, @-er1 ; Register pre-decr operand +;;; .word 0x6c98 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext48 + fail +.Lnext48: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:2, erd) + mov.l #byte_dst-3, er1 + mov.b r0l, @(3:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0173 +;;; .word 0x6898 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 byte_dst-3, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b r2l, @byte_dst + beq .Lnext52 + fail +.Lnext52: + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:16, erd) + mov.l #byte_dst-4, er1 + mov.b r0l, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x6e98 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext45 + fail +.Lnext45: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @(dd:32, erd) + mov.l #byte_dst-8, er1 + mov.b r0l, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6aa8 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r2l, r0l + beq .Lnext46 + fail +.Lnext46: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_b_reg8_to_indexb16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, rd.b) + mov.b r0l, @(byte_dst-1:16, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexw16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, rd.w) + mov.b r0l, @(byte_dst-2:16, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffff0002 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexl16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b ers, @(dd:16, erd.l) + mov.b r0l, @(byte_dst-3:16, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x00000003 er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexb32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, rd.b) + mov.b r0l, @(byte_dst-4:32, r1.b) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffffff04, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexw32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, rd.w) + mov.b r0l, @(byte_dst-5:32, r1.w) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xffff0005, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_indexl32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006 er1 + set_ccr_zero + ;; mov.b ers, @(dd:32, erd.l) + mov.b r0l, @(byte_dst-6:32, er1.l) ; byte indexed operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x00000006, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r0l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +.if (sim_cpu == h8sx) +mov_b_reg8_to_abs8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + + mov.l #byte_dst-20, er0 + ldc er0, sbr + set_ccr_zero + ;; mov.b ers, @aa:8 + mov.b r1l, @20:8 ; 8-bit address-direct (sbr-relative) operand + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 byte_dst-20, er0 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_dst, r1l + bne fail1 + mov.b #0, @byte_dst ; zero it again for the next use. +.endif + +mov_b_reg8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @aa:16 + mov.b r0l, @byte_dst:16 ; 16-bit address-direct operand +;;; .word 0x6a88 +;;; .word @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r0l, r1l + beq .Lnext41 + fail +.Lnext41: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + +mov_b_reg8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b ers, @aa:32 + mov.b r0l, @byte_dst:32 ; 32-bit address-direct operand +;;; .word 0x6aa8 +;;; .long @byte_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.b @byte_dst, r0l + cmp.b r0l, r1l + beq .Lnext42 + fail +.Lnext42: + mov.b #0, r0l + mov.b r0l, @byte_dst ; zero it again for the next use. + + ;; + ;; Move byte to register destination. + ;; + +mov_b_indirect_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers, rd + mov.l #byte_src, er1 + mov.b @er1, r0l ; Register indirect operand +;;; .word 0x6818 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_postinc_to_reg8: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers+, rd + + mov.l #byte_src, er1 + mov.b @er1+, r0l ; Register post-incr operand +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src+1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_b_postdec_to_reg8: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers-, rd + + mov.l #byte_src, er1 + mov.b @er1-, r0l ; Register post-decr operand +;;; .word 0x0172 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src-1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_preinc_to_reg8: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @+ers, rd + + mov.l #byte_src-1, er1 + mov.b @+er1, r0l ; Register pre-incr operand +;;; .word 0x0171 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_predec_to_reg8: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @-ers, rd + + mov.l #byte_src+1, er1 + mov.b @-er1, r0l ; Register pre-decr operand +;;; .word 0x0173 +;;; .word 0x6c18 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_b_disp2_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:2, ers), rd + mov.l #byte_src-1, er1 + mov.b @(1:2, er1), r0l ; Register plus 2-bit disp. operand +;;; .word 0x0171 +;;; .word 0x6818 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src-1, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_b_disp16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:16, ers), rd + mov.l #byte_src+0x1234, er1 + mov.b @(-0x1234:16, er1), r0l ; Register plus 16-bit disp. operand +;;; .word 0x6e18 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_disp32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:32, ers), rd + mov.l #byte_src+65536, er1 + mov.b @(-65536:32, er1), r0l ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6a28 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 byte_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_b_indexb16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + set_ccr_zero + ;; mov.b @(dd:16, rs.b), rd + mov.b @(byte_src-1:16, r1.b), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0xffffff01, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexw16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0002, er1 + set_ccr_zero + ;; mov.b @(dd:16, rs.w), rd + mov.b @(byte_src-2:16, r1.w), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0xffff0002, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexl16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000003, er1 + set_ccr_zero + ;; mov.b @(dd:16, ers.l), rd + mov.b @(byte_src-3:16, er1.l), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5a5 | 77 + + test_h_gr32 0x00000003, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexb32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff04, er1 + set_ccr_zero + ;; mov.b @(dd:32, rs.b), rd + mov.b @(byte_src-4:32, r1.b), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0xffffff04 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexw32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0005, er1 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), rd + mov.b @(byte_src-5:32, r1.w), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0xffff0005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_indexl32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000006, er1 + set_ccr_zero + ;; mov.b @(dd:32, ers.l), rd + mov.b @(byte_src-6:32, er1.l), r0l ; indexed byte operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 0x00000006 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +.if (sim_cpu == h8sx) +mov_b_abs8_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #byte_src-255, er1 + ldc er1, sbr + set_ccr_zero + ;; mov.b @aa:8, rd + mov.b @0xff:8, r0l ; 8-bit (sbr relative) address-direct operand + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_h_gr32 byte_src-255, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_b_abs16_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:16, rd + mov.b @byte_src:16, r0l ; 16-bit address-direct operand +;;; .word 0x6a08 +;;; .word @byte_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_b_abs32_to_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:32, rd + mov.b @byte_src:32, r0l ; 32-bit address-direct operand +;;; .word 0x6a28 +;;; .long @byte_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a5a577 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + + ;; + ;; Move byte from memory to memory + ;; + +mov_b_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers, @erd + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1, @er0 +;;; .word 0x0178 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_b_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers+, @erd+ + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1+, @er0+ +;;; .word 0x0178 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst+1 er0 + test_h_gr32 byte_src+1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_b_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @ers-, @erd- + + mov.l #byte_src, er1 + mov.l #byte_dst, er0 + mov.b @er1-, @er0- +;;; .word 0x0178 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-1 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_b_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @+ers, @+erd + + mov.l #byte_src-1, er1 + mov.l #byte_dst-1, er0 + mov.b @+er1, @+er0 +;;; .word 0x0178 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_b_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @-ers, @-erd + + mov.l #byte_src+1, er1 + mov.l #byte_dst+1, er0 + mov.b @-er1, @-er0 +;;; .word 0x0178 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst er0 + test_h_gr32 byte_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_b_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:2, ers), @(dd:2, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:2, er1), @(2:2, er0) +;;; .word 0x0178 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_b_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:16, ers), @(dd:16, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:16, er1), @(2:16, er0) +;;; .word 0x0178 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_b_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @(dd:32, ers), @(dd:32, erd) + + mov.l #byte_src-1, er1 + mov.l #byte_dst-2, er0 + mov.b @(1:32, er1), @(2:32, er0) +;;; .word 0x0178 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 byte_dst-2 er0 + test_h_gr32 byte_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_b_indexb16_to_indexb16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + mov.l #0xffffff02, er0 + ;; mov.b @(dd:16, rs.b), @(dd:16, rd.b) + set_ccr_zero + mov.b @(byte_src-1:16, r1.b), @(byte_dst-2:16, r0.b) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffffff02 er0 + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexw16_to_indewb16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0003, er1 + mov.l #0xffff0004, er0 + ;; mov.b @(dd:16, rs.w), @(dd:16, rd.w) + set_ccr_zero + mov.b @(byte_src-3:16, r1.w), @(byte_dst-4:16, r0.w) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffff0004 er0 + test_h_gr32 0xffff0003 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexl16_to_indexl16: ; reg 16-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000005, er1 + mov.l #0x00000006, er0 + ;; mov.b @(dd:16, ers.l), @(dd:16, erd.l) + set_ccr_zero + mov.b @(byte_src-5:16, er1.l), @(byte_dst-6:16, er0.l) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0x00000006 er0 + test_h_gr32 0x00000005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexb32_to_indexb32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffffff01, er1 + mov.l #0xffffff02, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.b), @(dd:32, rd.b) + mov.b @(byte_src-1:32, r1.b), @(byte_dst-2:32, r0.b) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffffff02 er0 + test_h_gr32 0xffffff01 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexw32_to_indexw32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0xffff0003, er1 + mov.l #0xffff0004, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) + mov.b @(byte_src-3:32, r1.w), @(byte_dst-4:32, r0.w) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0xffff0004 er0 + test_h_gr32 0xffff0003 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_indexl32_to_indexl32: ; reg 32-bit indexed, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + mov.l #0x00000005, er1 + mov.l #0x00000006, er0 + set_ccr_zero + ;; mov.b @(dd:32, rs.w), @(dd:32, rd.w) + mov.b @(byte_src-5:32, er1.l), @(byte_dst-6:32, er0.l) + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 0x00000006 er0 + test_h_gr32 0x00000005 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + bne fail1 + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + beq fail1 + +mov_b_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:16, @aa:16 + + mov.b @byte_src:16, @byte_dst:16 +;;; .word 0x0178 +;;; .word 0x4040 +;;; .word @byte_src +;;; .word @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.b @aa:32, @aa:32 + + mov.b @byte_src:32, @byte_dst:32 +;;; .word 0x0178 +;;; .word 0x4848 +;;; .long @byte_src +;;; .long @byte_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.b @byte_src, @byte_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.b #0, @byte_dst + cmp.b @byte_src, @byte_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 + +fail1: + fail +
\ No newline at end of file diff --git a/sim/testsuite/sim/h8300/movl.s b/sim/testsuite/sim/h8300/movl.s new file mode 100644 index 0000000000..dcc392227e --- /dev/null +++ b/sim/testsuite/sim/h8300/movl.s @@ -0,0 +1,2160 @@ +# Hitachi H8 testcase 'mov.l' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 4 +long_src: + .long 0x77777777 +long_dst: + .long 0 + + .text + + ;; + ;; Move long from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_l_imm3_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:3, erd + mov.l #0x3:3, er0 ; Immediate 3-bit operand +;;; .word 0x0fb8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x3 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_imm16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, erd + mov.l #0x1234, er0 ; Immediate 16-bit operand +;;; .word 0x7a08 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x1234 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_l_imm32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, erd + mov.l #0x12345678, er0 ; Immediate 32-bit operand +;;; .word 0x7a00 +;;; .long 0x12345678 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x12345678 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_l_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x010d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext1 + fail +.Lnext1: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd+ + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x010d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext2 + fail +.Lnext2: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @erd- + mov.l #long_dst, er1 + mov.l #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x010d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext3 + fail +.Lnext3: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @+erd + mov.l #long_dst-4, er1 + mov.l #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x010d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext4 + fail +.Lnext4: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @-erd + mov.l #long_dst+4, er1 + mov.l #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x010d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext5 + fail +.Lnext5: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xa5:8, @(12:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x010d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext6 + fail +.Lnext6: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x010d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext7 + fail +.Lnext7: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x010d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext8 + fail +.Lnext8: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @aa:16 + mov.l #0xa5:8, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x010d +;;; .word 0x40a5 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext9 + fail +.Lnext9: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:8, @aa:32 + mov.l #0xa5:8, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x010d +;;; .word 0x48a5 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xa5, @long_dst + beq .Lnext10 + fail +.Lnext10: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext11 + fail +.Lnext11: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd+ + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext12 + fail +.Lnext12: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @erd- + mov.l #long_dst, er1 + mov.l #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext13 + fail +.Lnext13: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @+erd + mov.l #long_dst-4, er1 + mov.l #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext14 + fail +.Lnext14: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @-erd + mov.l #long_dst+4, er1 + mov.l #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext15 + fail +.Lnext15: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xdead:16, @(12:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext16 + fail +.Lnext16: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext17 + fail +.Lnext17: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext18 + fail +.Lnext18: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @aa:16 + mov.l #0xdead:16, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x4000 +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext19 + fail +.Lnext19: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:16, @aa:32 + mov.l #0xdead:16, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x7a7c +;;; .word 0xdead +;;; .word 0x4800 +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xdead, @long_dst + beq .Lnext20 + fail +.Lnext20: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1 ; Register indirect operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext21 + fail +.Lnext21: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_postinc: ; post-increment from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd+ + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1+ ; Imm32, register post-incr operands. +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext22 + fail +.Lnext22: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_postdec: ; post-decrement from imm32 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @erd- + mov.l #long_dst, er1 + mov.l #0xcafedead:32, @er1- ; Imm32, register post-decr operands. +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext23 + fail +.Lnext23: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @+erd + mov.l #long_dst-4, er1 + mov.l #0xcafedead:32, @+er1 ; Imm32, register pre-incr operands +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext24 + fail +.Lnext24: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @-erd + mov.l #long_dst+4, er1 + mov.l #0xcafedead:32, @-er1 ; Imm32, register pre-decr operands +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext25 + fail +.Lnext25: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l #0xcafedead:32, @(12:2, er1) ; Imm32, reg plus 2-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext26 + fail +.Lnext26: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l #0xcafedead:32, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext27 + fail +.Lnext27: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l #0xcafedead:32, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext28 + fail +.Lnext28: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @aa:16 + mov.l #0xcafedead:32, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x4000 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext29 + fail +.Lnext29: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_imm32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l #xx:32, @aa:32 + mov.l #0xcafedead:32, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x7a74 +;;; .long 0xcafedead +;;; .word 0x4800 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l #0xcafedead, @long_dst + beq .Lnext30 + fail +.Lnext30: + mov.l #0, @long_dst ; zero it again for the next use. + +.endif + + ;; + ;; Move long from register source + ;; + +mov_l_reg32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, erd + mov.l #0x12345678, er1 + mov.l er1, er0 ; Register 32-bit operand +;;; .word 0x0f90 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr32 0x12345678 er0 + test_h_gr32 0x12345678 er1 ; mov src unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_reg32_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd + mov.l #long_dst, er1 + mov.l er0, @er1 ; Register indirect operand +;;; .word 0x0100 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext44 + fail +.Lnext44: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_l_reg32_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd+ + mov.l #long_dst, er1 + mov.l er0, @er1+ ; Register post-incr operand +;;; .word 0x0103 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst+4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext49 + fail +.Lnext49: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @erd- + mov.l #long_dst, er1 + mov.l er0, @er1- ; Register post-decr operand +;;; .word 0x0101 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext50 + fail +.Lnext50: + mov.l #0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @+erd + mov.l #long_dst-4, er1 + mov.l er0, @+er1 ; Register pre-incr operand +;;; .word 0x0102 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext51 + fail +.Lnext51: + mov.l #0, @long_dst ; zero it again for the next use. +.endif ; h8sx + +mov_l_reg32_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @-erd + mov.l #long_dst+4, er1 + mov.l er0, @-er1 ; Register pre-decr operand +;;; .word 0x0100 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext48 + fail +.Lnext48: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_l_reg32_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:2, erd) + mov.l #long_dst-12, er1 + mov.l er0, @(12:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0103 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 long_dst-12, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l er2, @long_dst + beq .Lnext52 + fail +.Lnext52: + mov.l #0, @long_dst ; zero it again for the next use. +.endif ; h8sx + +mov_l_reg32_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:16, erd) + mov.l #long_dst-4, er1 + mov.l er0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x0100 +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 long_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext45 + fail +.Lnext45: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @(dd:32, erd) + mov.l #long_dst-8, er1 + mov.l er0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7890 +;;; .word 0x6ba0 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 long_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er2, er0 + beq .Lnext46 + fail +.Lnext46: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @aa:16 + mov.l er0, @long_dst:16 ; 16-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b80 +;;; .word @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er0, er1 + beq .Lnext41 + fail +.Lnext41: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + +mov_l_reg32_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l ers, @aa:32 + mov.l er0, @long_dst:32 ; 32-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6ba0 +;;; .long @long_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.l #0, er0 + mov.l @long_dst, er0 + cmp.l er0, er1 + beq .Lnext42 + fail +.Lnext42: + mov.l #0, er0 + mov.l er0, @long_dst ; zero it again for the next use. + + ;; + ;; Move long to register destination. + ;; + +mov_l_indirect_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers, erd + mov.l #long_src, er1 + mov.l @er1, er0 ; Register indirect operand +;;; .word 0x0100 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_postinc_to_reg32: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers+, erd + + mov.l #long_src, er1 + mov.l @er1+, er0 ; Register post-incr operand +;;; .word 0x0100 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src+4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_l_postdec_to_reg32: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers-, erd + + mov.l #long_src, er1 + mov.l @er1-, er0 ; Register post-decr operand +;;; .word 0x0102 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_preinc_to_reg32: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @+ers, erd + + mov.l #long_src-4, er1 + mov.l @+er1, er0 ; Register pre-incr operand +;;; .word 0x0101 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_predec_to_reg32: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @-ers, erd + + mov.l #long_src+4, er1 + mov.l @-er1, er0 ; Register pre-decr operand +;;; .word 0x0103 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_h_gr32 long_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_l_disp2_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:2, ers), erd + mov.l #long_src-4, er1 + mov.l @(4:2, er1), er0 ; Register plus 2-bit disp. operand +;;; .word 0x0101 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src-4, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif ; h8sx + +mov_l_disp16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:16, ers), erd + mov.l #long_src+0x1234, er1 + mov.l @(-0x1234:16, er1), er0 ; Register plus 16-bit disp. operand +;;; .word 0x0100 +;;; .word 0x6f10 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_disp32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:32, ers), erd + mov.l #long_src+65536, er1 + mov.l @(-65536:32, er1), er0 ; Register plus 32-bit disp. operand +;;; .word 0x7890 +;;; .word 0x6b20 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 long_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_abs16_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:16, erd + mov.l @long_src:16, er0 ; 16-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b00 +;;; .word @long_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_l_abs32_to_reg32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:32, erd + mov.l @long_src:32, er0 ; 32-bit address-direct operand +;;; .word 0x0100 +;;; .word 0x6b20 +;;; .long @long_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0x77777777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +.if (sim_cpu == h8sx) + + ;; + ;; Move long from memory to memory + ;; + +mov_l_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers, @erd + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1, @er0 +;;; .word 0x0108 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_l_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers+, @erd+ + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1+, @er0+ +;;; .word 0x0108 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst+4 er0 + test_h_gr32 long_src+4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_l_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @ers-, @erd- + + mov.l #long_src, er1 + mov.l #long_dst, er0 + mov.l @er1-, @er0- +;;; .word 0x0108 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-4 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_l_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @+ers, @+erd + + mov.l #long_src-4, er1 + mov.l #long_dst-4, er0 + mov.l @+er1, @+er0 +;;; .word 0x0108 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_l_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @-ers, @-erd + + mov.l #long_src+4, er1 + mov.l #long_dst+4, er0 + mov.l @-er1, @-er0 +;;; .word 0x0108 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst er0 + test_h_gr32 long_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_l_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:2, ers), @(dd:2, erd) + + mov.l #long_src-4, er1 + mov.l #long_dst-8, er0 + mov.l @(4:2, er1), @(8:2, er0) +;;; .word 0x0108 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-8 er0 + test_h_gr32 long_src-4 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_l_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:16, ers), @(dd:16, erd) + + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + mov.l @(1:16, er1), @(2:16, er0) +;;; .word 0x0108 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_l_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @(dd:32, ers), @(dd:32, erd) + + mov.l #long_src-1, er1 + mov.l #long_dst-2, er0 + mov.l @(1:32, er1), @(2:32, er0) +;;; .word 0x0108 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 long_dst-2 er0 + test_h_gr32 long_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_l_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:16, @aa:16 + + mov.l @long_src:16, @long_dst:16 +;;; .word 0x0108 +;;; .word 0x4040 +;;; .word @long_src +;;; .word @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_l_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.l @aa:32, @aa:32 + + mov.l @long_src:32, @long_dst:32 +;;; .word 0x0108 +;;; .word 0x4848 +;;; .long @long_src +;;; .long @long_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.l @long_src, @long_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.l #0, @long_dst + cmp.l @long_src, @long_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/movw.s b/sim/testsuite/sim/h8300/movw.s new file mode 100644 index 0000000000..b8b09ea8ba --- /dev/null +++ b/sim/testsuite/sim/h8300/movw.s @@ -0,0 +1,1857 @@ +# Hitachi H8 testcase 'mov.w' +# mach(): h8300h h8300s h8sx +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + + .data + .align 2 +word_src: + .word 0x7777 +word_dst: + .word 0 + + .text + + ;; + ;; Move word from immediate source + ;; + +.if (sim_cpu == h8sx) +mov_w_imm3_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:3, rd + mov.w #0x3:3, r0 ; Immediate 3-bit operand +;;; .word 0x0f30 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a50003 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_w_imm16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, rd + mov.w #0x1234, r0 ; Immediate 16-bit operand +;;; .word 0x7900 +;;; .word 0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a51234 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_w_imm4_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:4, @aa:16 + mov.w #0xf:4, @word_dst:16 ; 4-bit imm to 16-bit address-direct +;;; .word 0x6bdf +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xf, @word_dst + beq .Lnext21 + fail +.Lnext21: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm4_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:4, @aa:32 + mov.w #0xf:4, @word_dst:32 ; 4-bit imm to 32-bit address-direct +;;; .word 0x6bff +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xf, @word_dst + beq .Lnext22 + fail +.Lnext22: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1 ; Register indirect operand +;;; .word 0x015d +;;; .word 0x01a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext1 + fail +.Lnext1: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_postinc: ; post-increment from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd+ + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1+ ; Imm8, register post-incr operands. +;;; .word 0x015d +;;; .word 0x81a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext2 + fail +.Lnext2: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_postdec: ; post-decrement from imm8 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @erd- + mov.l #word_dst, er1 + mov.w #0xa5:8, @er1- ; Imm8, register post-decr operands. +;;; .word 0x015d +;;; .word 0xa1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext3 + fail +.Lnext3: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @+erd + mov.l #word_dst-2, er1 + mov.w #0xa5:8, @+er1 ; Imm8, register pre-incr operands +;;; .word 0x015d +;;; .word 0x91a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext4 + fail +.Lnext4: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @-erd + mov.l #word_dst+2, er1 + mov.w #0xa5:8, @-er1 ; Imm8, register pre-decr operands +;;; .word 0x015d +;;; .word 0xb1a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext5 + fail +.Lnext5: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w #0xa5:8, @(6:2, er1) ; Imm8, reg plus 2-bit disp. operand +;;; .word 0x015d +;;; .word 0x31a5 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext6 + fail +.Lnext6: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w #0xa5:8, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x015d +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext7 + fail +.Lnext7: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w #0xa5:8, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x015d +;;; .word 0xc9a5 +;;; .long 8 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext8 + fail +.Lnext8: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @aa:16 + mov.w #0xa5:8, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x015d +;;; .word 0x40a5 +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext9 + fail +.Lnext9: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm8_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:8, @aa:32 + mov.w #0xa5:8, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x015d +;;; .word 0x48a5 +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xa5, @word_dst + beq .Lnext10 + fail +.Lnext10: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1 ; Register indirect operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x0100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext11 + fail +.Lnext11: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_postinc: ; post-increment from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd+ + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1+ ; Imm16, register post-incr operands. +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x8100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext12 + fail +.Lnext12: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_postdec: ; post-decrement from imm16 to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @erd- + mov.l #word_dst, er1 + mov.w #0xdead:16, @er1- ; Imm16, register post-decr operands. +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xa100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext13 + fail +.Lnext13: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @+erd + mov.l #word_dst-2, er1 + mov.w #0xdead:16, @+er1 ; Imm16, register pre-incr operands +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x9100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext14 + fail +.Lnext14: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @-erd + mov.l #word_dst+2, er1 + mov.w #0xdead:16, @-er1 ; Imm16, register pre-decr operands +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xb100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext15 + fail +.Lnext15: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w #0xdead:16, @(6:2, er1) ; Imm16, reg plus 2-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x3100 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext16 + fail +.Lnext16: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w #0xdead:16, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xc100 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext17 + fail +.Lnext17: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w #0xdead:16, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0xc900 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext18 + fail +.Lnext18: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @aa:16 + mov.w #0xdead:16, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x4000 +;;; .word @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext19 + fail +.Lnext19: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_imm16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w #xx:16, @aa:32 + mov.w #0xdead:16, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x7974 +;;; .word 0xdead +;;; .word 0x4800 +;;; .long @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w #0xdead, @word_dst + beq .Lnext20 + fail +.Lnext20: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + + ;; + ;; Move word from register source + ;; + +mov_w_reg16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, erd + mov.w #0x1234, r1 + mov.w r1, r0 ; Register 16-bit operand +;;; .word 0x0d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + test_h_gr16 0x1234 r0 + test_h_gr16 0x1234 r1 ; mov src unchanged +.if (sim_cpu) + test_h_gr32 0xa5a51234 er0 + test_h_gr32 0xa5a51234 er1 ; mov src unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_w_reg16_to_indirect: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd + mov.l #word_dst, er1 + mov.w r0, @er1 ; Register indirect operand +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext44 + fail +.Lnext44: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_w_reg16_to_postinc: ; post-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd+ + mov.l #word_dst, er1 + mov.w r0, @er1+ ; Register post-incr operand +;;; .word 0x0153 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst+2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext49 + fail +.Lnext49: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_postdec: ; post-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @erd- + mov.l #word_dst, er1 + mov.w r0, @er1- ; Register post-decr operand +;;; .word 0x0151 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-2, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext50 + fail +.Lnext50: + mov.w #0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_preinc: ; pre-increment from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @+erd + mov.l #word_dst-2, er1 + mov.w r0, @+er1 ; Register pre-incr operand +;;; .word 0x0152 +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext51 + fail +.Lnext51: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + +mov_w_reg16_to_predec: ; pre-decrement from register to mem + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @-erd + mov.l #word_dst+2, er1 + mov.w r0, @-er1 ; Register pre-decr operand +;;; .word 0x6d90 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext48 + fail +.Lnext48: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +.if (sim_cpu == h8sx) +mov_w_reg16_to_disp2: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:2, erd) + mov.l #word_dst-6, er1 + mov.w r0, @(6:2, er1) ; Register plus 2-bit disp. operand +;;; .word 0x0153 +;;; .word 0x6990 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_h_gr32 word_dst-6, er1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w r2, @word_dst + beq .Lnext52 + fail +.Lnext52: + mov.w #0, @word_dst ; zero it again for the next use. +.endif + +mov_w_reg16_to_disp16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:16, erd) + mov.l #word_dst-4, er1 + mov.w r0, @(4:16, er1) ; Register plus 16-bit disp. operand +;;; .word 0x6f90 +;;; .word 0x0004 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 word_dst-4, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext45 + fail +.Lnext45: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_disp32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @(dd:32, erd) + mov.l #word_dst-8, er1 + mov.w r0, @(8:32, er1) ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6ba0 +;;; .long 8 + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 word_dst-8, er1 + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r2, r0 + beq .Lnext46 + fail +.Lnext46: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_abs16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @aa:16 + mov.w r0, @word_dst:16 ; 16-bit address-direct operand +;;; .word 0x6b80 +;;; .word @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r0, r1 + beq .Lnext41 + fail +.Lnext41: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + +mov_w_reg16_to_abs32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w ers, @aa:32 + mov.w r0, @word_dst:32 ; 32-bit address-direct operand +;;; .word 0x6ba0 +;;; .long @word_dst + + ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_neg_set + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure _ALL_ general regs not disturbed + test_gr_a5a5 1 ; (first, because on h8/300 we must use one + test_gr_a5a5 2 ; to examine the destination memory). + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + mov.w #0, r0 + mov.w @word_dst, r0 + cmp.w r0, r1 + beq .Lnext42 + fail +.Lnext42: + mov.w #0, r0 + mov.w r0, @word_dst ; zero it again for the next use. + + ;; + ;; Move word to register destination. + ;; + +mov_w_indirect_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers, rd + mov.l #word_src, er1 + mov.w @er1, r0 ; Register indirect operand +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_postinc_to_reg16: ; post-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers+, rd + + mov.l #word_src, er1 + mov.w @er1+, r0 ; Register post-incr operand +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src+2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +mov_w_postdec_to_reg16: ; post-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers-, rd + + mov.l #word_src, er1 + mov.w @er1-, r0 ; Register post-decr operand +;;; .word 0x0152 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src-2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_preinc_to_reg16: ; pre-increment from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @+ers, rd + + mov.l #word_src-2, er1 + mov.w @+er1, r0 ; Register pre-incr operand +;;; .word 0x0151 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_predec_to_reg16: ; pre-decrement from mem to register + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @-ers, rd + + mov.l #word_src+2, er1 + mov.w @-er1, r0 ; Register pre-decr operand +;;; .word 0x0153 +;;; .word 0x6d10 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_h_gr32 word_src, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + +mov_w_disp2_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:2, ers), rd + mov.l #word_src-2, er1 + mov.w @(2:2, er1), r0 ; Register plus 2-bit disp. operand +;;; .word 0x0151 +;;; .word 0x6910 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src-2, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +mov_w_disp16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:16, ers), rd + mov.l #word_src+0x1234, er1 + mov.w @(-0x1234:16, er1), r0 ; Register plus 16-bit disp. operand +;;; .word 0x6f10 +;;; .word -0x1234 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src+0x1234, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_disp32_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:32, ers), rd + mov.l #word_src+65536, er1 + mov.w @(-65536:32, er1), r0 ; Register plus 32-bit disp. operand +;;; .word 0x7810 +;;; .word 0x6b20 +;;; .long -65536 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 ; mov result: a5a5 | 7777 + + test_h_gr32 word_src+65536, er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_abs16_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:16, rd + mov.w @word_src:16, r0 ; 16-bit address-direct operand +;;; .word 0x6b00 +;;; .word @word_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +mov_w_abs32_to_reg16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:32, rd + mov.w @word_src:32, r0 ; 32-bit address-direct operand +;;; .word 0x6b20 +;;; .long @word_src + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_h_gr32 0xa5a57777 er0 + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) + + ;; + ;; Move word from memory to memory + ;; + +mov_w_indirect_to_indirect: ; reg indirect, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers, @erd + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1, @er0 +;;; .word 0x0158 +;;; .word 0x0100 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext55 + fail +.Lnext55: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext56 + fail +.Lnext56: ; OK, pass on. + +mov_w_postinc_to_postinc: ; reg post-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers+, @erd+ + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1+, @er0+ +;;; .word 0x0158 +;;; .word 0x8180 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst+2 er0 + test_h_gr32 word_src+2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext65 + fail +.Lnext65: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext66 + fail +.Lnext66: ; OK, pass on. + +mov_w_postdec_to_postdec: ; reg post-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @ers-, @erd- + + mov.l #word_src, er1 + mov.l #word_dst, er0 + mov.w @er1-, @er0- +;;; .word 0x0158 +;;; .word 0xa1a0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext75 + fail +.Lnext75: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext76 + fail +.Lnext76: ; OK, pass on. + +mov_w_preinc_to_preinc: ; reg pre-increment, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @+ers, @+erd + + mov.l #word_src-2, er1 + mov.l #word_dst-2, er0 + mov.w @+er1, @+er0 +;;; .word 0x0158 +;;; .word 0x9190 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext85 + fail +.Lnext85: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext86 + fail +.Lnext86: ; OK, pass on. + +mov_w_predec_to_predec: ; reg pre-decrement, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @-ers, @-erd + + mov.l #word_src+2, er1 + mov.l #word_dst+2, er0 + mov.w @-er1, @-er0 +;;; .word 0x0158 +;;; .word 0xb1b0 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst er0 + test_h_gr32 word_src er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext95 + fail +.Lnext95: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext96 + fail +.Lnext96: ; OK, pass on. + +mov_w_disp2_to_disp2: ; reg 2-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:2, ers), @(dd:2, erd) + + mov.l #word_src-2, er1 + mov.l #word_dst-4, er0 + mov.w @(2:2, er1), @(4:2, er0) +;;; .word 0x0158 +;;; .word 0x1120 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-4 er0 + test_h_gr32 word_src-2 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext105 + fail +.Lnext105: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext106 + fail +.Lnext106: ; OK, pass on. + +mov_w_disp16_to_disp16: ; reg 16-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:16, ers), @(dd:16, erd) + + mov.l #word_src-1, er1 + mov.l #word_dst-2, er0 + mov.w @(1:16, er1), @(2:16, er0) +;;; .word 0x0158 +;;; .word 0xc1c0 +;;; .word 0x0001 +;;; .word 0x0002 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext115 + fail +.Lnext115: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext116 + fail +.Lnext116: ; OK, pass on. + +mov_w_disp32_to_disp32: ; reg 32-bit disp, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @(dd:32, ers), @(dd:32, erd) + + mov.l #word_src-1, er1 + mov.l #word_dst-2, er0 + mov.w @(1:32, er1), @(2:32, er0) +;;; .word 0x0158 +;;; .word 0xc9c8 +;;; .long 1 +;;; .long 2 + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + ;; Verify the affected registers. + + test_h_gr32 word_dst-2 er0 + test_h_gr32 word_src-1 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext125 + fail +.Lnext125: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext126 + fail +.Lnext126: ; OK, pass on. + +mov_w_abs16_to_abs16: ; 16-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:16, @aa:16 + + mov.w @word_src:16, @word_dst:16 +;;; .word 0x0158 +;;; .word 0x4040 +;;; .word @word_src +;;; .word @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext135 + fail +.Lnext135: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext136 + fail +.Lnext136: ; OK, pass on. + +mov_w_abs32_to_abs32: ; 32-bit absolute addr, memory to memory + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; mov.w @aa:32, @aa:32 + + mov.w @word_src:32, @word_dst:32 +;;; .word 0x0158 +;;; .word 0x4848 +;;; .long @word_src +;;; .long @word_dst + + ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 + test_neg_clear + test_zero_clear + test_ovf_clear + test_carry_clear + + test_gr_a5a5 0 ; Make sure *NO* general registers are changed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the move to memory. + cmp.w @word_src, @word_dst + beq .Lnext145 + fail +.Lnext145: + ;; Now clear the destination location, and verify that. + mov.w #0, @word_dst + cmp.w @word_src, @word_dst + bne .Lnext146 + fail +.Lnext146: ; OK, pass on. + + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/neg.s b/sim/testsuite/sim/h8300/neg.s index efb031384d..de82476068 100644 --- a/sim/testsuite/sim/h8300/neg.s +++ b/sim/testsuite/sim/h8300/neg.s @@ -547,8 +547,8 @@ neg_w_disp2dst: set_ccr_zero ;; neg.w @(dd:2, erd) - mov #word_dest-1, er1 - neg.w @(1:2, er1) ; reg plus 2-bit displacement + mov #word_dest-2, er1 + neg.w @(2:2, er1) ; reg plus 2-bit displacement ;;; .word 0x0155 ;;; .word 0x6918 ;;; .word 0x1790 @@ -562,7 +562,7 @@ neg_w_disp2dst: beq .Lwdisp2 fail .Lwdisp2: - test_h_gr32 word_dest-1 er1 ; er1 contains address minus one + test_h_gr32 word_dest-2 er1 ; er1 contains address minus one test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -872,8 +872,8 @@ neg_l_disp2dst: set_ccr_zero ;; neg.l @(dd:2, erd) - mov #long_dest-1, er1 - neg.l @(1:2, er1) ; reg plus 2-bit displacement + mov #long_dest-4, er1 + neg.l @(4:2, er1) ; reg plus 2-bit displacement ;;; .word 0x0105 ;;; .word 0x6918 ;;; .word 0x17b0 @@ -887,7 +887,7 @@ neg_l_disp2dst: beq .Lldisp2 fail .Lldisp2: - test_h_gr32 long_dest-1 er1 ; er1 contains address minus one + test_h_gr32 long_dest-4 er1 ; er1 contains address minus one test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 diff --git a/sim/testsuite/sim/h8300/not.s b/sim/testsuite/sim/h8300/not.s index d96f323277..862c2b22ef 100644 --- a/sim/testsuite/sim/h8300/not.s +++ b/sim/testsuite/sim/h8300/not.s @@ -538,8 +538,8 @@ not_w_disp2dst: set_ccr_zero ;; not.w @(dd:2, erd) - mov #word_dest-1, er1 - not.w @(1:2, er1) ; reg plus 2-bit displacement + mov #word_dest-2, er1 + not.w @(2:2, er1) ; reg plus 2-bit displacement ;;; .word 0x0155 ;;; .word 0x6918 ;;; .word 0x1710 @@ -553,7 +553,7 @@ not_w_disp2dst: beq .Lwdisp2 fail .Lwdisp2: - test_h_gr32 word_dest-1 er1 ; er1 contains address minus one + test_h_gr32 word_dest-2 er1 ; er1 contains address minus one test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -859,8 +859,8 @@ not_l_disp2dst: set_ccr_zero ;; not.l @(dd:2, erd) - mov #long_dest-1, er1 - not.l @(1:2, er1) ; reg plus 2-bit displacement + mov #long_dest-4, er1 + not.l @(4:2, er1) ; reg plus 2-bit displacement ;;; .word 0x0105 ;;; .word 0x6918 ;;; .word 0x1730 @@ -874,7 +874,7 @@ not_l_disp2dst: beq .Lldisp2 fail .Lldisp2: - test_h_gr32 long_dest-1 er1 ; er1 contains address minus one + test_h_gr32 long_dest-4 er1 ; er1 contains address minus one test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 diff --git a/sim/testsuite/sim/h8300/orb.s b/sim/testsuite/sim/h8300/orb.s new file mode 100644 index 0000000000..fd06f08fb9 --- /dev/null +++ b/sim/testsuite/sim/h8300/orb.s @@ -0,0 +1,493 @@ +# Hitachi H8 testcase 'or.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # or.b #xx:8, rd ; c rd xxxxxxxx + # or.b #xx:8, @erd ; 7 d rd ???? c ???? xxxxxxxx + # or.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx + # or.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx + # or.b rs, rd ; 1 4 rs rd + # or.b reg8, @erd ; 7 d rd ???? 1 4 rs ???? + # or.b reg8, @erd+ ; 0 1 7 9 8 rd 4 rs + # or.b reg8, @erd- ; 0 1 7 9 a rd 4 rs + # or.b reg8, @+erd ; 0 1 7 9 9 rd 4 rs + # or.b reg8, @-erd ; 0 1 7 9 b rd 4 rs + # + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +or_b_imm8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.b #xx:8,Rd + or.b #0xaa, r0l ; Immediate 8-bit src, reg8 dest + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5af r0 ; or result: a5 | aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5af er0 ; or result: a5 | aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +or_b_imm8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd + mov #byte_dest, er0 + or.b #0xaa:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L1 + fail +.L1: + +or_b_imm8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd+ + mov #byte_dest, er0 + or.b #0x55:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xc055 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L2 + fail +.L2: + +or_b_imm8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@eRd- + mov #byte_dest, er0 + or.b #0xaa:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L3 + fail +.L3: + +or_b_imm8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@+eRd + mov #pre_byte, er0 + or.b #0x55:8, @+er0 ; Immediate 8-bit src, reg pre-incr dest +;;; .word 0x0175 +;;; .word 0x6c08 +;;; .word 0xc055 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L4 + fail +.L4: + +or_b_imm8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b #xx:8,@-eRd + mov #post_byte, er0 + or.b #0xaa:8, @-er0 ; Immediate 8-bit src, reg pre-decr dest +;;; .word 0x0177 +;;; .word 0x6c08 +;;; .word 0xc0aa + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 contains destination address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L5 + fail +.L5: + + +.endif + +or_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.b Rs,Rd + mov.b #0xaa, r0h + or.b r0h, r0l ; Reg8 src, reg8 dest + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xaaaf r0 ; or result: a5 | aa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5aaaf er0 ; or result: a5 | aa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +or_b_reg8_rdind: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd ; or reg8 to register indirect + mov #byte_dest, er0 + mov #0xaa, r1l + or.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1490 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L6 + fail +.L6: + +or_b_reg8_rdpostinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd+ ; or reg8 to register indirect post-increment + mov #byte_dest, er0 + mov #0x55, r1l + or.b r1l, @er0+ ; reg8 src, reg post-incr dest +;;; .word 0x0179 +;;; .word 0x8049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L7 + fail +.L7: + +or_b_reg8_rdpostdec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@eRd- ; or reg8 to register indirect post-decrement + mov #byte_dest, er0 + mov #0xaa, r1l + or.b r1l, @er0- ; reg8 src, reg post-decr dest +;;; .word 0x0179 +;;; .word 0xa049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L8 + fail +.L8: + +or_b_reg8_rdpreinc: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@+eRd ; or reg8 to register indirect pre-increment + mov #pre_byte, er0 + mov #0x55, r1l + or.b r1l, @+er0 ; reg8 src, reg pre-incr dest +;;; .word 0x0179 +;;; .word 0x9049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a555 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xf5, r0l + beq .L9 + fail +.L9: + +or_b_reg8_rdpredec: + mov #byte_dest, er0 + mov.b #0xa5, r1l + mov.b r1l, @er0 + + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; or.b rs8,@-eRd ; or reg8 to register indirect pre-decrement + mov #post_byte, er0 + mov #0xaa, r1l + or.b r1l, @-er0 ; reg8 src, reg pre-decr dest +;;; .word 0x0179 +;;; .word 0xb049 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 contains destination address + test_h_gr32 0xa5a5a5aa er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xaf, r0l + beq .L10 + fail +.L10: + +orc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; orc #xx:8,ccr + + test_neg_clear + orc #0x8, ccr ; Immediate 8-bit operand (neg flag) + test_neg_set + + test_zero_clear + orc #0x4, ccr ; Immediate 8-bit operand (zero flag) + test_zero_set + + test_ovf_clear + orc #0x2, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_set + + test_carry_clear + orc #0x1, ccr ; Immediate 8-bit operand (carry flag) + test_carry_set + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/orl.s b/sim/testsuite/sim/h8300/orl.s new file mode 100644 index 0000000000..03c3f2228b --- /dev/null +++ b/sim/testsuite/sim/h8300/orl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'or.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +or_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l #xx:16,Rd + or.l #0xaaaa, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +or_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l #xx:32,Rd + or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +or_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.l Rs,Rd + mov.l #0xaaaaaaaa, er1 + or.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa + test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/orw.s b/sim/testsuite/sim/h8300/orw.s new file mode 100644 index 0000000000..32eef4559e --- /dev/null +++ b/sim/testsuite/sim/h8300/orw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'or.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +or_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.w #xx:16,Rd + or.w #0xaaaa, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +or_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; or.w Rs,Rd + mov.w #0xaaaa, r1 + or.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xafaf r0 ; or result: a5a5 | aaaa + test_h_gr16 0xaaaa r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5afaf er0 ; or result: a5a5 | aaaa + test_h_gr32 0xa5a5aaaa er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s index af5cba0fb3..2a964c1c29 100644 --- a/sim/testsuite/sim/h8300/rotr.s +++ b/sim/testsuite/sim/h8300/rotr.s @@ -768,15 +768,15 @@ rotr_w_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - rotr.w @(2:2, er0) ; shift right arithmetic by one, disp2 + mov #word_dest-4, er0 + rotr.w @(4:2, er0) ; shift right arithmetic by one, disp2 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1059,15 +1059,15 @@ rotr_w_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - rotr.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2 + mov #word_dest-4, er0 + rotr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1357,15 +1357,15 @@ rotr_l_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - rotr.l @(2:2, er0) ; shift right arithmetic by one, disp2 + mov #long_dest-8, er0 + rotr.l @(8:2, er0) ; shift right arithmetic by one, disp2 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 test_zero_clear test_ovf_clear test_neg_set - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1660,15 +1660,15 @@ rotr_l_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - rotr.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2 + mov #long_dest-8, er0 + rotr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 test_zero_clear test_ovf_clear test_neg_clear - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s index 6fc5b2ce21..96ec8a12b6 100644 --- a/sim/testsuite/sim/h8300/rotxr.s +++ b/sim/testsuite/sim/h8300/rotxr.s @@ -849,8 +849,8 @@ rotxr_w_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - rotxr.w @(2:2, er0) ; shift right arithmetic by one, disp2 + mov #word_dest-4, er0 + rotxr.w @(4:2, er0) ; shift right arithmetic by one, disp2 ;;; .word 0x0156 ;;; .word 0xa908 ;;; .word 0x1310 @@ -860,7 +860,7 @@ rotxr_w_disp2_1: test_ovf_clear test_neg_clear - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1172,8 +1172,8 @@ rotxr_w_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - rotxr.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2 + mov #word_dest-4, er0 + rotxr.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 ;;; .word 0x0156 ;;; .word 0xa908 ;;; .word 0x1350 @@ -1183,7 +1183,7 @@ rotxr_w_disp2_2: test_ovf_clear test_neg_set - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1503,8 +1503,8 @@ rotxr_l_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - rotxr.l @(2:2, er0) ; shift right arithmetic by one, disp2 + mov #long_dest-8, er0 + rotxr.l @(8:2, er0) ; shift right arithmetic by one, disp2 ;;; .word 0x0106 ;;; .word 0xa908 ;;; .word 0x1330 @@ -1514,7 +1514,7 @@ rotxr_l_disp2_1: test_ovf_clear test_neg_clear - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1841,8 +1841,8 @@ rotxr_l_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - rotxr.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2 + mov #long_dest-8, er0 + rotxr.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 ;;; .word 0x0106 ;;; .word 0xa908 ;;; .word 0x1370 @@ -1852,7 +1852,7 @@ rotxr_l_disp2_2: test_ovf_clear test_neg_set - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s index b0ea673862..9c9166be31 100644 --- a/sim/testsuite/sim/h8300/shar.s +++ b/sim/testsuite/sim/h8300/shar.s @@ -847,8 +847,8 @@ shar_w_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - shar.w @(2:2, er0) ; shift right arithmetic by one, disp2 + mov #word_dest-4, er0 + shar.w @(4:2, er0) ; shift right arithmetic by one, disp2 ;;; .word 0x0156 ;;; .word 0x6908 ;;; .word 0x1190 @@ -858,7 +858,7 @@ shar_w_disp2_1: test_ovf_clear test_neg_set - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1170,8 +1170,8 @@ shar_w_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - shar.w #2, @(2:2, er0) ; shift right arithmetic by two, disp2 + mov #word_dest-4, er0 + shar.w #2, @(4:2, er0) ; shift right arithmetic by two, disp2 ;;; .word 0x0156 ;;; .word 0x6908 ;;; .word 0x11d0 @@ -1181,7 +1181,7 @@ shar_w_disp2_2: test_ovf_clear test_neg_set - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1501,8 +1501,8 @@ shar_l_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - shar.l @(2:2, er0) ; shift right arithmetic by one, disp2 + mov #long_dest-8, er0 + shar.l @(8:2, er0) ; shift right arithmetic by one, disp2 ;;; .word 0x0106 ;;; .word 0x6908 ;;; .word 0x11b0 @@ -1512,7 +1512,7 @@ shar_l_disp2_1: test_ovf_clear test_neg_set - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1839,8 +1839,8 @@ shar_l_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - shar.l #2, @(2:2, er0) ; shift right arithmetic by two, disp2 + mov #long_dest-8, er0 + shar.l #2, @(8:2, er0) ; shift right arithmetic by two, disp2 ;;; .word 0x0106 ;;; .word 0x6908 ;;; .word 0x11f0 @@ -1850,7 +1850,7 @@ shar_l_disp2_2: test_ovf_clear test_neg_set - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s index 14b80da6ac..f7dffc233f 100644 --- a/sim/testsuite/sim/h8300/shlr.s +++ b/sim/testsuite/sim/h8300/shlr.s @@ -1194,8 +1194,8 @@ shlr_w_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - shlr.w @(2:2, er0) ; shift right logical by one, disp2 + mov #word_dest-4, er0 + shlr.w @(4:2, er0) ; shift right logical by one, disp2 ;;; .word 0x0156 ;;; .word 0x6908 ;;; .word 0x1110 @@ -1205,7 +1205,7 @@ shlr_w_disp2_1: test_ovf_clear test_neg_clear - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1517,8 +1517,8 @@ shlr_w_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - shlr.w #2, @(2:2, er0) ; shift right logical by two, disp2 + mov #word_dest-4, er0 + shlr.w #2, @(4:2, er0) ; shift right logical by two, disp2 ;;; .word 0x0156 ;;; .word 0x6908 ;;; .word 0x1150 @@ -1528,7 +1528,7 @@ shlr_w_disp2_2: test_ovf_clear test_neg_clear - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -1838,8 +1838,8 @@ shlr_w_disp2_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - shlr.w #4, @(2:2, er0) ; shift right logical by four, disp2 + mov #word_dest-4, er0 + shlr.w #4, @(4:2, er0) ; shift right logical by four, disp2 ;;; .word 0x0156 ;;; .word 0x6908 ;;; .word 0x1120 @@ -1849,7 +1849,7 @@ shlr_w_disp2_4: test_ovf_clear test_neg_clear - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -2159,8 +2159,8 @@ shlr_w_disp2_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #word_dest-2, er0 - shlr.w #8, @(2:2, er0) ; shift right logical by eight, disp2 + mov #word_dest-4, er0 + shlr.w #8, @(4:2, er0) ; shift right logical by eight, disp2 ;;; .word 0x0156 ;;; .word 0x6908 ;;; .word 0x1160 @@ -2170,7 +2170,7 @@ shlr_w_disp2_8: test_ovf_clear test_neg_clear - test_h_gr32 word_dest-2 er0 + test_h_gr32 word_dest-4 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -2515,8 +2515,8 @@ shlr_l_disp2_1: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - shlr.l @(2:2, er0) ; shift right logical by one, disp2 + mov #long_dest-8, er0 + shlr.l @(8:2, er0) ; shift right logical by one, disp2 ;;; .word 0x0106 ;;; .word 0x6908 ;;; .word 0x1130 @@ -2526,7 +2526,7 @@ shlr_l_disp2_1: test_ovf_clear test_neg_clear - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -2853,8 +2853,8 @@ shlr_l_disp2_2: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - shlr.l #2, @(2:2, er0) ; shift right logical by two, disp2 + mov #long_dest-8, er0 + shlr.l #2, @(8:2, er0) ; shift right logical by two, disp2 ;;; .word 0x0106 ;;; .word 0x6908 ;;; .word 0x1170 @@ -2864,7 +2864,7 @@ shlr_l_disp2_2: test_ovf_clear test_neg_clear - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -3188,8 +3188,8 @@ shlr_l_disp2_4: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - shlr.l #4, @(2:2, er0) ; shift right logical by four, disp2 + mov #long_dest-8, er0 + shlr.l #4, @(8:2, er0) ; shift right logical by four, disp2 ;;; .word 0x0106 ;;; .word 0x6908 ;;; .word 0x1138 @@ -3199,7 +3199,7 @@ shlr_l_disp2_4: test_ovf_clear test_neg_clear - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -3523,8 +3523,8 @@ shlr_l_disp2_8: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - shlr.l #8, @(2:2, er0) ; shift right logical by eight, disp2 + mov #long_dest-8, er0 + shlr.l #8, @(8:2, er0) ; shift right logical by eight, disp2 ;;; .word 0x0106 ;;; .word 0x6908 ;;; .word 0x1178 @@ -3534,7 +3534,7 @@ shlr_l_disp2_8: test_ovf_clear test_neg_clear - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 @@ -3858,8 +3858,8 @@ shlr_l_disp2_16: set_grs_a5a5 ; Fill all general regs with a fixed pattern set_ccr_zero - mov #long_dest-2, er0 - shlr.l #16, @(2:2, er0) ; shift right logical by 16, dest2 + mov #long_dest-8, er0 + shlr.l #16, @(8:2, er0) ; shift right logical by 16, dest2 ;;; .word 0x0106 ;;; .word 0x6908 ;;; .word 0x11f8 @@ -3869,7 +3869,7 @@ shlr_l_disp2_16: test_ovf_clear test_neg_clear - test_h_gr32 long_dest-2 er0 + test_h_gr32 long_dest-8 er0 test_gr_a5a5 1 ; Make sure other general regs not disturbed test_gr_a5a5 2 test_gr_a5a5 3 diff --git a/sim/testsuite/sim/h8300/stc.s b/sim/testsuite/sim/h8300/stc.s index cbbd824359..232bd5a96e 100644 --- a/sim/testsuite/sim/h8300/stc.s +++ b/sim/testsuite/sim/h8300/stc.s @@ -12,28 +12,40 @@ .data byte_dest1: .byte 0 + .byte 0 byte_dest2: .byte 0 + .byte 0 byte_dest3: .byte 0 + .byte 0 byte_dest4: .byte 0 + .byte 0 byte_dest5: .byte 0 + .byte 0 byte_dest6: .byte 0 + .byte 0 byte_dest7: .byte 0 + .byte 0 byte_dest8: .byte 0 + .byte 0 byte_dest9: .byte 0 + .byte 0 byte_dest10: .byte 0 + .byte 0 byte_dest11: .byte 0 + .byte 0 byte_dest12: .byte 0 + .byte 0 start @@ -144,11 +156,11 @@ stc_ccr_disp16: set_grs_a5a5 set_ccr_zero - mov #byte_dest4, er1 + mov #byte_dest5-1, er1 ldc #0xff, ccr stc ccr, @(1:16,er1) ; disp16 dest (5) - test_h_gr32 byte_dest4, er1 ; er1 still contains address + test_h_gr32 byte_dest5-1, er1 ; er1 still contains address test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 @@ -162,11 +174,11 @@ stc_exr_disp16: set_grs_a5a5 set_ccr_zero - mov #byte_dest7, er1 + mov #byte_dest6+1, er1 ldc #0x87, exr stc exr, @(-1:16,er1) ; disp16 dest (6) - test_h_gr32 byte_dest7, er1 ; er1 still contains address + test_h_gr32 byte_dest6+1, er1 ; er1 still contains address test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 @@ -180,11 +192,11 @@ stc_ccr_disp32: set_grs_a5a5 set_ccr_zero - mov #byte_dest6, er1 + mov #byte_dest7-1, er1 ldc #0xff, ccr stc ccr, @(1:32,er1) ; disp32 dest (7) - test_h_gr32 byte_dest6, er1 ; er1 still contains address + test_h_gr32 byte_dest7-1, er1 ; er1 still contains address test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 @@ -198,11 +210,11 @@ stc_exr_disp32: set_grs_a5a5 set_ccr_zero - mov #byte_dest9, er1 + mov #byte_dest8+1, er1 ldc #0x87, exr stc exr, @(-1:32,er1) ; disp16 dest (8) - test_h_gr32 byte_dest9, er1 ; er1 still contains address + test_h_gr32 byte_dest8+1, er1 ; er1 still contains address test_gr_a5a5 2 ; Make sure other general regs not disturbed test_gr_a5a5 3 @@ -215,11 +227,11 @@ stc_ccr_predecr: set_grs_a5a5 set_ccr_zero - mov #byte_dest10, er1 + mov #byte_dest9+2, er1 ldc #0xff, ccr stc ccr, @-er1 ; predecr dest (9) - test_h_gr32 byte_dest9, er1 ; er1 still contains address + test_h_gr32 byte_dest9 er1 ; er1 still contains address test_gr_a5a5 0 ; Make sure other general regs not disturbed test_gr_a5a5 2 @@ -233,7 +245,7 @@ stc_exr_predecr: set_grs_a5a5 set_ccr_zero - mov #byte_dest11, er1 + mov #byte_dest10+2, er1 ldc #0x87, exr stc exr, @-er1 ; predecr dest (10) diff --git a/sim/testsuite/sim/h8300/subb.s b/sim/testsuite/sim/h8300/subb.s new file mode 100644 index 0000000000..01832948e8 --- /dev/null +++ b/sim/testsuite/sim/h8300/subb.s @@ -0,0 +1,289 @@ +# Hitachi H8 testcase 'sub.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # sub.b #xx:8, rd ; <illegal> + # sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx + # sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx + # sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx + # sub.b rs, rd ; 1 8 rs rd + # sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ???? + # sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs + # sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs + # + + # Coming soon: + # sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx + # sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx + # sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs + # sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +.if (0) ; Guess what? Sub.b immediate reg8 is illegal! +sub_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.b #xx:8,Rd + sub.b #5, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu == h8sx) +sub_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd + mov #byte_dest, er0 + sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa0, r0l + beq .L1 + fail +.L1: + +sub_b_imm8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd+ + mov #byte_dest, er0 + sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 still contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x9b, r0l + beq .L2 + fail +.L2: + +sub_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b #xx:8,@eRd- + mov #byte_dest, er0 + sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xa105 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte, er0 ; er0 still contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x96, r0l + beq .L3 + fail +.L3: + +.endif + +sub_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.b Rs,Rd + mov.b #5, r0h + sub.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x05a0 r0 ; sub result: a5 - 5 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5 +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +sub_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1890 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x91, r0l + beq .L4 + fail +.L4: + +sub_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd+ ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0+ ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0x8039 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte er0 ; er0 still contains address plus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x8c, r0l + beq .L5 + fail +.L5: + +sub_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; sub.b rs8,@eRd- ; Subx to register indirect + mov #byte_dest, er0 + mov #5, r1l + sub.b r1l, @er0- ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0xa039 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 still contains address minus one + test_h_gr32 0xa5a5a505 er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the sub to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x87, r0l + beq .L6 + fail +.L6: + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/subl.s b/sim/testsuite/sim/h8300/subl.s new file mode 100644 index 0000000000..7f62f11a32 --- /dev/null +++ b/sim/testsuite/sim/h8300/subl.s @@ -0,0 +1,91 @@ +# Hitachi H8 testcase 'sub.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; +sub_l_imm3: ; 3-bit immediate mode only for h8sx + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:3,eRd ; Immediate 3-bit operand + sub.l #7:3, er0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +sub_l_imm16: ; sub immediate 16-bit value + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:16,eRd ; Immediate 16-bit operand + sub.l #0x1111:16, er0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111 + test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + +sub_l_imm32: + ;; sub.l immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.l #xx:32,Rd + sub.l #0x11111111, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +sub.l.reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; add.l Rs,Rd + mov.l #0x11111111, er1 + sub.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111 + test_h_gr32 0x11111111 er1 + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/subw.s b/sim/testsuite/sim/h8300/subw.s new file mode 100644 index 0000000000..2370250706 --- /dev/null +++ b/sim/testsuite/sim/h8300/subw.s @@ -0,0 +1,78 @@ +# Hitachi H8 testcase 'sub.w' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start +.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx +sub_w_imm3: ; sub.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w #xx:3,Rd ; Immediate 3-bit operand + sub.w #7:3, r0 + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa59e r0 ; sub result: a5a5 - 7 + test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +sub_w_imm16: ; sub.w immediate not available in h8300 mode. + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w #xx:16,Rd + sub.w #0x111, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 + test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +sub.w.reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; sub.w Rs,Rd + mov.w #0x111, r1 + sub.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa494 r0 ; sub result: a5a5 - 111 + test_h_gr16 0x0111 r1 +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a494 er0 ; sub result: a5a5 - 111 + test_h_gr32 0xa5a50111 er1 +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/xorb.s b/sim/testsuite/sim/h8300/xorb.s new file mode 100644 index 0000000000..7005a95c60 --- /dev/null +++ b/sim/testsuite/sim/h8300/xorb.s @@ -0,0 +1,327 @@ +# Hitachi H8 testcase 'xor.b' +# mach(): all +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + # Instructions tested: + # xor.b #xx:8, rd ; d rd xxxxxxxx + # xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx + # xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx + # xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx + # xor.b rs, rd ; 1 5 rs rd + # xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ???? + # xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs + # xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs + # xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs + # xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs + # + + # Coming soon: + # ... + +.data +pre_byte: .byte 0 +byte_dest: .byte 0xa5 +post_byte: .byte 0 + + start + +xor_b_imm8_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.b #xx:8,Rd + xor.b #0xff, r0l ; Immediate 8-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +xor_b_imm8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd + mov #byte_dest, er0 + xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst +;;; .word 0x7d00 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 byte_dest, er0 ; er0 still contains address + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L1 + fail +.L1: + +xor_b_imm8_postinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd+ + mov #byte_dest, er0 + xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst +;;; .word 0x0174 +;;; .word 0x6c08 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 post_byte, er0 ; er0 contains address plus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L2 + fail +.L2: + +xor_b_imm8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b #xx:8,@eRd- + mov #byte_dest, er0 + xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst +;;; .word 0x0176 +;;; .word 0x6c08 +;;; .word 0xd0ff + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 pre_byte, er0 ; er0 contains address minus one + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the xor to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L3 + fail +.L3: + + +.endif + +xor_b_reg8_reg8: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.b Rs,Rd + mov.b #0xff, r0h + xor.b r0h, r0l ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.if (sim_cpu == h8sx) +xor_b_reg8_rdind: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd ; xor reg8 to register indirect + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0 ; reg8 src, reg indirect dest +;;; .word 0x7d00 +;;; .word 0x1590 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 byte_dest er0 ; er0 still contains address + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L4 + fail +.L4: + +xor_b_reg8_rdpostinc: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0+ ; reg8 src, reg post-increment dest +;;; .word 0x0179 +;;; .word 0x8059 + + test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_clear + + test_h_gr32 post_byte er0 ; er0 contains address plus one + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0x5a, r0l + beq .L5 + fail +.L5: + +xor_b_reg8_rdpostdec: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement + mov #byte_dest, er0 + mov #0xff, r1l + xor.b r1l, @er0- ; reg8 src, reg indirect dest +;;; .word 0x0179 +;;; .word 0xa059 + + test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 + test_ovf_clear + test_zero_clear + test_neg_set + + test_h_gr32 pre_byte er0 ; er0 contains address minus one + test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + ;; Now check the result of the or to memory. + sub.b r0l, r0l + mov.b @byte_dest, r0l + cmp.b #0xa5, r0l + beq .L6 + fail +.L6: + +xorc_imm8_ccr: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + set_ccr_zero + + ;; xorc #xx:8,ccr + + test_neg_clear + xorc #0x8, ccr ; Immediate 8-bit operand (neg flag) + test_neg_set + xorc #0x8, ccr + test_neg_clear + + test_zero_clear + xorc #0x4, ccr ; Immediate 8-bit operand (zero flag) + test_zero_set + xorc #0x4, ccr + test_zero_clear + + test_ovf_clear + xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag) + test_ovf_set + xorc #0x2, ccr + test_ovf_clear + + test_carry_clear + xorc #0x1, ccr ; Immediate 8-bit operand (carry flag) + test_carry_set + xorc #0x1, ccr + test_carry_clear + + test_gr_a5a5 0 ; Make sure other general regs not disturbed + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +.endif + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/xorl.s b/sim/testsuite/sim/h8300/xorl.s new file mode 100644 index 0000000000..67b2e49fb0 --- /dev/null +++ b/sim/testsuite/sim/h8300/xorl.s @@ -0,0 +1,77 @@ +# Hitachi H8 testcase 'xor.l' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. +xor_l_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l #xx:16,Rd + xor.l #0xffff:16, er0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5a5a5 | ffff + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +xor_l_imm32: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l #xx:32,Rd + xor.l #0xffffffff, er0 ; Immediate 32-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff + + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + +xor_l_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.l Rs,Rd + mov.l #0xffffffff, er1 + xor.l er1, er0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + + test_h_gr32 0x5a5a5a5a er0 ; xor result: a5a5a5a5 ^ ffffffff + test_h_gr32 0xffffffff er1 ; Make sure er1 is unchanged + + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 diff --git a/sim/testsuite/sim/h8300/xorw.s b/sim/testsuite/sim/h8300/xorw.s new file mode 100644 index 0000000000..3c5e5b868e --- /dev/null +++ b/sim/testsuite/sim/h8300/xorw.s @@ -0,0 +1,61 @@ +# Hitachi H8 testcase 'xor.w' +# mach(): h8300h h8300s h8sx +# as(h8300): --defsym sim_cpu=0 +# as(h8300h): --defsym sim_cpu=1 +# as(h8300s): --defsym sim_cpu=2 +# as(h8sx): --defsym sim_cpu=3 +# ld(h8300h): -m h8300helf +# ld(h8300s): -m h8300self +# ld(h8sx): -m h8300sxelf + + .include "testutils.inc" + + start + +.if (sim_cpu) ; non-zero means h8300h, s, or sx +xor_w_imm16: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.w #xx:16,Rd + xor.w #0xffff, r0 ; Immediate 16-bit operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff +.endif + test_gr_a5a5 1 ; Make sure other general regs not disturbed + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 +.endif + +xor_w_reg: + set_grs_a5a5 ; Fill all general regs with a fixed pattern + ;; fixme set ccr + + ;; xor.w Rs,Rd + mov.w #0xffff, r1 + xor.w r1, r0 ; Register operand + + ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 + test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff + test_h_gr16 0xffff r1 ; Make sure r1 is unchanged +.if (sim_cpu) ; non-zero means h8300h, s, or sx + test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff + test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged +.endif + test_gr_a5a5 2 ; Make sure other general regs not disturbed + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + + pass + + exit 0 |
