diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 12 | ||||
| -rw-r--r-- | opcodes/ppc-dis.c | 14 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 112 |
3 files changed, 130 insertions, 8 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f6a0abff42..42a099692e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2012-03-10 Edmar Wienskoski <edmar@freescale.com> + + * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". + * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. + (PPCVEC2, PPCTMR, E6500): New short names. + (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, + mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, + lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, + lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, + lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC + optional operands on sync instruction for E6500 target. + 2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt: Set instruction type of pku to SS_L2RDRD. diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index e0113923c3..e1c9f1b05c 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -1,6 +1,6 @@ /* ppc-dis.c -- Disassemble PowerPC instructions Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, - 2008, 2009, 2010 Free Software Foundation, Inc. + 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of the GNU opcodes library. @@ -114,6 +114,18 @@ struct ppc_mopt ppc_opts[] = { | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 0 }, + { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI + | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 + | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_POWER7), + 0 }, + { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI + | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC + | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4 + | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), + 0 }, { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index f5c4616731..b11b5b2cc7 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1,6 +1,6 @@ /* ppc-opc.c -- PowerPC opcode list Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, - 2005, 2006, 2007, 2008, 2009, 2010, 2011 + 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support @@ -53,6 +53,7 @@ static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); static long extract_boe (unsigned long, ppc_cpu_t, int *); static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); static long extract_fxm (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); static long extract_mbe (unsigned long, ppc_cpu_t, int *); static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); @@ -477,6 +478,7 @@ const struct powerpc_operand powerpc_operands[] = lower 5 bits are stored in the upper 5 and vice- versa. */ #define SPR SISIGNOPT + 1 #define PMR SPR +#define TMR SPR #define SPR_MASK (0x3ff << 11) { 0x3ff, 11, insert_spr, extract_spr, 0 }, @@ -499,8 +501,12 @@ const struct powerpc_operand powerpc_operands[] = #define T STRM { 0x3, 21, NULL, NULL, 0 }, + /* The ESYNC field in an X (sync) form instruction. */ +#define ESYNC STRM + 1 + { 0xf, 16, insert_ls, NULL, PPC_OPERAND_OPTIONAL }, + /* The SV field in a POWER SC form instruction. */ -#define SV STRM + 1 +#define SV ESYNC + 1 { 0x3fff, 2, NULL, NULL, 0 }, /* The TBR field in an XFX form instruction. This is like the SPR @@ -542,6 +548,7 @@ const struct powerpc_operand powerpc_operands[] = /* The UIMM field in a VX form instruction. */ #define UIMM SIMM + 1 +#define DCTL UIMM { 0x1f, 16, NULL, NULL, 0 }, /* The SHB field in a VA form instruction. */ @@ -1036,6 +1043,32 @@ extract_fxm (unsigned long insn, return mask; } +/* The LS field in a sync instruction that accepts 2 operands + Values 2 and 3 are reserved, + must be treated as 0 for future compatibility + Values 0 and 1 can be accepted, if field ESYNC is zero + Otherwise L = complement of ESYNC-bit2 (1<<18) */ + +static unsigned long +insert_ls (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + unsigned long ls; + + ls = (insn >> 21) & 0x03; + if (value == 0) + { + if (ls > 1) + return insn & ~(0x3 << 21); + return insn; + } + if ((value & 0x2) != 0) + return (insn & ~(0x3 << 21)) | ((value & 0xf) << 16); + return (insn & ~(0x3 << 21)) | (0x1 << 21) | ((value & 0xf) << 16); +} + /* The MB and ME fields in an M form instruction expressed as a single operand which is itself a bitmask. The extraction function always marks it as invalid, since we never want to recognize an @@ -1804,6 +1837,9 @@ extract_dm (unsigned long insn, /* An X form sync instruction with everything filled in except the LS field. */ #define XSYNC_MASK (0xff9fffff) +/* An X form sync instruction with everything filled in except the L and E fields. */ +#define XSYNCLE_MASK (0xff90ffff) + /* An X_MASK, but with the EH bit clear. */ #define XEH_MASK (X_MASK & ~((unsigned long )1)) @@ -1998,6 +2034,7 @@ extract_dm (unsigned long insn, #define PPC860 PPC #define PPCPS PPC_OPCODE_PPCPS #define PPCVEC PPC_OPCODE_ALTIVEC +#define PPCVEC2 PPC_OPCODE_ALTIVEC2 #define PPCVSX PPC_OPCODE_VSX #define POWER PPC_OPCODE_POWER #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 @@ -2016,6 +2053,7 @@ extract_dm (unsigned long insn, #define PPCEFS PPC_OPCODE_EFS #define PPCBRLK PPC_OPCODE_BRLOCK #define PPCPMR PPC_OPCODE_PMR +#define PPCTMR PPC_OPCODE_TMR #define PPCCHLK PPC_OPCODE_CACHELCK #define PPCRFMCI PPC_OPCODE_RFMCI #define E500MC PPC_OPCODE_E500MC @@ -2023,6 +2061,7 @@ extract_dm (unsigned long insn, #define TITAN PPC_OPCODE_TITAN #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN #define E500 PPC_OPCODE_E500 +#define E6500 PPC_OPCODE_E6500 /* The opcode table. @@ -2189,12 +2228,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"vabsdub", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, {"machhws", XO (4, 108,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"machhws.", XO (4, 108,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vabsduh", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, {"vslb", VX (4, 260), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, @@ -2207,6 +2248,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"macchwu", XO (4, 140,0,0),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, {"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW, PPCNONE, {RT, RA, RB}}, +{"vabsduw", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, {"vslh", VX (4, 324), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, PPCNONE, {VD, VA, VB}}, @@ -3690,6 +3732,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, PPCNONE, {RT, RA, RB}}, +{"dni", XRC(31,97,1), XRB_MASK, E6500, PPCNONE, {DUI, DCTL}}, + {"lvx", X(31,103), X_MASK, PPCVEC, PPCNONE, {VD, RA, RB}}, {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, @@ -3699,6 +3743,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mul", XO(31,107,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"mul.", XO(31,107,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"mvidsplt", X(31,110), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}}, + {"mtsrdin", X(31,114), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, {"lharx", X(31,116), XEH_MASK, POWER7, PPCNONE, {RT, RA0, RB, EH}}, @@ -3733,7 +3779,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, PPCNONE, {RT, RA, RB}}, {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, -{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, +{"mviwsplt", X(31,142), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}}, + +{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}}, {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, PPCNONE, {FXM, RS}}, @@ -3770,7 +3818,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, -{"dcbtlse", X(31,174), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, +{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, PPCNONE, {RS, A_L}}, @@ -3788,6 +3836,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}}, +{"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}}, + {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA, RB}}, {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, @@ -3865,8 +3915,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, PPCNONE, {RS, RA}}, +{"lvexbx", X(31,261), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"icbt", X(31,262), XRT_MASK, PPC403, PPCNONE, {RA, RB}}, +{"lvepxl", X(31,263), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, @@ -3900,6 +3954,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdcrux", X(31,291), X_MASK, PPC464, PPCNONE, {RS, RA}}, +{"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, +{"lvepx", X(31,295), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"tlbie", X(31,306), XRTLRA_MASK, PPC, TITAN, {RB, L}}, {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}}, @@ -3951,6 +4008,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {RT, SPR}}, {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, PPCNONE, {RT, SPR}}, +{"lvexwx", X(31,325), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"dcread", X(31,326), X_MASK, PPC476|TITAN, PPCNONE, {RT, RA, RB}}, {"div", XO(31,331,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, @@ -3959,6 +4018,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, PPCNONE, {RT, PMR}}, +{"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}}, {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}}, {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, PPCNONE, {RT}}, @@ -4189,6 +4249,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, PPCNONE, {RA, RS}}, +{"stvexbx", X(31,389), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE, {CT, RA, RB}}, {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, @@ -4197,7 +4259,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, -{"dcblce", X(31,398), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, +{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, {"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, @@ -4213,6 +4275,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdcrux", X(31,419), X_MASK, PPC464, PPCNONE, {RA, RS}}, +{"stvexhx", X(31,421), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + +{"dcblq.", XRC(31,422,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}}, + {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, @@ -4226,6 +4292,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mdors", 0x7f9ce378, 0xffffffff, E500MC, PPCNONE, {0}}, +{"miso", 0x7f5ad378, 0xffffffff, E6500, PPCNONE, {0}}, + {"mr", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, {"or", XRC(31,444,0), X_MASK, COM, PPCNONE, {RA, RS, RB}}, {"mr.", XRC(31,444,1), X_MASK, COM, PPCNONE, {RA, RS, RBS}}, @@ -4268,6 +4336,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN, {SPR, RS}}, {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, PPCNONE, {SPR, RS}}, +{"stvexwx", X(31,453), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}}, @@ -4278,6 +4348,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divwu.", XO(31,459,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, PPCNONE, {PMR, RS}}, +{"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}}, {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}}, {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, PPCNONE, {RS}}, @@ -4463,7 +4534,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divw", XO(31,491,0,0), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, {"divw.", XO(31,491,0,1), XO_MASK, PPC, PPCNONE, {RT, RA, RB}}, -{"icbtlse", X(31,494), X_MASK, PPCCHLK, PPCNONE, {CT, RA, RB}}, +{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, {"slbia", X(31,498), 0xffffffff, PPC64, PPCNONE, {0}}, @@ -4522,6 +4593,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lhdx", X(31,547), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, +{"lvtrx", X(31,549), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"bbelr", X(31,550), X_MASK, PPCBRLK, PPCNONE, {0}}, {"lvrx", X(31,551), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, @@ -4538,6 +4611,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lwdx", X(31,579), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, +{"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}}, @@ -4549,9 +4624,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, +{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}}, {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}}, {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}}, -{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, PPCNONE, {0}}, +{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}}, {"dcs", X(31,598), 0xffffffff, PWRCOM, PPCNONE, {0}}, @@ -4562,6 +4638,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lddx", X(31,611), X_MASK, E500MC, PPCNONE, {RT, RA, RB}}, +{"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"nego", XO(31,104,1,0), XORB_MASK, COM, PPCNONE, {RT, RA}}, @@ -4611,6 +4689,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sthdx", X(31,675), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, +{"stvfrx", X(31,677), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, @@ -4623,6 +4703,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stwdx", X(31,707), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, +{"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA, RB}}, @@ -4655,6 +4737,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stddx", X(31,739), X_MASK, E500MC, PPCNONE, {RS, RA, RB}}, +{"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, @@ -4683,6 +4767,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"srliq", XRC(31,760,0), X_MASK, M601, PPCNONE, {RA, RS, SH}}, {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, +{"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, +{"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, @@ -4715,6 +4801,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lfddx", X(31,803), X_MASK, E500MC, PPCNONE, {FRT, RA, RB}}, +{"lvtrxl", X(31,805), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, +{"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}}, @@ -4735,6 +4823,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sradi", XS(31,413,0), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, {"sradi.", XS(31,413,1), XS_MASK, PPC64, PPCNONE, {RA, RS, SH6}}, +{"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, @@ -4753,6 +4843,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, RA0, RB}}, +{"lvswxl", X(31,869), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + {"abso", XO(31,360,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, {"abso.", XO(31,360,1,1), XORB_MASK, M601, PPCNONE, {RT, RA}}, @@ -4798,6 +4890,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stfddx", X(31,931), X_MASK, E500MC, PPCNONE, {FRS, RA, RB}}, +{"stvfrxl", X(31,933), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, PPCNONE, {RA0, RB}}, {"wclrall", X(31,934), XRARB_MASK, PPCA2, PPCNONE, {L}}, {"wclr", X(31,934), X_MASK, PPCA2, PPCNONE, {L, RA0, RB}}, @@ -4826,6 +4920,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"extsb", XRC(31,954,0), XRB_MASK, PPC, PPCNONE, {RA, RS}}, {"extsb.", XRC(31,954,1), XRB_MASK, PPC, PPCNONE, {RA, RS}}, +{"stvflxl", X(31,965), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}}, {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, PPCNONE, {CT}}, @@ -4853,6 +4949,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, PPCNONE, {RA, RB}}, +{"stvswxl", X(31,997), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, + {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}}, {"nabso", XO(31,488,1,0), XORB_MASK, M601, PPCNONE, {RT, RA}}, |
