diff options
Diffstat (limited to 'gas')
35 files changed, 208 insertions, 106 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 291f436546..f7484949fe 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,24 @@ +2001-06-28 Eric Christopher <echristo@redhat.com> + H.J. Lu <hjl@gnu.org> + + * config/tc-mips.c (mips_arch): New. Use mips_arch instead + of mips_cpu for the ISA selection. + (md_longopts): Add OPTION_MARCH and OPTION_MTUNE. + (md_parse_option): Handle OPTION_MARCH and OPTION_MTUNE. + (mips_tune): New. Use mips_tune for scheduling and optimization + issues. + (append_insn): Use mips_tune and mips_arch. + (macro_build): Ditto. + (mips_ip): Ditto. + (md_begin): Handle mips_arch, mips_tune and mips_cpu. For + backwards compatability mips_cpu generates arch and tune. + (md_show_usage): Document new behavior. + + * doc/c-mips.texi (MIPS Opts): Document -march and -mtune. + Deprecate -mcpu. + + * NEWS: Update. + 2001-06-27 Nick Clifton <nickc@cambridge.redhat.com> * write.c (write_object_file): Do not set finalize_syms until @@ -1,5 +1,8 @@ -*- text -*- +The MIPS assembler now accepts -march/-mtune. -mcpu has been deprecated +but still works for compatability. + The MIPS assembler no longer issues a warning by default when it generates a nop instruction from a macro. The new command line option -n will turn on the warning. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 828b37dec0..ebe8d7f0fb 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -206,9 +206,16 @@ unsigned long mips_cprmask[4]; /* MIPS ISA we are using for this output file. */ static int file_mips_isa = ISA_UNKNOWN; -/* The CPU type we are using for this output file. */ +/* The argument of the -mcpu= flag. Historical for code generation. */ static int mips_cpu = CPU_UNKNOWN; +/* The argument of the -march= flag. The architecture we are assembling. */ +static int mips_arch = CPU_UNKNOWN; + +/* The argument of the -mtune= flag. The architecture for which we + are optimizing. */ +static int mips_tune = CPU_UNKNOWN; + /* The argument of the -mabi= flag. */ static char * mips_abi_string = 0; @@ -246,44 +253,21 @@ static int mips_gp32 = 0; /* Whether the processor uses hardware interlocks to protect reads from the HI and LO registers, and thus does not - require nops to be inserted. - - FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO: - -mcpu=FOO schedules for FOO, but still produces code that meets the - requirements of MIPS ISA I. For example, it won't generate any - FOO-specific instructions, and it will still assume that any - scheduling hazards described in MIPS ISA I are there, even if FOO - has interlocks. -mFOO gives GCC permission to generate code that - will only run on a FOO; it will generate FOO-specific instructions, - and assume interlocks provided by a FOO. - - However, GAS currently doesn't make this distinction; before Jan 28 - 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's - assumptions. The GCC driver passes these flags through to GAS, so - if GAS actually does anything that doesn't meet MIPS ISA I with - -mFOO, then GCC's -mcpu=FOO flag isn't going to work. + require nops to be inserted. */ - And furthermore, it did not assume that -mFOO implied -mcpu=FOO, - which seems senseless --- why generate code which will only run on - a FOO, but schedule for something else? - - So now, at least, -mcpu=FOO and -mFOO are exactly equivalent. - - -- Jim Blandy <jimb@cygnus.com> */ - -#define hilo_interlocks (mips_cpu == CPU_R4010 \ +#define hilo_interlocks (mips_arch == CPU_R4010 \ ) /* Whether the processor uses hardware interlocks to protect reads from the GPRs, and thus does not require nops to be inserted. */ #define gpr_interlocks \ (mips_opts.isa != ISA_MIPS1 \ - || mips_cpu == CPU_R3900) + || mips_arch == CPU_R3900) /* As with other "interlocks" this is used by hardware that has FP (co-processor) interlocks. */ /* Itbl support may require additional care here. */ -#define cop_interlocks (mips_cpu == CPU_R4300 \ +#define cop_interlocks (mips_arch == CPU_R4300 \ ) /* Is this a mfhi or mflo instruction? */ @@ -955,40 +939,56 @@ md_begin () if (mips_opts.mips16 < 0) mips_opts.mips16 = target_cpu_had_mips16; - /* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was + /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was specified on the command line, or some other value if one was. Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on the command line, or will be set otherwise if one was. */ - if (mips_cpu != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) + if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) { /* We have it all. There's nothing to do. */ } - else if (mips_cpu != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) + else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN) { - /* We have CPU, we need ISA. */ - ci = mips_cpu_info_from_cpu (mips_cpu); + /* We have ARCH, we need ISA. */ + ci = mips_cpu_info_from_cpu (mips_arch); assert (ci != NULL); mips_opts.isa = ci->isa; } - else if (mips_cpu == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) + else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN) { - /* We have ISA, we need default CPU. */ + /* We have ISA, we need default ARCH. */ ci = mips_cpu_info_from_isa (mips_opts.isa); assert (ci != NULL); - mips_cpu = ci->cpu; + mips_arch = ci->cpu; + } + else if (mips_arch == CPU_UNKNOWN + && mips_opts.isa == ISA_UNKNOWN + && mips_cpu != CPU_UNKNOWN) + { + /* Historic -mcpu= option. Warn. */ + ci = mips_cpu_info_from_cpu (mips_cpu); + assert (ci != NULL); + mips_arch = ci->cpu; + mips_tune = ci->cpu; + mips_opts.isa = ci->isa; + as_warn (_("The -mcpu option is deprecated. Please use -march and -mtune instead.")); + } else { - /* We need to set both ISA and CPU from target cpu. */ + /* We need to set both ISA and ARCH from target cpu. */ ci = mips_cpu_info_from_name (cpu); if (ci == NULL) ci = mips_cpu_info_from_cpu (CPU_R3000); assert (ci != NULL); mips_opts.isa = ci->isa; - mips_cpu = ci->cpu; + mips_arch = ci->cpu; } - ci = mips_cpu_info_from_cpu (mips_cpu); + if (mips_tune == CPU_UNKNOWN) + mips_tune = mips_arch; + + ci = mips_cpu_info_from_cpu (mips_arch); assert (ci != NULL); mips_isa_from_cpu = ci->isa; @@ -1019,7 +1019,7 @@ md_begin () && ISA_HAS_64BIT_REGS (mips_isa_from_cpu)) mips_32bitmode = 1; - if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu)) + if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch)) as_warn (_("Could not set architecture and machine")); file_mips_isa = mips_opts.isa; @@ -1593,7 +1593,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi) though the tx39's divide insns still do require the delay. */ if (! (hilo_interlocks - || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))) + || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) && (mips_optimize == 0 || (pinfo & INSN_WRITE_LO))) nops += 2; @@ -1615,7 +1615,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi) insert a NOP. Some newer processors have interlocks. Also the note tx39's multiply above. */ if (! (hilo_interlocks - || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))) + || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) && (mips_optimize == 0 || (pinfo & INSN_WRITE_HI))) nops += 2; @@ -1654,11 +1654,11 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi) || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO) && (pinfo & INSN_WRITE_LO) && ! (hilo_interlocks - || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT)))) + || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))) || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI) && (pinfo & INSN_WRITE_HI) && ! (hilo_interlocks - || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))))) + || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))) prev_prev_nop = 1; else prev_prev_nop = 0; @@ -2011,7 +2011,7 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi) | INSN_COPROC_MOVE_DELAY | INSN_WRITE_COND_CODE))) || (! (hilo_interlocks - || (mips_cpu == CPU_R3900 && (pinfo & INSN_MULT))) + || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))) && (prev_pinfo & (INSN_READ_LO | INSN_READ_HI))) @@ -2496,9 +2496,9 @@ macro_build (place, counter, ep, name, fmt, va_alist) { if (strcmp (fmt, insn.insn_mo->args) == 0 && insn.insn_mo->pinfo != INSN_MACRO - && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_cpu, + && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch, mips_gp32) - && (mips_cpu != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) + && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) break; ++insn.insn_mo; @@ -4848,7 +4848,7 @@ macro (ip) lr = 1; goto ld; case M_LDC1_AB: - if (mips_cpu == CPU_R4650) + if (mips_arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -4937,7 +4937,7 @@ macro (ip) s = "scd"; goto st; case M_SDC1_AB: - if (mips_cpu == CPU_R4650) + if (mips_arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -5425,7 +5425,7 @@ macro (ip) } case M_L_DOB: - if (mips_cpu == CPU_R4650) + if (mips_arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -5466,7 +5466,7 @@ macro (ip) * But, the resulting address is the same after relocation so why * generate the extra instruction? */ - if (mips_cpu == CPU_R4650) + if (mips_arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -5484,7 +5484,7 @@ macro (ip) goto ldd_std; case M_S_DAB: - if (mips_cpu == CPU_R4650) + if (mips_arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -6113,7 +6113,7 @@ macro2 (ip) break; case M_S_DOB: - if (mips_cpu == CPU_R4650) + if (mips_arch == CPU_R4650) { as_bad (_("opcode not supported on this processor")); return; @@ -7084,14 +7084,14 @@ mips_ip (str, ip) assert (strcmp (insn->name, str) == 0); - if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_cpu, mips_gp32)) + if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch, mips_gp32)) ok = true; else ok = false; if (insn->pinfo != INSN_MACRO) { - if (mips_cpu == CPU_R4650 && (insn->pinfo & FP_D) != 0) + if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0) ok = false; } @@ -7110,7 +7110,7 @@ mips_ip (str, ip) static char buf[100]; sprintf (buf, _("opcode not supported on this processor: %s (%s)"), - mips_cpu_to_str (mips_cpu), + mips_cpu_to_str (mips_arch), mips_isa_to_str (mips_opts.isa)); insn_error = buf; @@ -8941,6 +8941,10 @@ struct option md_longopts[] = {"mips5", no_argument, NULL, OPTION_MIPS5}, #define OPTION_MIPS64 (OPTION_MD_BASE + 30) {"mips64", no_argument, NULL, OPTION_MIPS64}, +#define OPTION_MARCH (OPTION_MD_BASE + 31) + {"march", required_argument, NULL, OPTION_MARCH}, +#define OPTION_MTUNE (OPTION_MD_BASE + 32) + {"mtune", required_argument, NULL, OPTION_MTUNE}, #ifdef OBJ_ELF #define OPTION_ELF_BASE (OPTION_MD_BASE + 35) #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0) @@ -9042,47 +9046,78 @@ md_parse_option (c, arg) mips_opts.isa = ISA_MIPS64; break; + case OPTION_MTUNE: + case OPTION_MARCH: case OPTION_MCPU: { + int cpu = CPU_UNKNOWN; + /* Identify the processor type. */ - if (strcasecmp (arg, "default") == 0) - mips_cpu = CPU_UNKNOWN; - else + if (strcasecmp (arg, "default") != 0) { const struct mips_cpu_info *ci; ci = mips_cpu_info_from_name (arg); if (ci == NULL || ci->is_isa) - as_bad (_("invalid architecture -mcpu=%s"), arg); + { + switch (c) + { + case OPTION_MTUNE: + as_fatal (_("invalid architecture -mtune=%s"), arg); + break; + case OPTION_MARCH: + as_fatal (_("invalid architecture -march=%s"), arg); + break; + case OPTION_MCPU: + as_fatal (_("invalid architecture -mcpu=%s"), arg); + break; + } + } else - mips_cpu = ci->cpu; + cpu = ci->cpu; + } + + switch (c) + { + case OPTION_MTUNE: + mips_tune = cpu; + break; + case OPTION_MARCH: + mips_arch = cpu; + break; + case OPTION_MCPU: + mips_cpu = cpu; } } break; case OPTION_M4650: - mips_cpu = CPU_R4650; + mips_arch = CPU_R4650; + mips_tune = CPU_R4650; break; case OPTION_NO_M4650: break; case OPTION_M4010: - mips_cpu = CPU_R4010; + mips_arch = CPU_R4010; + mips_tune = CPU_R4010; break; case OPTION_NO_M4010: break; case OPTION_M4100: - mips_cpu = CPU_VR4100; + mips_arch = CPU_VR4100; + mips_tune = CPU_VR4100; break; case OPTION_NO_M4100: break; case OPTION_M3900: - mips_cpu = CPU_R3900; + mips_arch = CPU_R3900; + mips_tune = CPU_R3900; break; case OPTION_NO_M3900: @@ -9288,7 +9323,7 @@ MIPS options:\n\ -mips5 generate MIPS ISA V instructions\n\ -mips32 generate MIPS32 ISA instructions\n\ -mips64 generate MIPS64 ISA instructions\n\ --mcpu=CPU generate code for CPU, where CPU is one of:\n")); +-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); first = 1; @@ -9313,7 +9348,7 @@ MIPS options:\n\ fputc ('\n', stream); fprintf (stream, _("\ --mCPU equivalent to -mcpu=CPU.\n\ +-mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\ -no-mCPU don't generate code specific to CPU.\n\ For -mCPU and -no-mCPU, CPU must be one of:\n")); diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 64b7882d1b..177e5980d3 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -72,7 +72,7 @@ Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA processors, respectively. You can also switch instruction sets during the assembly; see @ref{MIPS ISA, Directives to -override the ISA level}. +override the ISA level}. @item -mgp32 Assume that 32-bit general purpose registers are available. This @@ -121,7 +121,7 @@ For each option @samp{-m@var{nnnn}}, generate code for the MIPS @sc{r@var{nnnn}} chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards. -@item -mcpu=@var{cpu} +@item -march=@var{cpu} Generate code for a particular MIPS cpu. It is exactly equivalent to @samp{-m@var{cpu}}, except that there are more value of @var{cpu} understood. Valid @var{cpu} value are: @@ -152,6 +152,16 @@ mips32-4k, sb1 @end quotation +@item -mtune=@var{cpu} +Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are +identical to @samp{-march=@var{cpu}}. + +@item -mcpu=@var{cpu} +Generate code and schedule for a particular MIPS cpu. This is exactly +equivalent to @samp{-march=@var{cpu}} and @samp{-mtune=@var{cpu}}. Valid +@var{cpu} values are identical to @samp{-march=@var{cpu}}. +Use of this option is discouraged. + @cindex @code{-nocpp} ignored (MIPS) @item -nocpp @@ -258,13 +268,13 @@ mips0} restores the @sc{isa} level to its original level: either the level you selected with command line options, or the default for your configuration. You can use this feature to permit specific @sc{r4000} instructions while assembling in 32 bit mode. Use this directive with -care! +care! The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor. Use @samp{.set nomips16} to return to normal 32 bit mode. -Traditional @sc{mips} assemblers do not support this directive. +Traditional @sc{mips} assemblers do not support this directive. @node MIPS autoextend @section Directives for extending MIPS 16 bit instructions diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 01e5ebb871..71c999dc00 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,37 @@ +2001-06-28 Eric Christopher <echristo@redhat.com> + + * gas/mips/usd.d: Change for march/mtune. + * gas/mips/ulh-xgot.d: Ditto. + * gas/mips/uld.d: Ditto. + * gas/mips/trunc.d: Ditto. + * gas/mips/rol.d: Ditto. + * gas/mips/nodelay.d: Ditto. + * gas/mips/mul.d: Ditto. + * gas/mips/mul-ilocks.d: Ditto. + * gas/mips/trap20.d: Ditto. + * gas/mips/mips4.d: Ditto. + * gas/mips/mips16.d: Ditto. + * gas/mips/lif-xgot.d: Ditto. + * gas/mips/lif-svr4pic.d: Ditto. + * gas/mips/ld-xgot.d: Ditto. + * gas/mips/ld-svr4pic.d: Ditto. + * gas/mips/ld-ilocks-addr32.d: Ditto. + * gas/mips/lb-xgot.d: Ditto. + * gas/mips/jal-xgot.d: Ditto. + * gas/mips/jal-svr4pic.d: Ditto. + * gas/mips/delay.d: Ditto. + * gas/mips/lb-xgot-ilocks.d: Ditto. + * gas/mips/div.d: Ditto. + * gas/mips/break20.d: Ditto. + * gas/mips/delay.d: Ditto. + * gas/mips/elf_e_flags3.d: Ditto. + * gas/mips/elf_e_flags4.d: Ditto. + * gas/mips/lineno.d: Ditto. + * gas/mips/mips16.d: Ditto. + * gas/mips/mips4.d: Ditto. + * gas/mips/mips4010.d: Ditto. + * gas/mips/mips4650.d: Ditto. + 2001-06-21 Nick Clifton <nickc@cambridge.redhat.com> * gas/arm/arm.exp: Remove msr-bad.s test. @@ -13,7 +47,7 @@ * gas/ppc/aix.exp: New file, aix specific tests. * gas/ppc/align.s: New file, .comm alignment test. - + 2001-06-13 Andreas Jaeger <aj@suse.de> * gas/vtable/vtable.exp (run_list_test): Don't run on sparc64. diff --git a/gas/testsuite/gas/mips/break20.d b/gas/testsuite/gas/mips/break20.d index 4498a4cd87..31318984ec 100644 --- a/gas/testsuite/gas/mips/break20.d +++ b/gas/testsuite/gas/mips/break20.d @@ -1,4 +1,4 @@ -#as: -mcpu=r3900 +#as: -march=r3900 #objdump: -dr --prefix-addresses -mmips:3900 #name: MIPS 20-bit break @@ -15,4 +15,4 @@ Disassembly of section .text: 0+001c <[^>]*> sdbbp 0x14 0+0020 <[^>]*> sdbbp 0x14,0x28 0+0024 <[^>]*> sdbbp 0x3ff,0x3ff - ...
\ No newline at end of file + ... diff --git a/gas/testsuite/gas/mips/delay.d b/gas/testsuite/gas/mips/delay.d index 03b2e15f73..dde5c0a9d3 100644 --- a/gas/testsuite/gas/mips/delay.d +++ b/gas/testsuite/gas/mips/delay.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:4000 #name: MIPS delay -#as: -mips3 -mcpu=r4000 +#as: -mips3 -mtune=r4000 # # Gas should produce nop's after mtc1 and related diff --git a/gas/testsuite/gas/mips/div.d b/gas/testsuite/gas/mips/div.d index ffd5675233..6d60da50fc 100644 --- a/gas/testsuite/gas/mips/div.d +++ b/gas/testsuite/gas/mips/div.d @@ -1,5 +1,5 @@ +#as: -march=r4000 -mtune=r4000 #objdump: -dr --prefix-addresses -mmips:4000 -#as: -mcpu=r4000 #name: MIPS div # Test the div macro. diff --git a/gas/testsuite/gas/mips/elf_e_flags3.d b/gas/testsuite/gas/mips/elf_e_flags3.d index acfde0b1a4..9ba5042d06 100644 --- a/gas/testsuite/gas/mips/elf_e_flags3.d +++ b/gas/testsuite/gas/mips/elf_e_flags3.d @@ -1,6 +1,6 @@ -# name: ELF e_flags: -mcpu=4650 +# name: ELF e_flags: -march=4650 -mtune=4650 # source: elf_e_flags.s -# as: -mcpu=4650 +# as: -march=4650 -mtune=4650 # objdump: -fd .*:.*file format.*mips.* diff --git a/gas/testsuite/gas/mips/elf_e_flags4.d b/gas/testsuite/gas/mips/elf_e_flags4.d index 36489cda84..9ba5042d06 100644 --- a/gas/testsuite/gas/mips/elf_e_flags4.d +++ b/gas/testsuite/gas/mips/elf_e_flags4.d @@ -1,6 +1,6 @@ -# name: ELF e_flags: -m4650 -mcpu=4650 +# name: ELF e_flags: -march=4650 -mtune=4650 # source: elf_e_flags.s -# as: -m4650 -mcpu=4650 +# as: -march=4650 -mtune=4650 # objdump: -fd .*:.*file format.*mips.* diff --git a/gas/testsuite/gas/mips/jal-svr4pic.d b/gas/testsuite/gas/mips/jal-svr4pic.d index 44af20a1a8..5dc94c284a 100644 --- a/gas/testsuite/gas/mips/jal-svr4pic.d +++ b/gas/testsuite/gas/mips/jal-svr4pic.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS R3000 jal-svr4pic -#as: -mips1 -KPIC -mcpu=r3000 +#as: -mips1 -KPIC -mtune=r3000 # Test the jal macro with -KPIC. diff --git a/gas/testsuite/gas/mips/jal-xgot.d b/gas/testsuite/gas/mips/jal-xgot.d index 318b50bd6b..8792c9b8c6 100644 --- a/gas/testsuite/gas/mips/jal-xgot.d +++ b/gas/testsuite/gas/mips/jal-xgot.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS R3000 jal-xgot -#as: -mips1 -KPIC -xgot -mcpu=r3000 +#as: -mips1 -KPIC -xgot -mtune=r3000 #source: jal-svr4pic.s # Test the jal macro with -KPIC -xgot. diff --git a/gas/testsuite/gas/mips/lb-xgot-ilocks.d b/gas/testsuite/gas/mips/lb-xgot-ilocks.d index d949bfdf41..06aca8a0c8 100644 --- a/gas/testsuite/gas/mips/lb-xgot-ilocks.d +++ b/gas/testsuite/gas/mips/lb-xgot-ilocks.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS lb-xgot-ilocks -#as: -mips1 -KPIC -xgot -mcpu=r3900 +#as: -mips1 -KPIC -xgot -mtune=r3900 #source: lb-pic.s # Test the lb macro with -KPIC -xgot. diff --git a/gas/testsuite/gas/mips/lb-xgot.d b/gas/testsuite/gas/mips/lb-xgot.d index da84c8fd8e..27dfad5f8d 100644 --- a/gas/testsuite/gas/mips/lb-xgot.d +++ b/gas/testsuite/gas/mips/lb-xgot.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS lb-xgot -#as: -mips1 -KPIC -xgot -mcpu=r3000 +#as: -mips1 -KPIC -xgot -mtune=r3000 #source: lb-pic.s # Test the lb macro with -KPIC -xgot. diff --git a/gas/testsuite/gas/mips/ld-ilocks-addr32.d b/gas/testsuite/gas/mips/ld-ilocks-addr32.d index 30cf382738..52c6d2f605 100644 --- a/gas/testsuite/gas/mips/ld-ilocks-addr32.d +++ b/gas/testsuite/gas/mips/ld-ilocks-addr32.d @@ -1,5 +1,5 @@ #objdump: -dr --prefix-addresses -mmips:4000 -#as: -mips3 -mcpu=r4000 +#as: -mips3 -mtune=r4000 -march=r4000 #name: MIPS ld-ilocks #source: ld.s @@ -629,4 +629,3 @@ Disassembly of section .text: 0+05c4 <[^>]*> sd a0,-23131\(at\) [ ]*5c4: [A-Z0-9_]*LO[A-Z0-9_]* .sbss.* 0+05c8 <[^>]*> nop - diff --git a/gas/testsuite/gas/mips/ld-svr4pic.d b/gas/testsuite/gas/mips/ld-svr4pic.d index 31860f41a6..b41b257b39 100644 --- a/gas/testsuite/gas/mips/ld-svr4pic.d +++ b/gas/testsuite/gas/mips/ld-svr4pic.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS ld-svr4pic -#as: -mips1 -mcpu=r3000 -KPIC +#as: -mips1 -mtune=r3000 -KPIC #source: ld-pic.s # Test the ld macro with -KPIC. diff --git a/gas/testsuite/gas/mips/ld-xgot.d b/gas/testsuite/gas/mips/ld-xgot.d index c864b56b23..d5456baa2c 100644 --- a/gas/testsuite/gas/mips/ld-xgot.d +++ b/gas/testsuite/gas/mips/ld-xgot.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS ld-xgot -#as: -mips1 -mcpu=r3000 -KPIC -xgot +#as: -mips1 -mtune=r3000 -KPIC -xgot #source: ld-pic.s # Test the ld macro with -KPIC -xgot. diff --git a/gas/testsuite/gas/mips/ld.d b/gas/testsuite/gas/mips/ld.d index 2a6acc2e8f..b7ef4ffc08 100644 --- a/gas/testsuite/gas/mips/ld.d +++ b/gas/testsuite/gas/mips/ld.d @@ -1,5 +1,5 @@ #objdump: -dr --prefix-addresses -mmips:4000 -#as: -mcpu=r4000 +#as: -march=r4000 #name: MIPS ld # Test the ld macro. diff --git a/gas/testsuite/gas/mips/lif-svr4pic.d b/gas/testsuite/gas/mips/lif-svr4pic.d index 048bbd6944..9432ecc5c6 100644 --- a/gas/testsuite/gas/mips/lif-svr4pic.d +++ b/gas/testsuite/gas/mips/lif-svr4pic.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS lifloat-svr4pic -#as: -mips1 -mcpu=r3000 -KPIC -EB --defsym SVR4=1 +#as: -mips1 -mtune=r3000 -KPIC -EB --defsym SVR4=1 #source: lifloat.s # Test the li.d and li.s macros with -KPIC. diff --git a/gas/testsuite/gas/mips/lif-xgot.d b/gas/testsuite/gas/mips/lif-xgot.d index f4d747743b..9056c62cfc 100644 --- a/gas/testsuite/gas/mips/lif-xgot.d +++ b/gas/testsuite/gas/mips/lif-xgot.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS lifloat-xgot -#as: -mips1 -mcpu=r3000 -KPIC -xgot -EB --defsym XGOT=1 +#as: -mips1 -mtune=r3000 -KPIC -xgot -EB --defsym XGOT=1 #source: lifloat.s # Test the li.d and li.s macros with -KPIC -xgot. diff --git a/gas/testsuite/gas/mips/lineno.d b/gas/testsuite/gas/mips/lineno.d index 40a201c162..77907e596a 100644 --- a/gas/testsuite/gas/mips/lineno.d +++ b/gas/testsuite/gas/mips/lineno.d @@ -1,6 +1,6 @@ #objdump: -d -l -mmips:4000 #name: assembly line numbers -#as: -g -mcpu=r4000 +#as: -g -march=r4000 .*: +file format .*mips.* diff --git a/gas/testsuite/gas/mips/mips16.d b/gas/testsuite/gas/mips/mips16.d index 216e264914..1550529ac5 100644 --- a/gas/testsuite/gas/mips/mips16.d +++ b/gas/testsuite/gas/mips/mips16.d @@ -1,5 +1,5 @@ #objdump: -dr -mmips:4000 -#as: -mips3 -mcpu=r4000 +#as: -mips3 -mtune=r4000 #name: mips16 # Test the mips16 instruction set. diff --git a/gas/testsuite/gas/mips/mips4.d b/gas/testsuite/gas/mips/mips4.d index 874e420c3e..0c20f8ac80 100644 --- a/gas/testsuite/gas/mips/mips4.d +++ b/gas/testsuite/gas/mips/mips4.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:5000 #name: MIPS mips4 -#as: -mips4 -mcpu=r5000 +#as: -mips4 -mtune=r5000 # Test the mips4 macros. diff --git a/gas/testsuite/gas/mips/mips4010.d b/gas/testsuite/gas/mips/mips4010.d index 49fa381cf8..12e8ac1988 100644 --- a/gas/testsuite/gas/mips/mips4010.d +++ b/gas/testsuite/gas/mips/mips4010.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:4010 #name: MIPS 4010 -#as: -mcpu=4010 +#as: -march=4010 .*: +file format .*mips.* diff --git a/gas/testsuite/gas/mips/mips4100.d b/gas/testsuite/gas/mips/mips4100.d index f471990167..4ef2e19342 100644 --- a/gas/testsuite/gas/mips/mips4100.d +++ b/gas/testsuite/gas/mips/mips4100.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:4100 #name: MIPS 4100 -#as: -mcpu=4100 +#as: -march=4100 .*: +file format .*mips.* diff --git a/gas/testsuite/gas/mips/mips4650.d b/gas/testsuite/gas/mips/mips4650.d index 4b65809882..2e68a37cf7 100644 --- a/gas/testsuite/gas/mips/mips4650.d +++ b/gas/testsuite/gas/mips/mips4650.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:4650 #name: MIPS 4650 -#as: -mcpu=4650 +#as: -march=4650 -mtune=4650 .*: +file format .*mips.* diff --git a/gas/testsuite/gas/mips/mul-ilocks.d b/gas/testsuite/gas/mips/mul-ilocks.d index ba9c10e15f..9450a04f76 100644 --- a/gas/testsuite/gas/mips/mul-ilocks.d +++ b/gas/testsuite/gas/mips/mul-ilocks.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses #name: MIPS mul-ilocks -#as: +#as: -march=r4000 -mtune=r4000 #source: mul.s # Test the mul macro. diff --git a/gas/testsuite/gas/mips/mul.d b/gas/testsuite/gas/mips/mul.d index ab25f12c99..1c4f78419f 100644 --- a/gas/testsuite/gas/mips/mul.d +++ b/gas/testsuite/gas/mips/mul.d @@ -1,5 +1,5 @@ #objdump: -dr --prefix-addresses -mmips:4000 -#as: -mcpu=r4000 +#as: -march=r4000 -mtune=r4000 #name: MIPS mul # Test the mul macro. diff --git a/gas/testsuite/gas/mips/nodelay.d b/gas/testsuite/gas/mips/nodelay.d index f21e73bb01..7e4da4097b 100644 --- a/gas/testsuite/gas/mips/nodelay.d +++ b/gas/testsuite/gas/mips/nodelay.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:5000 #name: MIPS nodelay -#as: -mips4 -mcpu=r8000 +#as: -mips4 -mtune=r8000 #source: delay.s # For -mips4 diff --git a/gas/testsuite/gas/mips/rol.d b/gas/testsuite/gas/mips/rol.d index 05addb4f5d..78f39f12a1 100644 --- a/gas/testsuite/gas/mips/rol.d +++ b/gas/testsuite/gas/mips/rol.d @@ -1,5 +1,5 @@ #objdump: -dr --prefix-addresses -mmips:3000 -#as: -mcpu=r3000 +#as: -march=r3000 -mtune=r3000 #name: MIPS R3000 rol # Test the rol and ror macros. diff --git a/gas/testsuite/gas/mips/trap20.d b/gas/testsuite/gas/mips/trap20.d index 3a77230116..7bde8448b9 100644 --- a/gas/testsuite/gas/mips/trap20.d +++ b/gas/testsuite/gas/mips/trap20.d @@ -1,4 +1,4 @@ -#as: -mcpu=r4000 +#as: -march=r4000 #objdump: -dr --prefix-addresses -mmips:4000 #name: MIPS 20-bit trap diff --git a/gas/testsuite/gas/mips/trunc.d b/gas/testsuite/gas/mips/trunc.d index 8276e3fbc3..0087c02f13 100644 --- a/gas/testsuite/gas/mips/trunc.d +++ b/gas/testsuite/gas/mips/trunc.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS trunc -#as: -mips1 -mcpu=r3000 +#as: -mips1 -mtune=r3000 # Test the trunc macros. diff --git a/gas/testsuite/gas/mips/uld.d b/gas/testsuite/gas/mips/uld.d index 06c83dd574..b5632926bc 100644 --- a/gas/testsuite/gas/mips/uld.d +++ b/gas/testsuite/gas/mips/uld.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:4000 #name: MIPS uld -#as: -mips3 -mcpu=r4000 +#as: -mips3 -mtune=r4000 # Test the uld macro. diff --git a/gas/testsuite/gas/mips/ulh-xgot.d b/gas/testsuite/gas/mips/ulh-xgot.d index 96d47ddc79..4ee5b6b8b2 100644 --- a/gas/testsuite/gas/mips/ulh-xgot.d +++ b/gas/testsuite/gas/mips/ulh-xgot.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:3000 #name: MIPS ulh-xgot -#as: -mips1 -mcpu=r3000 -KPIC -xgot -EB --defsym XGOT=1 +#as: -mips1 -mtune=r3000 -KPIC -xgot -EB --defsym XGOT=1 #source: ulh-pic.s # Test the unaligned load and store macros with -KPIC -xgot. diff --git a/gas/testsuite/gas/mips/usd.d b/gas/testsuite/gas/mips/usd.d index 7aa701deed..0e9da49c23 100644 --- a/gas/testsuite/gas/mips/usd.d +++ b/gas/testsuite/gas/mips/usd.d @@ -1,6 +1,6 @@ #objdump: -dr --prefix-addresses -mmips:4000 #name: MIPS usd -#as: -mips3 -mcpu=r4000 +#as: -mips3 -mtune=r4000 # Test the usd macro. |
