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-rw-r--r--gas/testsuite/gas/arm/arch7.d76
-rw-r--r--gas/testsuite/gas/arm/arch7.s79
-rw-r--r--gas/testsuite/gas/arm/arch7m-bad.d4
-rw-r--r--gas/testsuite/gas/arm/arch7m-bad.l5
-rw-r--r--gas/testsuite/gas/arm/arch7m-bad.s7
-rw-r--r--gas/testsuite/gas/arm/thumb32.d20
6 files changed, 181 insertions, 10 deletions
diff --git a/gas/testsuite/gas/arm/arch7.d b/gas/testsuite/gas/arm/arch7.d
new file mode 100644
index 0000000000..f656340828
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7.d
@@ -0,0 +1,76 @@
+#name: ARM V7 instructions
+#as: -march=armv7r
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> f6d6f008 pli \[r6, r8\]
+0+004 <[^>]*> f6d9f007 pli \[r9, r7\]
+0+008 <[^>]*> f6d0f101 pli \[r0, r1, lsl #2\]
+0+00c <[^>]*> f4d5f000 pli \[r5\]
+0+010 <[^>]*> f4d5ffff pli \[r5, #4095\]
+0+014 <[^>]*> f455ffff pli \[r5, #-4095\]
+0+018 <[^>]*> e320f0f0 dbg #0
+0+01c <[^>]*> e320f0ff dbg #15
+0+020 <[^>]*> f57ff05f dmb sy
+0+024 <[^>]*> f57ff05f dmb sy
+0+028 <[^>]*> f57ff04f dsb sy
+0+02c <[^>]*> f57ff04f dsb sy
+0+030 <[^>]*> f57ff047 dsb un
+0+034 <[^>]*> f57ff04e dsb st
+0+038 <[^>]*> f57ff046 dsb unst
+0+03c <[^>]*> f57ff06f isb sy
+0+040 <[^>]*> f57ff06f isb sy
+0+044 <[^>]*> f916 f008 pli \[r6, r8\]
+0+048 <[^>]*> f919 f007 pli \[r9, r7\]
+0+04c <[^>]*> f910 f021 pli \[r0, r1, lsl #2\]
+0+050 <[^>]*> f995 f000 pli \[r5\]
+0+054 <[^>]*> f995 ffff pli \[r5, #4095\]
+0+058 <[^>]*> f915 fcff pli \[r5, #-255\]
+0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0000105f <[^>]*>
+0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; fffff065 <[^>]*>
+0+064 <[^>]*> f3af 80f0 dbg #0
+0+068 <[^>]*> f3af 80ff dbg #15
+0+06c <[^>]*> f3bf 8f5f dmb sy
+0+070 <[^>]*> f3bf 8f5f dmb sy
+0+074 <[^>]*> f3bf 8f4f dsb sy
+0+078 <[^>]*> f3bf 8f4f dsb sy
+0+07c <[^>]*> f3bf 8f47 dsb un
+0+080 <[^>]*> f3bf 8f4e dsb st
+0+084 <[^>]*> f3bf 8f46 dsb unst
+0+088 <[^>]*> f3bf 8f6f isb sy
+0+08c <[^>]*> f3bf 8f6f isb sy
+0+090 <[^>]*> fb99 f6fc sdiv r6, r9, ip
+0+094 <[^>]*> fb96 f9f3 sdiv r9, r6, r3
+0+098 <[^>]*> fbb6 f9f3 udiv r9, r6, r3
+0+09c <[^>]*> fbb9 f6fc udiv r6, r9, ip
+# V7M APSR has the same encoding as V7A CPSR_f
+0+0a0 <[^>]*> f3ef 8000 mrs r0, (CPSR|APSR)
+0+0a4 <[^>]*> f3ef 8001 mrs r0, IAPSR
+0+0a8 <[^>]*> f3ef 8002 mrs r0, EAPSR
+0+0ac <[^>]*> f3ef 8003 mrs r0, PSR
+0+0b0 <[^>]*> f3ef 8005 mrs r0, IPSR
+0+0b4 <[^>]*> f3ef 8006 mrs r0, EPSR
+0+0b8 <[^>]*> f3ef 8007 mrs r0, IEPSR
+0+0bc <[^>]*> f3ef 8008 mrs r0, MSP
+0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
+0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
+0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
+0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
+0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
+0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
+0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR), r0
+0+0dc <[^>]*> f380 8801 msr IAPSR, r0
+0+0e0 <[^>]*> f380 8802 msr EAPSR, r0
+0+0e4 <[^>]*> f380 8803 msr PSR, r0
+0+0e8 <[^>]*> f380 8805 msr IPSR, r0
+0+0ec <[^>]*> f380 8806 msr EPSR, r0
+0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
+0+0f4 <[^>]*> f380 8808 msr MSP, r0
+0+0f8 <[^>]*> f380 8809 msr PSP, r0
+0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
+0+100 <[^>]*> f380 8811 msr BASEPRI, r0
+0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
+0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
+0+10c <[^>]*> f380 8814 msr CONTROL, r0
diff --git a/gas/testsuite/gas/arm/arch7.s b/gas/testsuite/gas/arm/arch7.s
new file mode 100644
index 0000000000..9b30aa27cb
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7.s
@@ -0,0 +1,79 @@
+ # ARMV7 instructions
+ .text
+ .arch armv7r
+label1:
+ pli [r6, r8]
+ pli [r9, r7]
+ pli [r0, r1, lsl #2]
+ pli [r5]
+ pli [r5, #4095]
+ pli [r5, #-4095]
+
+ dbg #0
+ dbg #15
+ dmb
+ dmb sy
+ dsb
+ dsb sy
+ dsb un
+ dsb st
+ dsb unst
+ isb
+ isb sy
+ .thumb
+ .thumb_func
+label2:
+ pli [r6, r8]
+ pli [r9, r7]
+ pli [r0, r1, lsl #2]
+ pli [r5]
+ pli [r5, #4095]
+ pli [r5, #-255]
+ pli [pc, #4095]
+ pli [pc, #-4095]
+
+ dbg #0
+ dbg #15
+ dmb
+ dmb sy
+ dsb
+ dsb sy
+ dsb un
+ dsb st
+ dsb unst
+ isb
+ isb sy
+
+ sdiv r6, r9, r12
+ sdiv r9, r6, r3
+ udiv r9, r6, r3
+ udiv r6, r9, r12
+ .arch armv7m
+ mrs r0, apsr
+ mrs r0, iapsr
+ mrs r0, eapsr
+ mrs r0, psr
+ mrs r0, ipsr
+ mrs r0, epsr
+ mrs r0, iepsr
+ mrs r0, msp
+ mrs r0, psp
+ mrs r0, primask
+ mrs r0, basepri
+ mrs r0, basepri_max
+ mrs r0, faultmask
+ mrs r0, control
+ msr apsr, r0
+ msr iapsr, r0
+ msr eapsr, r0
+ msr psr, r0
+ msr ipsr, r0
+ msr epsr, r0
+ msr iepsr, r0
+ msr msp, r0
+ msr psp, r0
+ msr primask, r0
+ msr basepri, r0
+ msr basepri_max, r0
+ msr faultmask, r0
+ msr control, r0
diff --git a/gas/testsuite/gas/arm/arch7m-bad.d b/gas/testsuite/gas/arm/arch7m-bad.d
new file mode 100644
index 0000000000..b7a3336cb3
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7m-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid V7M instructions
+#as: -march=armv7m
+#error-output: arch7m-bad.l
+
diff --git a/gas/testsuite/gas/arm/arch7m-bad.l b/gas/testsuite/gas/arm/arch7m-bad.l
new file mode 100644
index 0000000000..c962dacdf0
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7m-bad.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:5: Error: selected processor does not support 'A' form of this instruction -- `cpsie a'
+[^:]*:6: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie i,#0x10'
+[^:]*:7: Error: selected processor does not support `cps #0x10'
+
diff --git a/gas/testsuite/gas/arm/arch7m-bad.s b/gas/testsuite/gas/arm/arch7m-bad.s
new file mode 100644
index 0000000000..78ff86495e
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7m-bad.s
@@ -0,0 +1,7 @@
+ .text
+ .thumb
+ .thumb_func
+label:
+ cpsie a
+ cpsie i, #0x10
+ cps #0x10
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index e811b14ada..0aac53a0ca 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -631,16 +631,16 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f240 5000 movw r0, #1280 ; 0x500
0[0-9a-f]+ <[^>]+> f240 0081 movw r0, #129 ; 0x81
0[0-9a-f]+ <[^>]+> f64f 70ff movw r0, #65535 ; 0xffff
-0[0-9a-f]+ <[^>]+> f3ef 8000 mrs r0, SPSR
-0[0-9a-f]+ <[^>]+> f3ff 8000 mrs r0, CPSR
-0[0-9a-f]+ <[^>]+> f3ef 8900 mrs r9, SPSR
-0[0-9a-f]+ <[^>]+> f3ff 8900 mrs r9, CPSR
-0[0-9a-f]+ <[^>]+> f380 8100 msr SPSR_c, r0
-0[0-9a-f]+ <[^>]+> f390 8100 msr CPSR_c, r0
-0[0-9a-f]+ <[^>]+> f389 8100 msr SPSR_c, r9
-0[0-9a-f]+ <[^>]+> f380 8200 msr SPSR_x, r0
-0[0-9a-f]+ <[^>]+> f380 8400 msr SPSR_s, r0
-0[0-9a-f]+ <[^>]+> f380 8800 msr SPSR_f, r0
+0[0-9a-f]+ <[^>]+> f3ef 8000 mrs r0, CPSR
+0[0-9a-f]+ <[^>]+> f3ff 8000 mrs r0, SPSR
+0[0-9a-f]+ <[^>]+> f3ef 8900 mrs r9, CPSR
+0[0-9a-f]+ <[^>]+> f3ff 8900 mrs r9, SPSR
+0[0-9a-f]+ <[^>]+> f380 8100 msr CPSR_c, r0
+0[0-9a-f]+ <[^>]+> f390 8100 msr SPSR_c, r0
+0[0-9a-f]+ <[^>]+> f389 8100 msr CPSR_c, r9
+0[0-9a-f]+ <[^>]+> f380 8200 msr CPSR_x, r0
+0[0-9a-f]+ <[^>]+> f380 8400 msr CPSR_s, r0
+0[0-9a-f]+ <[^>]+> f380 8800 msr CPSR_f, r0
0[0-9a-f]+ <[^>]+> fb00 f000 mul\.w r0, r0, r0
0[0-9a-f]+ <[^>]+> fb09 f000 mul\.w r0, r9, r0
0[0-9a-f]+ <[^>]+> fb00 f009 mul\.w r0, r0, r9
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