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authorYufeng Zhang <yufeng.zhang@arm.com>2013-11-20 11:22:40 +0000
committerYufeng Zhang <yufeng.zhang@arm.com>2013-11-20 11:31:35 +0000
commit34ded1ce7e95aa266983634d1d5c0ec8a33cc416 (patch)
tree10d27d459db1e4eb3e399b0186e2b6d8b0580a9d
parent58140105768ee0dc7cc162507ce6e92748f4f8a0 (diff)
downloadppe42-binutils-34ded1ce7e95aa266983634d1d5c0ec8a33cc416.tar.gz
ppe42-binutils-34ded1ce7e95aa266983634d1d5c0ec8a33cc416.zip
gas/testsuite/
* gas/aarch64/msr.s: Add tests. * gas/aarch64/msr.d: Update. include/opcode * aarch64.h (aarch64_pstatefields): Change element type to aarch64_sys_reg. opcodes/ * aarch64-opc.c (aarch64_pstatefields): Update.
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/aarch64/msr.d2
-rw-r--r--gas/testsuite/gas/aarch64/msr.s5
-rw-r--r--include/opcode/ChangeLog5
-rw-r--r--include/opcode/aarch64.h2
-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/aarch64-opc.c10
7 files changed, 26 insertions, 7 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2eb0336a0a..be67b6ea5f 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * gas/aarch64/msr.s: Add tests.
+ * gas/aarch64/msr.d: Update.
+
2013-11-18 Renlin Li <Renlin.Li@arm.com>
* gas/arm/attr-march-armv7ve.d: New test case for armv7ve.
diff --git a/gas/testsuite/gas/aarch64/msr.d b/gas/testsuite/gas/aarch64/msr.d
index c6c32200a4..750cae119a 100644
--- a/gas/testsuite/gas/aarch64/msr.d
+++ b/gas/testsuite/gas/aarch64/msr.d
@@ -13,3 +13,5 @@ Disassembly of section \.text:
14: d5034fff msr daifclr, #0xf
18: d51b4220 msr daif, x0
1c: d53b4220 mrs x0, daif
+ 20: d50040bf msr spsel, #0x0
+ 24: d50041bf msr spsel, #0x1
diff --git a/gas/testsuite/gas/aarch64/msr.s b/gas/testsuite/gas/aarch64/msr.s
index 9f67d98771..01018c289d 100644
--- a/gas/testsuite/gas/aarch64/msr.s
+++ b/gas/testsuite/gas/aarch64/msr.s
@@ -1,5 +1,5 @@
/*
- Copyright 2011, 2012 Free Software Foundation, Inc.
+ Copyright 2011-2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
@@ -31,3 +31,6 @@ func:
msr daif, x0
mrs x0, daif
+
+ msr spsel, #0
+ msr spsel, #1
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 02f3372991..b8a99f8982 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (aarch64_pstatefields): Change element type to
+ aarch64_sys_reg.
+
2013-11-18 Renlin Li <Renlin.Li@arm.com>
* arm.h (ARM_AEXT_V7VE): New define.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4a3a312b68..053294e335 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -611,7 +611,6 @@ struct aarch64_name_value_pair
};
extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
-extern const struct aarch64_name_value_pair aarch64_pstatefields [];
extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
extern const struct aarch64_name_value_pair aarch64_prfops [32];
@@ -623,6 +622,7 @@ typedef struct
} aarch64_sys_reg;
extern const aarch64_sys_reg aarch64_sys_regs [];
+extern const aarch64_sys_reg aarch64_pstatefields [];
extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
typedef struct
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 75532119ab..0b72d5b6fe 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64-opc.c (aarch64_pstatefields): Update.
+
2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
Revert
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index af1472a582..43133279df 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3019,12 +3019,12 @@ aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
return (reg->flags & F_DEPRECATED) != 0;
}
-const struct aarch64_name_value_pair aarch64_pstatefields [] =
+const aarch64_sys_reg aarch64_pstatefields [] =
{
- { "spsel", 0x05 },
- { "daifset", 0x1e },
- { "daifclr", 0x1f },
- { 0, CPENC(0,0,0,0,0) },
+ { "spsel", 0x05, 0 },
+ { "daifset", 0x1e, 0 },
+ { "daifclr", 0x1f, 0 },
+ { 0, CPENC(0,0,0,0,0), 0 },
};
const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
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