From 18de4ba00b600e40fd49aaaea8d0bf118b8a90e5 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Thu, 3 May 2018 16:27:01 +1000 Subject: pdbg: add 'regs' command This uses ramming to pull out most registers. There are more SPRs to left to add. Ramming remains set over all register extraction, by keeping ram_is_setup target attribut. This helps to speed things up and minimise disturbance to the host. Signed-off-by: Nicholas Piggin --- libpdbg/p9chip.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'libpdbg/p9chip.c') diff --git a/libpdbg/p9chip.c b/libpdbg/p9chip.c index 7182ae1..f6fd849 100644 --- a/libpdbg/p9chip.c +++ b/libpdbg/p9chip.c @@ -241,6 +241,9 @@ static int p9_ram_setup(struct thread *thread) struct core *chip = target_to_core(thread->target.parent); uint64_t value; + if (thread->ram_is_setup) + return 1; + if (pdbg_expert_mode) goto expert; @@ -299,6 +302,8 @@ expert: thread->status = p9_get_thread_status(thread); + thread->ram_is_setup = true; + return 0; out_fail: @@ -313,6 +318,9 @@ static int __p9_ram_instruction(struct thread *thread, uint64_t opcode, uint64_t uint64_t predecode, value; int rc; + if (!thread->ram_is_setup) + return 1; + switch(opcode & OPCODE_MASK) { case MTNIA_OPCODE: predecode = 8; @@ -330,6 +338,17 @@ static int __p9_ram_instruction(struct thread *thread, uint64_t opcode, uint64_t predecode = 8; break; + case MFSPR_OPCODE: + switch(MFSPR_SPR(opcode)) { + case 1: /* XER */ + predecode = 4; + break; + default: + predecode = 0; + break; + } + break; + default: predecode = 0; } @@ -392,6 +411,9 @@ static int p9_ram_instruction(struct thread *thread, uint64_t opcode, uint64_t * static int p9_ram_destroy(struct thread *thread) { + if (!thread->ram_is_setup) + return 1; + /* Disable ram mode */ CHECK_ERR(thread_write(thread, P9_RAM_MODEREG, 0)); @@ -402,6 +424,8 @@ static int p9_ram_destroy(struct thread *thread) ram_nonexpert_cleanup(thread); + thread->ram_is_setup = false; + return 0; } -- cgit v1.2.1