Rename chiplet to core

A core is a specific subset of chiplets so rename the existing usage of chiplet
to core so that we may add other types of chiplets to the system. No functional
change.

Signed-off-by: Alistair Popple <alistair@popple.id.au>

6 files changed, 51 insertions, 51 deletions

diff --git a/README.md b/README.md
index d0d621f..51b5f09 100644
--- a/README.md
+++ b/README.md
@@ -102,84 +102,84 @@ $ ./pdbg -a probe
         CFAM hMFSI Port
             p1: POWER FSI2PIB
                 POWER9 ADU
-                c16: POWER9 Chiplet
+                c16: POWER9 Core
                     t0: POWER9 Thread
                     t1: POWER9 Thread
                     t2: POWER9 Thread
                     t3: POWER9 Thread
-                c17: POWER9 Chiplet
+                c17: POWER9 Core
                     t0: POWER9 Thread
                     t1: POWER9 Thread
                     t2: POWER9 Thread
                     t3: POWER9 Thread
-                c18: POWER9 Chiplet
+                c18: POWER9 Core
                     t0: POWER9 Thread
                     t1: POWER9 Thread
                     t2: POWER9 Thread
                     t3: POWER9 Thread
-                c19: POWER9 Chiplet
+                c19: POWER9 Core
                     t0: POWER9 Thread
                     t1: POWER9 Thread
                     t2: POWER9 Thread
                     t3: POWER9 Thread
-                c20: POWER9 Chiplet
+                c20: POWER9 Core
                     t0: POWER9 Thread
                     t1: POWER9 Thread
                     t2: POWER9 Thread
                     t3: POWER9 Thread
-                c21: POWER9 Chiplet
+                c21: POWER9 Core
                     t0: POWER9 Thread
                     t1: POWER9 Thread
                     t2: POWER9 Thread
                     t3: POWER9 Thread
-                c22: POWER9 Chiplet
+                c22: POWER9 Core
                     t0: POWER9 Thread
                     t1: POWER9 Thread
                     t2: POWER9 Thread
                     t3: POWER9 Thread
-                c23: POWER9 Chiplet
+                c23: POWER9 Core
                     t0: POWER9 Thread
                     t1: POWER9 Thread
                     t2: POWER9 Thread
                     t3: POWER9 Thread
         p0: POWER FSI2PIB
             POWER9 ADU
-            c5: POWER9 Chiplet
+            c5: POWER9 Core
                 t0: POWER9 Thread
                 t1: POWER9 Thread
                 t2: POWER9 Thread
                 t3: POWER9 Thread
-            c7: POWER9 Chiplet
+            c7: POWER9 Core
                 t0: POWER9 Thread
                 t1: POWER9 Thread
                 t2: POWER9 Thread
                 t3: POWER9 Thread
-            c14: POWER9 Chiplet
+            c14: POWER9 Core
                 t0: POWER9 Thread
                 t1: POWER9 Thread
                 t2: POWER9 Thread
                 t3: POWER9 Thread
-            c15: POWER9 Chiplet
+            c15: POWER9 Core
                 t0: POWER9 Thread
                 t1: POWER9 Thread
                 t2: POWER9 Thread
                 t3: POWER9 Thread
-            c19: POWER9 Chiplet
+            c19: POWER9 Core
                 t0: POWER9 Thread
                 t1: POWER9 Thread
                 t2: POWER9 Thread
                 t3: POWER9 Thread
-            c20: POWER9 Chiplet
+            c20: POWER9 Core
                 t0: POWER9 Thread
                 t1: POWER9 Thread
                 t2: POWER9 Thread
                 t3: POWER9 Thread
-            c21: POWER9 Chiplet
+            c21: POWER9 Core
                 t0: POWER9 Thread
                 t1: POWER9 Thread
                 t2: POWER9 Thread
                 t3: POWER9 Thread
-            c22: POWER9 Chiplet
+            c22: POWER9 Core
                 t0: POWER9 Thread
                 t1: POWER9 Thread
                 t2: POWER9 Thread
@@ -189,7 +189,7 @@ Note that only selected targets will be shown above. If none are shown
 try adding '-a' to select all targets
 ```
 
-Chiplet-IDs are core/chip numbers which should be passed as arguments to `-c`
+Core-IDs are core/chip numbers which should be passed as arguments to `-c`
 when performing operations such as getgpr that operate on particular cores.
 Processor-IDs should be passed as arguments to `-p` to operate on different
 processor chips. Specifying no targets is an error and will result in the
diff --git a/libpdbg/htm.c b/libpdbg/htm.c
index 6377699..ee6cf1e 100644
--- a/libpdbg/htm.c
+++ b/libpdbg/htm.c
@@ -421,7 +421,7 @@ static int do_setup(struct htm *htm)
 					0xFFFF000000)))
 		return -1;
 
-	/* Stop on chiplet xstop */
+	/* Stop on core xstop */
 	if (HTM_ERR(pib_write(&htm->target, HTM_TRIGGER_CONTROL, HTM_CTRL_XSTOP_STOP)))
 		return -1;;
 
diff --git a/libpdbg/p8chip.c b/libpdbg/p8chip.c
index 8944a72..3d3795f 100644
--- a/libpdbg/p8chip.c
+++ b/libpdbg/p8chip.c
@@ -72,7 +72,7 @@
 /* How long (in us) to wait for a special wakeup to complete */
 #define SPECIAL_WKUP_TIMEOUT		10
 
-static int assert_special_wakeup(struct chiplet *chip)
+static int assert_special_wakeup(struct core *chip)
 {
 	int i = 0;
 	uint64_t gp0;
@@ -97,7 +97,7 @@ static int assert_special_wakeup(struct chiplet *chip)
 
 #if 0
 /* TODO: Work out when to do this. */
-static int deassert_special_wakeup(struct chiplet *chip)
+static int deassert_special_wakeup(struct core *chip)
 {
 	/* Assert special wakeup to prevent low power states */
 	CHECK_ERR(pib_write(&chip->target, PMSPCWKUPFSP_REG, 0));
@@ -163,7 +163,7 @@ static int p8_thread_stop(struct thread *thread)
 {
 	int i = 0;
 	uint64_t val;
-	struct chiplet *chip = target_to_chiplet(thread->target.dn->parent->target);
+	struct core *chip = target_to_core(thread->target.dn->parent->target);
 
 	do {
 		/* Quiese active thread */
@@ -201,7 +201,7 @@ static int p8_thread_stop(struct thread *thread)
 static int p8_thread_start(struct thread *thread)
 {
 	uint64_t val;
-	struct chiplet *chip = target_to_chiplet(thread->target.dn->parent->target);
+	struct core *chip = target_to_core(thread->target.dn->parent->target);
 
 	/* Activate thread */
 	CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_START));
@@ -218,7 +218,7 @@ static int p8_thread_start(struct thread *thread)
 static int p8_ram_setup(struct thread *thread)
 {
 	struct dt_node *dn;
-	struct chiplet *chip = target_to_chiplet(thread->target.dn->parent->target);
+	struct core *chip = target_to_core(thread->target.dn->parent->target);
 	uint64_t ram_mode, val;
 
 	/* We can only ram a thread if all the threads on the core/chip are
@@ -250,7 +250,7 @@ static int p8_ram_setup(struct thread *thread)
 
 static int p8_ram_instruction(struct thread *thread, uint64_t opcode, uint64_t *scratch)
 {
-	struct chiplet *chip = target_to_chiplet(thread->target.dn->parent->target);
+	struct core *chip = target_to_core(thread->target.dn->parent->target);
 	uint64_t val;
 
 	CHECK_ERR(pib_write(&chip->target, SCR0_REG, *scratch));
@@ -282,7 +282,7 @@ static int p8_ram_instruction(struct thread *thread, uint64_t opcode, uint64_t *
 
 static int p8_ram_destroy(struct thread *thread)
 {
-	struct chiplet *chip = target_to_chiplet(thread->target.dn->parent->target);
+	struct core *chip = target_to_core(thread->target.dn->parent->target);
 	uint64_t ram_mode;
 
 	/* Disable RAM mode */
@@ -294,7 +294,7 @@ static int p8_ram_destroy(struct thread *thread)
 }
 
 /*
- * Initialise all viable threads for ramming on the given chiplet.
+ * Initialise all viable threads for ramming on the given core.
  */
 static int p8_thread_probe(struct pdbg_target *target)
 {
@@ -322,10 +322,10 @@ struct thread p8_thread = {
 };
 DECLARE_HW_UNIT(p8_thread);
 
-static int p8_chiplet_probe(struct pdbg_target *target)
+static int p8_core_probe(struct pdbg_target *target)
 {
 	uint64_t value;
-	struct chiplet *chiplet = target_to_chiplet(target);
+	struct core *core = target_to_core(target);
 
 	/* Work out if this chip is actually present */
 	if (pib_read(target, SCOM_EX_GP3, &value)) {
@@ -336,16 +336,16 @@ static int p8_chiplet_probe(struct pdbg_target *target)
 	if (!GETFIELD(PPC_BIT(0), value))
 		return -1;
 
-	assert_special_wakeup(chiplet);
+	assert_special_wakeup(core);
 	return 0;
 }
 
-struct chiplet p8_chiplet = {
+struct core p8_core = {
 	.target = {
-		.name = "POWER8 Chiplet",
+		.name = "POWER8 Core",
 		.compatible = "ibm,power8-core",
-		.class = "chiplet",
-		.probe = p8_chiplet_probe,
+		.class = "core",
+		.probe = p8_core_probe,
 	},
 };
-DECLARE_HW_UNIT(p8_chiplet);
+DECLARE_HW_UNIT(p8_core);
diff --git a/libpdbg/p9chip.c b/libpdbg/p9chip.c
index 037f03e..720c166 100644
--- a/libpdbg/p9chip.c
+++ b/libpdbg/p9chip.c
@@ -126,7 +126,7 @@ static int p9_thread_sreset(struct thread *thread)
 static int p9_ram_setup(struct thread *thread)
 {
 	struct dt_node *dn;
-	struct chiplet *chip = target_to_chiplet(thread->target.dn->parent->target);
+	struct core *chip = target_to_core(thread->target.dn->parent->target);
 
 	/* We can only ram a thread if all the threads on the core/chip are
 	 * quiesced */
@@ -215,7 +215,7 @@ struct thread p9_thread = {
 };
 DECLARE_HW_UNIT(p9_thread);
 
-static int p9_chiplet_probe(struct pdbg_target *target)
+static int p9_core_probe(struct pdbg_target *target)
 {
 	int i = 0;
 	uint64_t value;
@@ -241,12 +241,12 @@ static int p9_chiplet_probe(struct pdbg_target *target)
 	return 0;
 }
 
-struct chiplet p9_chiplet = {
+struct core p9_core = {
 	.target = {
-		.name = "POWER9 Chiplet",
+		.name = "POWER9 Core",
 		.compatible = "ibm,power9-core",
-		.class = "chiplet",
-		.probe = p9_chiplet_probe,
+		.class = "core",
+		.probe = p9_core_probe,
 	},
 };
-DECLARE_HW_UNIT(p9_chiplet);
+DECLARE_HW_UNIT(p9_core);
diff --git a/libpdbg/target.h b/libpdbg/target.h
index c59081e..857d23c 100644
--- a/libpdbg/target.h
+++ b/libpdbg/target.h
@@ -112,10 +112,10 @@ struct fsi {
 };
 #define target_to_fsi(x) container_of(x, struct fsi, target)
 
-struct chiplet {
+struct core {
 	struct pdbg_target target;
 };
-#define target_to_chiplet(x) container_of(x, struct chiplet, target)
+#define target_to_core(x) container_of(x, struct core, target)
 
 struct thread {
 	struct pdbg_target target;
diff --git a/src/main.c b/src/main.c
index c823819..9eab915 100644
--- a/src/main.c
+++ b/src/main.c
@@ -77,7 +77,7 @@ static void print_usage(char *pname)
 	printf("Usage: %s [options] command ...\n\n", pname);
 	printf(" Options:\n");
 	printf("\t-p, --processor=processor-id\n");
-	printf("\t-c, --chip=chiplet-id\n");
+	printf("\t-c, --chip=core-id\n");
 	printf("\t-t, --thread=thread\n");
 	printf("\t-a, --all\n");
 	printf("\t\tRun command on all possible processors/chips/threads (default)\n");
@@ -450,13 +450,13 @@ static int print_thread_status(struct pdbg_target *target, uint32_t index, uint6
 	return 1;
 }
 
-static int print_chiplet_thread_status(struct pdbg_target *chiplet_target, uint32_t index, uint64_t *unused, uint64_t *unused1)
+static int print_core_thread_status(struct pdbg_target *core_target, uint32_t index, uint64_t *unused, uint64_t *unused1)
 {
 	uint64_t status = -1UL;
 	int i, rc;
 
 	printf("c%02d:", index);
-	rc = for_each_child_target("thread", chiplet_target, print_thread_status, &status, NULL);
+	rc = for_each_child_target("thread", core_target, print_thread_status, &status, NULL);
 	for (i = 0; i < 8; i++)
 		switch ((status >> (i * 4)) & 0xf) {
 		case THREAD_STATUS_ACTIVE:
@@ -498,7 +498,7 @@ static int print_chiplet_thread_status(struct pdbg_target *chiplet_target, uint3
 static int print_proc_thread_status(struct pdbg_target *pib_target, uint32_t index, uint64_t *unused, uint64_t *unused1)
 {
 	printf("\np%01dt: 0 1 2 3 4 5 6 7\n", index);
-	return for_each_child_target("chiplet", pib_target, print_chiplet_thread_status, NULL, NULL);
+	return for_each_child_target("core", pib_target, print_core_thread_status, NULL, NULL);
 };
 
 #define REG_MEM -3
@@ -510,7 +510,7 @@ static void print_proc_reg(struct pdbg_target *target, uint64_t reg, uint64_t va
 	int proc_index, chip_index, thread_index;
 
 	thread_index = pdbg_target_index(target);
-	chip_index = pdbg_parent_index(target, "chiplet");
+	chip_index = pdbg_parent_index(target, "core");
 	proc_index = pdbg_parent_index(target, "pib");
 	printf("p%d:c%d:t%d:", proc_index, chip_index, thread_index);
 
@@ -524,7 +524,7 @@ static void print_proc_reg(struct pdbg_target *target, uint64_t reg, uint64_t va
 		printf("gpr%02" PRIu64 ": ", reg);
 
 	if (rc == 1) {
-		printf("Check threadstatus - not all threads on this chiplet are quiesced\n");
+		printf("Check threadstatus - not all threads on this core are quiesced\n");
 	} else if (rc == 2)
 		printf("Thread in incorrect state\n");
 	else
@@ -904,7 +904,7 @@ static int target_select(void)
 
 		if (processorsel[proc_index]) {
 			pdbg_enable_target(pib);
-			pdbg_for_each_target("chiplet", pib, chip) {
+			pdbg_for_each_target("core", pib, chip) {
 				int chip_index = pdbg_target_index(chip);
 				if (chipsel[proc_index][chip_index]) {
 					pdbg_enable_target(chip);
@@ -951,7 +951,7 @@ void print_target(struct pdbg_target *target, int level)
 			char c = 0;
 			if (!strcmp(pdbg_target_class_name(target), "pib"))
 				c = 'p';
-			else if (!strcmp(pdbg_target_class_name(target), "chiplet"))
+			else if (!strcmp(pdbg_target_class_name(target), "core"))
 				c = 'c';
 			else if (!strcmp(pdbg_target_class_name(target), "thread"))
 				c = 't';