pdbg/libpdbg, branch 04-16-2019OpenPOWER processor debug utility sourceshttps://git.raptorcs.com/git/pdbg/atom?h=04-16-20192019-04-19T12:14:35+00:00Clarify CFAM failure reason2019-04-19T12:14:35+00:00Raptor Engineering Development Teamsupport@raptorengineering.com2018-01-18T04:06:05+00:00urn:sha1:a1f574fe60cf3e299f22bc39f4de40bc7ea0d87cAdd Blackbird support2019-04-19T12:14:35+00:00Raptor Engineering Development Teamsupport@raptorengineering.com2019-04-19T06:57:15+00:00urn:sha1:8ef16543ce4af45f55d6235dc9e69b700658fe72Add Talos support2019-04-19T12:14:35+00:00Raptor Engineering Development Teamsupport@raptorengineering.com2018-01-17T23:40:55+00:00urn:sha1:68ac85897b4918e5fd5383f450fdfcdffc6ff380libpdbg/p8chip.c: Emulate sreset using ramming for active threads2019-03-27T06:02:19+00:00Nicholas Pigginnpiggin@gmail.com2019-03-12T01:49:20+00:00urn:sha1:51ca1a18d56948aeaae8599e6629aebb0b501519
Based on patch from Alistair, some fixes and changes:
- account HILE bit, set/clear MSR_LE
- clear MSR_PR
- don't use raw ramming (clearer this way, not perf critical)
At the moment, must manually stop all threads in the core, and manually
restart them. Can change behaviour depending on what exactly we want
(e.g., sreset all threads may be good for debugging).
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Tested-by: Stewart Smith <stewart@linux.ibm.com>
libpdbg/p8chip.c: ram state setup sequence match workbook2019-03-27T05:57:16+00:00Nicholas Pigginnpiggin@gmail.com2019-03-12T01:49:19+00:00urn:sha1:dccba372193c95469de633144c1f3ba2ba8ac223
This makes a few changes to stop and ram procedure.
First of all, the existing thread_stop procedure is also setting up some
of the ram state. Change that to just do the stop sequence from the
workbook, and move the ram stuff into ram setup and destroy.
The workbook calls for inactive threads being rammed to set a thread
active state before ram mode is exited, in order for GPRs modified by
ramming to avoid getting lost. Currently the code does that in the
stop sequence before ram mode is activated.
The code also currently deasserts the thread active bit after exiting
ram mode, which is not part of the workbook, so this is no longer done.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
libpdbg: use MTMSRD opcode rather than MTMSR2019-03-27T05:57:11+00:00Nicholas Pigginnpiggin@gmail.com2019-03-12T01:49:18+00:00urn:sha1:5a5334451cd22a40bc21b41789fcd74e04eb28ba
XXX: have to ensure this still does the right thing on P9
libpdbg/p8chip.c: release special wakeups for P82019-03-27T05:57:07+00:00Nicholas Pigginnpiggin@gmail.com2019-03-12T01:49:17+00:00urn:sha1:8dfaa632b7015a5267175e2f806d4fd28d3ecf89
This copies the special wakeup release logic from p9chip.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Revert incorrect version of "libpdbg/p8chip.c: Emulate sreset using ramming..."2019-03-27T05:56:03+00:00Alistair Popplealistair@popple.id.au2019-03-27T05:56:03+00:00urn:sha1:f79c0af079430fcf326c19f97d48e3e8c9c7e28c
This reverts commit 3ce2bc04c70bf6f961a62a380f7b4459445ed2da.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Revert incorrect version of "libpdbg/p8chip.c: ram state setup sequence ..."2019-03-27T05:55:28+00:00Alistair Popplealistair@popple.id.au2019-03-27T05:55:28+00:00urn:sha1:5fbfe98974854433738befd735337cd99188a3f7
This reverts commit eb1d866e30a1f8488fb794776bb5a1e0bc42d2e5.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Revert incorrect version of "libpdbg: use MTMSRD opcode rather than MTMSR"2019-03-27T05:54:30+00:00Alistair Popplealistair@popple.id.au2019-03-27T05:54:30+00:00urn:sha1:31961eae1f0a3106c840f3b79058041cce68b311
This reverts commit f795d2904010c0b2e2ad8d8163dffc906ce8cef7.
Signed-off-by: Alistair Popple <alistair@popple.id.au>