From 7cd36def20571c0331bc2b559c78369509b975ba Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Thu, 14 Aug 2014 11:43:38 -0500 Subject: Initial commit --- CENTAUR.xml | 140 +++ DDR3_DRAM_ABSTRACT.xml | 31 + DIMM_SPD.xml | 25 + LANCER_B0.xml | 57 ++ MOD_SEEPROM_512.xml | 37 + PCA9538.xml | 45 + PCIE_X16_ABSTRACT.xml | 42 + PCIE_X8_ABSTRACT.xml | 42 + PEX8718_PALMETTO.xml | 50 ++ PGOOD_LAYERBRIDGE.xml | 19 + README | 3 + TULETA_FSP2.xml | 2285 ++++++++++++++++++++++++++++++++++++++++++++++++ TUSB7340.xml | 53 ++ VENICE.xml | 323 +++++++ VRD_NOI2C.xml | 30 + ddr3_dimm_generic.xml | 46 + mru-type-mapping.xml | 266 ++++++ pcie_x16_card.xml | 43 + pcie_x8_card.xml | 43 + turismo_scm.xml | 254 ++++++ 20 files changed, 3834 insertions(+) create mode 100644 CENTAUR.xml create mode 100644 DDR3_DRAM_ABSTRACT.xml create mode 100644 DIMM_SPD.xml create mode 100644 LANCER_B0.xml create mode 100644 MOD_SEEPROM_512.xml create mode 100644 PCA9538.xml create mode 100644 PCIE_X16_ABSTRACT.xml create mode 100644 PCIE_X8_ABSTRACT.xml create mode 100644 PEX8718_PALMETTO.xml create mode 100644 PGOOD_LAYERBRIDGE.xml create mode 100644 README create mode 100644 TULETA_FSP2.xml create mode 100644 TUSB7340.xml create mode 100644 VENICE.xml create mode 100644 VRD_NOI2C.xml create mode 100644 ddr3_dimm_generic.xml create mode 100644 mru-type-mapping.xml create mode 100644 pcie_x16_card.xml create mode 100644 pcie_x8_card.xml create mode 100644 turismo_scm.xml diff --git a/CENTAUR.xml b/CENTAUR.xml new file mode 100644 index 0000000..4a73df2 --- /dev/null +++ b/CENTAUR.xml @@ -0,0 +1,140 @@ + + + + + + CENTAUR + chip + DD1 + membuf + yes + + mba01mba0 + port0 + port1 + port2 + port3 + + mba23mba1 + port0 + port1 + port2 + port3 + + + + L4L40 + + + + + I2CMASTER_DIMMS0 + 6 + 0 + SDA_M0 + I2C Master for DIMMs + + + I2CSPR_DIMMS0 + 6 + 1 + SDA_M0 + I2C SPR for DIMMs + + + + FSI_SLAVE00 + FSI_SLAVE11 + + + GPIO_PORT070 + + + DDR3_CH0_SLOT000mba01 + DDR3_CH0_SLOT101mba01 + DDR3_CH1_SLOT000mba23 + DDR3_CH1_SLOT101mba23 + DDR3_CH2_SLOT010mba01 + DDR3_CH2_SLOT111mba01 + DDR3_CH3_SLOT010mba23 + DDR3_CH3_SLOT111mba23 + + + DMI + + + + VMEM + VMEM + 1.35 + 10 + 12 + + + VPP + VPP + 2.5 + 3 + 4 + + + VCACHE + VCACHE + 1.035 + 18 + 21 + + + VCORE + VCORE + 0.9 + 18 + 21 + + + AVDD + AVDD + 0.9 + 18 + 21 + + + + + + + + + + shift + 3 + + + fsi2pib + 4 + + + scratchpad + 5 + + + i2cm + 6 + + + gpio + 7 + + + fsi2pib2 + 8 + + + + + + + diff --git a/DDR3_DRAM_ABSTRACT.xml b/DDR3_DRAM_ABSTRACT.xml new file mode 100644 index 0000000..e911169 --- /dev/null +++ b/DDR3_DRAM_ABSTRACT.xml @@ -0,0 +1,31 @@ + + + + + + DDR3_DRAM_ABSTRACT + chip + dram + + + + DDR_INTERFACE + ddr_addr + + + + + VDD + VDD + 1.35 + lookup + lookup + + + + + + diff --git a/DIMM_SPD.xml b/DIMM_SPD.xml new file mode 100644 index 0000000..55c552d --- /dev/null +++ b/DIMM_SPD.xml @@ -0,0 +1,25 @@ + + + + + + DIMM_SPD + chip + seeprom + DIMM_VPD + 24c32 + + + + SVPD + SDA + + + + + + + diff --git a/LANCER_B0.xml b/LANCER_B0.xml new file mode 100644 index 0000000..b244124 --- /dev/null +++ b/LANCER_B0.xml @@ -0,0 +1,57 @@ + + + + + + LANCER_B0 + chip + ethernet + x0pxxxx + Emulex Lancer B0 - 4ports + + + PCIE_X88 + + + ETH00 + ETH11 + ETH22 + ETH33 + + + + 0.9V + VCORE + 0.9 + 0.01 + 0.02 + + + 1.2V + VLOGIC + 1.2 + 0.01 + 0.02 + + + 1.8V + VIO + 1.8 + 0.01 + 0.02 + + + 3.3V + VCC + 3.3 + 0.01 + 0.02 + + + + + + diff --git a/MOD_SEEPROM_512.xml b/MOD_SEEPROM_512.xml new file mode 100644 index 0000000..38e1fce --- /dev/null +++ b/MOD_SEEPROM_512.xml @@ -0,0 +1,37 @@ + + + + + + MOD_SEEPROM_512 + chip + seeprom + 77P8905 + MODULE_VPD + 24c512 + + + + I2C + SDA0 + + + + + VCC + VCC + 1.8 + 0.01 + 0.02 + + + + + + + + + diff --git a/PCA9538.xml b/PCA9538.xml new file mode 100644 index 0000000..23a7745 --- /dev/null +++ b/PCA9538.xml @@ -0,0 +1,45 @@ + + + + + + PCA9538 + chip + i2c-expander + x0pxxxx + I2C Expander + + + + I2C + SDA + + + + + IO00 + IO11 + IO22 + IO33 + IO44 + IO55 + IO66 + IO77 + INTINT + + + + 3.3V + VCC + 3.3 + 0.01 + 0.02 + + + + + + diff --git a/PCIE_X16_ABSTRACT.xml b/PCIE_X16_ABSTRACT.xml new file mode 100644 index 0000000..694b147 --- /dev/null +++ b/PCIE_X16_ABSTRACT.xml @@ -0,0 +1,42 @@ + + + + + + PCIE_X16_ABSTRACT + blackbox + pcie-blackbox + + + + I2C + SDA + + + + + PCIE_X1616 + + + + 3.3V + VCC + 3.3 + 0.01 + 0.02 + + + 12V + 12V + 12 + 0.01 + 0.02 + + + + + + diff --git a/PCIE_X8_ABSTRACT.xml b/PCIE_X8_ABSTRACT.xml new file mode 100644 index 0000000..559e339 --- /dev/null +++ b/PCIE_X8_ABSTRACT.xml @@ -0,0 +1,42 @@ + + + + + + PCIE_X8_ABSTRACT + blackbox + pcie-blackbox + + + + I2C + SDA + + + + + PCIE_X88 + + + + 3.3V + VCC + 3.3 + 0.01 + 0.02 + + + 12V + 12V + 12 + 0.01 + 0.02 + + + + + + diff --git a/PEX8718_PALMETTO.xml b/PEX8718_PALMETTO.xml new file mode 100644 index 0000000..6f8d82f --- /dev/null +++ b/PEX8718_PALMETTO.xml @@ -0,0 +1,50 @@ + + + + + + PEX8718_PALMETTO + chip + pcie-switch + x0pxxxx + PLX 18 lane PCIe Gen3 Switch + + + I2CSDA + + + INBOUND_X8OUT800 + + + RESETRESET + + + S0_X2IN200 + S1_X2IN211 + S2_X1IN122 + S3_X1IN133 + + + + 0.9V + VLOGIC + 0.9 + 0.01 + 0.02 + + + 1.8V + VCC + 1.8 + + 0.01 + 0.02 + + + + + + diff --git a/PGOOD_LAYERBRIDGE.xml b/PGOOD_LAYERBRIDGE.xml new file mode 100644 index 0000000..e81fe3c --- /dev/null +++ b/PGOOD_LAYERBRIDGE.xml @@ -0,0 +1,19 @@ + + + + + + PGOOD_LAYERBRIDGE + layer-bridge + + + GPIO + + + PGOOD + + + + \ No newline at end of file diff --git a/README b/README new file mode 100644 index 0000000..e496c49 --- /dev/null +++ b/README @@ -0,0 +1,3 @@ + +XML files common across systems. These are used as input +in to the MRW generation tools. \ No newline at end of file diff --git a/TULETA_FSP2.xml b/TULETA_FSP2.xml new file mode 100644 index 0000000..f484067 --- /dev/null +++ b/TULETA_FSP2.xml @@ -0,0 +1,2285 @@ + + + + + + +TULETA_FSP2 +chip +fsp + + + + eth0_rxd_0_R03R030 + eth1_rxd_0_N02N020 + eth_mdc_P08P080 + + + fsim0_clk_AH03AH03 + fsim1_clk_AH02AH02 + FSIM_CLK[2]AG19 + FSIM_CLK[3]AF19 + + + fsis0_clk_AG22AG22 + fsis1_clk_AF21AF21 + + + fsp_boot_fail_oi_n_K02K02 + fsp_spinor_rst_n_M07M07 + fsp2_dpss_din_L07L07 + fsp2_dpss_cclk_L08L08 + fsp2_chip_rst_n_B28B28 + tod_battery_test_J22J22 + ps_ffs_sync_n_J26J26 + apps_reset_n_J25J25 + dpss_prog_n_K21K21 + dpss_sys_rst_n_L23L23 + apss_boot_mode_M22M22 + dpss_unlatch_n_L26L26 + ps_i2c_rst_n_M24M24 + cpu_spi_nor_rst_n_W27W27 + buddy_rst_out_n_W26W26 + fsp2_i2c_lightpath_reset_n_W24W24 + cm3_si5338_oe_n_V24V24 + cm2_si5335b_oeb2_n_V23V23 + cm2_si5335b_oeb3_n_U22U22 + system_pg_pex8732_AF28AF28 + system_pg_pex8748_AE27AE27 + system_pg_dcm_AE26AE26 + cpu0_cfam_reset_n_AC20AC20 + pex_i2c_smbus_cfg_en_n_AD18AD18 + fsp2_pex32_perst_n_AD19AD19 + fsp2_pex48_perst_n_AC18AC18 + + + irq0_eth0_n_K03K03 + irq1_eth1_n_K05K05 + irq2_tpm_n_H01H01 + irq3_psi_n_J01J01 + fsp_pp_state_L05L05 + irq5_rtc_n_M06M06 + irq4_ps_int_n_L06L06 + ps1_presence_K06K06 + ps2_presence_M09M09 + ps3_presence_M10M10 + ps4_presence_K09K09 + dpss_done_L10L10 + DASD_pca9554_int_n_J23J23 + tod_battery_low_n_H28H28 + dpss_init_n_L22L22 + dpss_i2c_int_n_M23M23 + cpu_pp_state_Y26Y26 + dpss_pgood_cpu_T21T21 + + + i2c0_scl_H02H02 + i2c1_scl_H04H04 + i2c2_scl_J06J06 + i2c3_scl_H06H06 + i2c4_scl_K08K08 + iou_i2c0_scl_V28V28 + I2C_SCL[10]Y28 + I2C_SCL[1]AA26 + I2C_SCL[2]W23 + I2C_SCL[3]V21 + I2C_SCL[4]AA28 + I2C_SCL[5]AB26 + I2C_SCL[6]Y23 + I2C_SCL[7]W21 + I2C_SCL[8]AD28 + I2C_SCL[9]AD27 + I2CMD2_SCLAC25 + I2CMD1_SCLAA24 + + + led_yellow_planar_E28E28 + led_green_network_reset_D27D27 + led_pcie_slot_c2_yel_E26E26 + led_yellow_tod_battery_F28F28 + led_yellow_dcm1_F27F27 + led_yellow_dcm2_F26F26 + led_blue_id_F25F25 + led_yellow_sysinfo_F24F24 + led_pcie_slot_c3_yel_H26H26 + + + oppanel_presence_n_C28C28 + storage_backplane_presence_n_C27C27 + native_iocard_presence_n_D26D26 + fengjia_c3_presence_n_G27G27 + fengjia_c5_presence_n_G26G26 + fengjia_c6_presence_n_H25H25 + fengjia_c7_presence_n_G24G24 + network_switch_reset_n_H23H23 + + + psi0_cp_fsp_clk_p_AC04AC040 + psi1_cp_fsp_clk_p_AB05AB051 + psi2_cp_fsp_clk_p_Y07Y072 + psi3_cp_fsp_clk_p_W08W083 + + + U750_RX[0]AA22 + U750_DCD[1]AF26 + U750_RX[1]AC23 + + + SC_CLK[0]J28 + SC_CLK[1]K26 + + + usb0_clk_A09A09 + usb1_clk_A06A06 + + + 1.2V1.2V + 1.2 + 0.01 + 0.02 + + 1.0V1.0V + 1.0 + 0.01 + 0.02 + + 1.35V1.35V + 1.35 + 0.01 + 0.02 + + 1.8V1.8V + 1.8 + 0.01 + 0.02 + + 3.3V3.3V + 3.3 + 0.01 + 0.02 + + + + + + -1 + fsp_boot_fail_oi_n_K02 + gpio-master-unit + + + 0 + 00 + output + open-drain + 0 + 0 + + + -1 + irq0_eth0_n_K03 + gpio-slave-unit + + + 0 + 01 + input + push-pull + 0 + + + + -1 + irq1_eth1_n_K05 + gpio-slave-unit + + + 0 + 02 + input + push-pull + 0 + + + + -1 + irq2_tpm_n_H01 + gpio-slave-unit + + + 0 + 03 + input + push-pull + 0 + + + + -1 + irq3_psi_n_J01 + gpio-slave-unit + + + 0 + 04 + input + push-pull + 0 + + + + -1 + fsp_pp_state_L05 + gpio-slave-unit + + + 0 + 05 + input + open-drain + 0 + + + + -1 + irq5_rtc_n_M06 + gpio-slave-unit + + + 0 + 06 + input + push-pull + 0 + + + + -1 + fsp_spinor_rst_n_M07 + gpio-master-unit + + + 0 + 07 + output + open-drain + 0 + 0 + + + -1 + fsp2_dpss_din_L07 + gpio-master-unit + + + 0 + 08 + output + push-pull + 0 + 0 + + + -1 + fsp2_dpss_cclk_L08 + gpio-master-unit + + + 0 + 09 + output + push-pull + 0 + 0 + + + -1 + irq4_ps_int_n_L06 + gpio-slave-unit + + + 0 + 10 + input + push-pull + 0 + + + + -1 + ps1_presence_K06 + gpio-slave-unit + + + 0 + 11 + input + open-drain + 0 + + + + -1 + ps2_presence_M09 + gpio-slave-unit + + + 0 + 12 + input + open-drain + 0 + + + + -1 + ps3_presence_M10 + gpio-slave-unit + + + 0 + 13 + input + open-drain + 0 + + + + -1 + ps4_presence_K09 + gpio-slave-unit + + + 0 + 14 + input + open-drain + 0 + + + + -1 + dpss_done_L10 + gpio-slave-unit + + + 0 + 15 + input + push-pull + 0 + 1 + + + -1 + i2c0_scl_H02 + i2c-master-unit + + + 0 + 0 + output + open-drain + 0 + + + + -1 + i2c0_sda_H03 + i2c-master-unit + + + 0 + 0 + bidi + open-drain + 0 + + + + -1 + i2c1_scl_H04 + i2c-master-unit + + + 1 + 0 + output + open-drain + 0 + + + + -1 + i2c1_sda_H05 + i2c-master-unit + + + 1 + 0 + output + open-drain + 0 + + + + -1 + i2c2_scl_J06 + i2c-master-unit + + + 2 + 0 + bidi + open-drain + 0 + + + + -1 + i2c2_sda_J07 + i2c-master-unit + + + 2 + 0 + output + open-drain + 0 + + + + -1 + i2c3_scl_H06 + i2c-master-unit + + + 3 + 0 + output + open-drain + 0 + + + + -1 + i2c3_sda_G06 + i2c-master-unit + + + 3 + 0 + bidi + open-drain + 0 + + + + -1 + i2c4_scl_K08 + i2c-master-unit + + + 4 + 0 + output + open-drain + 0 + + + + -1 + i2c4_sda_J09 + i2c-master-unit + + + 4 + 0 + bidi + open-drain + 0 + + + + -1 + ## Ethernet Ref Clock input from PHY_NONIOU + + + + 0 + 0 + + + 0 + + + + -1 + ## Ethernet PHY reset outputs tbd_NONIOU + + + + 0 + 0 + + + 0 + + + + -1 + # DDR3/4_NONIOU + + + + 0 + 0 + + + 0 + + + + -1 + ddr_ddrvref0_L19 + + + + 0 + 0 + + + 0 + + + + -1 + ddr_ddrvref1_L20 + + + + 0 + 0 + + + 0 + + + + -1 + ddr_cal_g_H10 + + + + 0 + 0 + + + 0 + + + + -1 + ddr_cal_r_H11 + + + + 0 + 0 + + + 0 + + + + -1 + usb0_clk_A09 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dat_0_C10 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dat_1_D09 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dat_2_C09 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dat_3_A08 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dat_4_B08 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dat_5_C08 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dat_6_D08 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dat_7_E08 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_stp_G09 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_dir_F08 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_nxt_G08 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb0_reset_n_J10 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_clk_A06 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dat_0_B07 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dat_1_C07 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dat_2_C06 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dat_3_A05 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dat_4_B05 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dat_5_C05 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dat_6_B04 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dat_7_C04 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_stp_A03 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_dir_E07 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_nxt_D05 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + usb1_reset_n_D06 + usb-master-unit + + + 0 + 0 + + + 0 + + + + -1 + fsim0_clk_AH03 + fsi-master-unit + + + 0 + 0 + output + push-pull + 0 + + + + -1 + fsim0_dio_AH05 + fsi-master-unit + + + 0 + 0 + bidi + push-pull + 0 + + + + -1 + fsim1_clk_AH02 + fsi-master-unit + + + 0 + 1 + + + 0 + + + + -1 + fsim1_dio_AG04 + fsi-master-unit + + + 0 + 1 + + + 0 + + + + -1 + fsis0_clk_AG22 + fsi-slave-unit + + + 0 + 0 + + + 0 + + + + -1 + fsis0_dio_AH20 + fsi-slave-unit + + + 0 + 0 + + + 0 + + + + -1 + fsis1_clk_AF21 + fsi-slave-unit + + + 0 + 1 + + + 0 + + + + -1 + fsis1_dio_AH21 + fsi-slave-unit + + + 0 + 1 + + + 0 + + + + -1 + iou_i2c0_scl_V28 + i2c-master-unit + + + 14 + 0 + + + 0 + + + + -1 + iou_i2c0_sda_V27 + i2c-master-unit + + + 14 + 0 + + + 0 + + + + 00 + fsp2_chip_rst_n_B28 + gpio-master-unit + 00 + 0 + 16 + 0 + output + open-drain + 0 + 1 + + + 01 + oppanel_presence_n_C28 + presence-master-unit + 00 + 0 + 16 + 1 + input + open-drain + 0 + 1 + + + 02 + storage_backplane_presence_n_C27 + presence-master-unit + 00 + 0 + 16 + 2 + input + open-drain + 0 + 1 + + + 03 + native_iocard_presence_n_D26 + presence-master-unit + 00 + 0 + 16 + 3 + input + open-drain + 0 + 1 + + + 04 + led_yellow_planar_E28 + led-driver-unit + 01 + 0 + 16 + 4 + output + open-drain + 0 + 0 + + + 05 + led_green_network_reset_D27 + led-driver-unit + 01 + 0 + 16 + 5 + output + open-drain + 0 + 0 + + + 06 + led_pcie_slot_c2_yel_E26 + led-driver-unit + 01 + 0 + 16 + 6 + output + open-drain + 0 + 0 + + + 08 + led_yellow_tod_battery_F28 + led-driver-unit + 02 + 0 + 16 + 8 + output + open-drain + 0 + 0 + + + 09 + led_yellow_dcm1_F27 + led-driver-unit + 02 + 0 + 16 + 9 + output + open-drain + 0 + 0 + + + 10 + led_yellow_dcm2_F26 + led-driver-unit + 02 + 0 + 16 + 10 + output + open-drain + 0 + 0 + + + 11 + led_blue_id_F25 + led-driver-unit + 02 + 0 + 16 + 11 + output + open-drain + 0 + 0 + + + 12 + fengjia_c3_presence_n_G27 + presence-master-unit + 03 + 0 + 16 + 12 + input + open-drain + 0 + 1 + + + 13 + fengjia_c5_presence_n_G26 + presence-master-unit + 03 + 0 + 16 + 13 + input + open-drain + 0 + 1 + + + 14 + fengjia_c6_presence_n_H25 + presence-master-unit + 03 + 0 + 16 + 14 + input + open-drain + 0 + 1 + + + 15 + fengjia_c7_presence_n_G24 + presence-master-unit + 03 + 0 + 16 + 15 + input + open-drain + 0 + 1 + + + 16 + DASD_pca9554_int_n_J23 + gpio-slave-unit + 04 + 0 + 16 + 16 + input + + 0 + + + + 17 + network_switch_reset_n_H23 + presence-master-unit + 04 + 0 + 16 + 17 + input + open-drain + 0 + 1 + + + 18 + led_yellow_sysinfo_F24 + led-driver-unit + 04 + 0 + 16 + 18 + output + open-drain + 0 + 0 + + + 19 + tod_battery_test_J22 + gpio-master-unit + 04 + 0 + 16 + 19 + output + push-pull + 0 + 0 + + + 20 + tod_battery_low_n_H28 + gpio-slave-unit + 05 + 0 + 16 + 20 + input + + 0 + + + + 21 + led_pcie_slot_c3_yel_H26 + led-driver-unit + 05 + 0 + 16 + 21 + output + open-drain + 0 + 0 + + + 22 + ps_ffs_sync_n_J26 + gpio-master-unit + 05 + 0 + 16 + 22 + output + open-drain + 0 + 1 + + + 23 + apps_reset_n_J25 + gpio-master-unit + 05 + 0 + 16 + 23 + output + open-drain + 0 + 1 + + + 27 + dpss_init_n_L22 + gpio-slave-unit + 06 + 0 + 16 + 27 + input + open-drain + 0 + + + + 28 + dpss_prog_n_K21 + gpio-master-unit + 07 + 0 + 16 + 28 + output + open-drain + 0 + 1 + + + 29 + dpss_sys_rst_n_L23 + gpio-master-unit + 07 + 0 + 16 + 29 + output + open-drain + 0 + 1 + + + 30 + dpss_i2c_int_n_M23 + gpio-slave-unit + 07 + 0 + 16 + 30 + input + open-drain + 0 + + + + 31 + apss_boot_mode_M22 + gpio-master-unit + 07 + 0 + 16 + 31 + output + push-pull + 0 + 0 + + + 32 + SC_CLK[0] + sc-master-unit + 08 + 4 + 15 + 24 + output + push-pull + 0 + + + + 33 + SC_DIO[0] + sc-master-unit + 08 + 4 + 15 + 24 + bidi + open-drain + 0 + + + + 34 + SC_RST[0] + sc-master-unit + 08 + 4 + 15 + 24 + output + open-drain + 0 + + + + 35 + dpss_unlatch_n_L26 + gpio-master-unit + 08 + 0 + 17 + 35 + output + open-drain + 0 + 1 + + + 36 + SC_CLK[1] + sc-master-unit + 09 + 4 + 15 + 25 + output + push-pull + 0 + + + + 37 + SC_DIO[1] + sc-master-unit + 09 + 4 + 15 + 25 + bidi + open-drain + 0 + + + + 38 + SC_RST[1] + sc-master-unit + 09 + 4 + 15 + 25 + output + open-drain + 0 + + + + 39 + ps_i2c_rst_n_M24 + gpio-master-unit + 09 + 0 + 17 + 39 + output + open-drain + 0 + 1 + + + 40 + cpu_spi_nor_rst_n_W27 + gpio-master-unit + 10 + 0 + 17 + 40 + output + open-drain + 0 + 1 + + + 41 + cpu_pp_state_Y26 + gpio-slave-unit + 10 + 0 + 17 + 41 + input + + 0 + + + + 42 + buddy_rst_out_n_W26 + gpio-master-unit + 10 + 0 + 17 + 42 + output + open-drain + 0 + 1 + + + 43 + fsp2_i2c_lightpath_reset_n_W24 + gpio-master-unit + 10 + 0 + 17 + 43 + output + open-drain + 0 + 1 + + + 44 + cm3_si5338_oe_n_V24 + gpio-master-unit + 11 + 0 + 17 + 44 + output + open-drain + 0 + 0 + + + 45 + cm2_si5335b_oeb2_n_V23 + gpio-master-unit + 11 + 0 + 17 + 45 + output + open-drain + 0 + 0 + + + 46 + cm2_si5335b_oeb3_n_U22 + gpio-master-unit + 11 + 0 + 17 + 46 + output + open-drain + 0 + 0 + + + 47 + dpss_pgood_cpu_T21 + gpio-slave-unit + 11 + 0 + 17 + 47 + input + open-drain + 0 + + + + 48 + I2C_SCL[10] + i2c-master-unit + 12 + 1 + 14 + 10 + output + open-drain + 0 + + + + 49 + I2C_SDA[10] + i2c-master-unit + 12 + 1 + 14 + 10 + bidi + open-drain + 0 + + + + 50 + I2C_SCL[1] + i2c-master-unit + 12 + 1 + 14 + 1 + output + open-drain + 0 + + + + 51 + I2C_SDA[1] + i2c-master-unit + 12 + 1 + 14 + 1 + bidi + open-drain + 0 + + + + 52 + I2C_SCL[2] + i2c-master-unit + 13 + 1 + 14 + 2 + output + open-drain + 0 + + + + 53 + I2C_SDA[2] + i2c-master-unit + 13 + 1 + 14 + 2 + bidi + open-drain + 0 + + + + 54 + I2C_SCL[3] + i2c-master-unit + 13 + 1 + 14 + 3 + output + open-drain + 0 + + + + 55 + I2C_SDA[3] + i2c-master-unit + 13 + 1 + 14 + 3 + bidi + open-drain + 0 + + + + 56 + I2C_SCL[4] + i2c-master-unit + 14 + 1 + 14 + 4 + output + open-drain + 0 + + + + 57 + I2C_SDA[4] + i2c-master-unit + 14 + 1 + 14 + 4 + bidi + open-drain + 0 + + + + 58 + I2C_SCL[5] + i2c-master-unit + 14 + 1 + 14 + 5 + output + open-drain + 0 + + + + 59 + I2C_SDA[5] + i2c-master-unit + 14 + 1 + 14 + 5 + bidi + open-drain + 0 + + + + 60 + I2C_SCL[6] + i2c-master-unit + 15 + 1 + 14 + 6 + output + open-drain + 0 + + + + 61 + I2C_SDA[6] + i2c-master-unit + 15 + 1 + 14 + 6 + bidi + open-drain + 0 + + + + 62 + I2C_SCL[7] + i2c-master-unit + 15 + 1 + 14 + 7 + output + open-drain + 0 + + + + 63 + I2C_SDA[7] + i2c-master-unit + 15 + 1 + 14 + 7 + bidi + open-drain + 0 + + + + 64 + I2C_SCL[8] + i2c-master-unit + 16 + 1 + 14 + 8 + output + open-drain + 0 + + + + 65 + I2C_SDA[8] + i2c-master-unit + 16 + 1 + 14 + 8 + bidi + open-drain + 0 + + + + 66 + I2C_SCL[9] + i2c-master-unit + 16 + 1 + 14 + 9 + output + open-drain + 0 + + + + 67 + I2C_SDA[9] + i2c-master-unit + 16 + 1 + 14 + 9 + bidi + open-drain + 0 + + + + 68 + I2CMD2_SCL + i2c-master-unit + 17 + 1 + 9 + 0 + output + open-drain + 0 + + + + 69 + I2CMD2_SDA + i2c-master-unit + 17 + 1 + 9 + 0 + bidi + open-drain + 0 + + + + 70 + I2CMD1_SCL + i2c-master-unit + 17 + 1 + 8 + 0 + output + open-drain + 0 + + + + 71 + I2CMD1_SDA + i2c-master-unit + 17 + 1 + 8 + 0 + bidi + open-drain + 0 + + + + 72 + system_pg_pex8732_AF28 + gpio-master-unit + 18 + 0 + 18 + 72 + output + open-drain + 0 + 1 + + + 73 + system_pg_pex8748_AE27 + gpio-master-unit + 18 + 0 + 18 + 73 + output + open-drain + 0 + 1 + + + 74 + system_pg_dcm_AE26 + gpio-master-unit + 18 + 0 + 18 + 74 + output + open-drain + 0 + 1 + + + 78 + U750_RX[0] + s16550-master-unit + 19 + 5 + 4 + 0 + input + push-pull + 0 + + + + 79 + U750_TX[0] + s16550-master-unit + 19 + 5 + 4 + 0 + output + push-pull + 0 + + + + 80 + U750_DSR[1] + s16550-master-unit + 20 + 5 + 5 + 1 + input + push-pull + 0 + + + + 81 + U750_DTR[1] + s16550-master-unit + 20 + 5 + 5 + 1 + output + push-pull + 0 + + + + 82 + U750_DCD[1] + s16550-master-unit + 20 + 5 + 5 + 1 + output + push-pull + 0 + + + + 83 + U750_RI[1] + s16550-master-unit + 20 + 5 + 5 + 1 + input + push-pull + 0 + + + + 84 + U750_RTS[1] + s16550-master-unit + 21 + 5 + 5 + 1 + output + push-pull + 0 + + + + 85 + U750_CTS[1] + s16550-master-unit + 21 + 5 + 5 + 1 + input + push-pull + 0 + + + + 86 + U750_RX[1] + s16550-master-unit + 21 + 5 + 5 + 1 + input + push-pull + 0 + + + + 87 + U750_TX[1] + s16550-master-unit + 21 + 5 + 5 + 1 + output + push-pull + 0 + + + + 88 + U750_RX[1] + s16550-master-unit + 22 + 5 + 5 + 1 + input + + 0 + + + + 96 + FSIM_CLK[2] + fsi-master-unit + 24 + 1 + 0 + 2 + output + push-pull + 0 + + + + 97 + FSIM_DIO[2] + fsi-master-unit + 24 + 1 + 0 + 2 + bidi + push-pull + 0 + + + + 98 + FSIM_CLK[3] + fsi-master-unit + 24 + 1 + 0 + 3 + output + push-pull + 0 + + + + 99 + FSIM_DIO[3] + fsi-master-unit + 24 + 1 + 0 + 3 + bidi + push-pull + 0 + + + + 100 + cpu0_cfam_reset_n_AC20 + gpio-master-unit + 25 + 0 + 19 + 100 + output + open-drain + 0 + 1 + + + 101 + pex_i2c_smbus_cfg_en_n_AD18 + gpio-master-unit + 25 + 0 + 19 + 101 + output + open-drain + 1 + 1 + + + 102 + fsp2_pex32_perst_n_AD19 + gpio-master-unit + 25 + 0 + 19 + 102 + output + open-drain + 1 + 1 + + + 103 + fsp2_pex48_perst_n_AC18 + gpio-master-unit + 25 + 0 + 19 + 103 + output + open-drain + 1 + 1 + + + + + + + +DRAM0 +DDR3 +4 + + +DRAM1 +DDR3 +4 + + +DRAM2 +DDR3 +4 + + + + +NAND0 +NAND +4 +eMMC + + +INOR0 +NOR +64 +SPI + + +PNOR0 +NOR +64 +SPI-FPGA-CFAM + + + + +NVRAM0 +128 + + + + + + + \ No newline at end of file diff --git a/TUSB7340.xml b/TUSB7340.xml new file mode 100644 index 0000000..1a25548 --- /dev/null +++ b/TUSB7340.xml @@ -0,0 +1,53 @@ + + + + + + TUSB7340 + chip + usb + x0pxxxx + TI USB3.0 4-port + + + PCIE_X11 + + + USB003.0 + USB103.0 + USB203.0 + USB303.0 + + + RESETRESET + + + + 1.05V + VDD11 + 1.05 + 0.01 + 0.02 + + + 3.3V1 + VDD33 + 3.3 + 0.01 + 0.02 + + + 3.3V2 + VDDA33 + 3.3 + 0.01 + 0.02 + + + + + + diff --git a/VENICE.xml b/VENICE.xml new file mode 100644 index 0000000..705f670 --- /dev/null +++ b/VENICE.xml @@ -0,0 +1,323 @@ + + + + + + VENICE + chip + DD1 + cpu + IBM Power8 + yes + + ex1ex1 + core1core1 + + ex2ex2 + core2core2 + + ex3ex3 + core3core3 + + ex4ex4 + core4core4 + + ex5ex5 + core5core5 + + ex6ex6 + core6core6 + + ex9ex9 + core9core9 + + ex10ex10 + core10core10 + + ex11ex11 + core11core11 + + ex12ex12 + core12core12 + + ex13ex13 + core13core13 + + ex14ex14 + core14core14 + + occocc0 + nxnx0 + porepore0 + mc0 + mcs0mcs0 + mcs1mcs1 + mcs2mcs2 + mcs3mcs3 + + mc1 + mcs4mcs4 + mcs5mcs5 + mcs6mcs6 + mcs7mcs7 + + + + + OSC0_CHIP_REFCLKproc0 + OSC0_PCIE_REFCLKpcie0 + OSC0_TOD_REFCLKtod0 + OSC1_CHIP_REFCLKproc1 + OSC1_PCIE_REFCLKpcie1 + OSC1_TOD_REFCLKtod1 + + + + I2C0 + SDA0 + + I2C Slave for BMC connection + + + + I2CM_PROM60cfam0 + I2CM_PROC_PROM00 + I2CM_PROM161cfam0 + I2CM_PROC_PROM101 + I2CM_HOTPLUG11 + I2CM_LIGHTPATH10 + + + OSC0_OSCSW_CTL0 + OSC0_OSCSW_CTL1 + OSC1_OSCSW_CTL0 + OSC1_OSCSW_CTL1 + + + OSC0_USE_OSC0 + OSC0_USE_OSC1 + OSC1_USE_OSC0 + OSC1_USE_OSC1 + + + SPISPI + + + PSI + + + FSI_SLAVE00 + FSI_SLAVE11 + + + FSI_CASCADE0 0120cfam0 + FSI_CASCADE1 0121cfam0 + FSI_CASCADE2 0122cfam0 + FSI_CASCADE3 0123cfam0 + FSI_CASCADE4 0124cfam0 + FSI_CASCADE5 0125cfam0 + FSI_CASCADE6 0126cfam0 + FSI_CASCADE7 0127cfam0 + FSI_CASCADE8 1120cfam0 + FSI_CASCADE9 1121cfam0 + FSI_CASCADE101122cfam0 + FSI_CASCADE111123cfam0 + FSI_CASCADE121124cfam0 + FSI_CASCADE131125cfam0 + FSI_CASCADE141126cfam0 + FSI_CASCADE151127cfam0 + + + MFSI0130cfam0 + MFSI1131cfam0 + MFSI2132cfam0 + MFSI3133cfam0 + MFSI4134cfam0 + MFSI5135cfam0 + MFSI6136cfam0 + MFSI7137cfam0 + + + + LPC + + + A0A + A1A + A2A + X0X + X1X + X2X + X3X + + + PCIE_IOP000 + PCIE_IOP0_108 + PCIE_IOP110 + + + + + DMI0mcs0 + DMI1mcs1 + DMI2mcs2 + DMI3mcs3 + DMI4mcs4 + DMI5mcs5 + DMI6mcs6 + DMI7mcs7 + + + + VDD0 + VDD0 + 1.0 + 180 + 212 + + + VCS0 + VCS + 1.05 + 18 + 21 + + + VIO + VIO + 1.05 + 18 + 21 + + + VPCI + VPCI + 1.2 + 5 + 3 + + + AVDD + AVDD + 1.5 + 2 + 1 + + + + + + + + + + PHB00 + PHB11 + PHB22 + + + + + + shift + 3 + + + + fsi2pib + 4 + + + + scratchpad + 5 + + + + i2cm + 6 + + + + mailbox + 10 + + + + cMFSI + 12 + + + + MFSI + 13 + + + + + + cfam0 + + + + + + + + yes + 32 + 128 + 128 + 4-way + + + + yes + 64 + 128 + 128 + 8-way + + + + yes + 512 + 128 + 128 + 8-way + + + + yes + 512 + 128 + 128 + 8-way + + + + 8 + 512 + 4 + 512 + 4 + 128 + no + no + no + no + no + yes + no + no + 8 + + + + + + + diff --git a/VRD_NOI2C.xml b/VRD_NOI2C.xml new file mode 100644 index 0000000..08ff38e --- /dev/null +++ b/VRD_NOI2C.xml @@ -0,0 +1,30 @@ + + + + + + VRD_NOI2C + vrd + vrd + VRD w/no I2C + 1 + 90 + 3.3 + + PGOODPGOOD + ENABLEENABLE + + 12V_IN12V_IN + 12 + + + + VOUTVOUT + + + + + diff --git a/ddr3_dimm_generic.xml b/ddr3_dimm_generic.xml new file mode 100644 index 0000000..e73479e --- /dev/null +++ b/ddr3_dimm_generic.xml @@ -0,0 +1,46 @@ + + + +ddr3_dimm_generic +dimm +DDR3 DIMM + + + DDR3_DRAM_ABSTRACT + DIMM_SPD + + + DDR3 DIMM + + + USPDDIMM_SPD0PRIMARY_FRU_VPD24c32 + U0DDR3_DRAM_ABSTRACT0 + + + UCONNDDR3 DIMM0 + + + + + ddr13 + UCONNDDR3_CH + U0DDR_INTERFACE + + + + + power12 + 0 + UCONNVMEM + U0VDD + + + + + i2c14 + UCONNI2CMASTER_DIMM + USPDSVPD + + + + diff --git a/mru-type-mapping.xml b/mru-type-mapping.xml new file mode 100644 index 0000000..ef7940e --- /dev/null +++ b/mru-type-mapping.xml @@ -0,0 +1,266 @@ + + + + + + unknown + 0xFFFF + + + + + + cpu + + proc-chip + 0x0001 + + + + + membuf + + membuf-chip + 0x0006 + + + + + fsp + + sp-chip + 0x0009 + + + + + cfam-s + + sp-iou-chip + 0x000A + + + + + pcie-switch + usb + + builtin-io + 0x000B + + + + + flash + + flash-chip + 0x000D + + + + + apss + + apss + 0x000E + + + + + dpss + + dpss + 0x000F + + + + + + dcm-module + + proc-module + 0x0100 + + + + + pcie-riser + + riser-card + 0x0101 + + + + + dimm + + dimm + 0x0102 + + + + + vrm + + vrm-card + 0x0104 + + + + + * + + card-asm + 0x0103 + + + + + + occ + + occ + 0x0201 + + + + + ex + + ex + 0x0202 + + + + + core + + core + 0x0203 + + + + + L2 + + L2 + 0x0204 + + + + + L3 + + L3 + 0x0205 + + + + + ncu + + ncu + 0x0206 + + + + + mcs + + mcs + 0x0207 + + + + + nx + + nx + 0x0208 + + + + + capp + + capp + 0x0209 + + + + + slw + + slw + 0x020A + + + + + as + + as + 0x020B + + + + + sbe + + sbe + 0x020C + + + + + L4 + + L4 + 0x020D + + + + + mba + + mba + 0x020E + + + + + + powerbus-unit,A + + abus + 0x0301 + + + + + powerbus-unit,X + + xbus + 0x0302 + + + + + pcie-root-unit,* + + pcie + 0x0303 + + + diff --git a/pcie_x16_card.xml b/pcie_x16_card.xml new file mode 100644 index 0000000..954236a --- /dev/null +++ b/pcie_x16_card.xml @@ -0,0 +1,43 @@ + + + +pcie_x16_card +pcie +PCIe x16 Card + + + PCIE_X16_ABSTRACT + + + PCIE_X16_SLOT + + + U3PCIE_X16_ABSTRACT0 + + + JSLOTPCIE_X16_SLOT0 + + + + + pcie2 + JSLOTPCIE_X16 + U3PCIE_X16 + + + + + power11 + 0 + JSLOT12V + U312V + + + power14 + 0 + JSLOT3.3V + U33.3V + + + + diff --git a/pcie_x8_card.xml b/pcie_x8_card.xml new file mode 100644 index 0000000..e94f6a6 --- /dev/null +++ b/pcie_x8_card.xml @@ -0,0 +1,43 @@ + + + +pcie_x8_card +pcie +PCIe x8 Card + + + PCIE_X8_ABSTRACT + + + PCIE_X8_SLOT + + + U0PCIE_X8_ABSTRACT0 + + + JSLOTPCIE_X8_SLOTignore0 + + + + + power97 + 0 + JSLOT3.3V + U03.3V + + + power94 + 0 + JSLOT12V + U012V + + + + + pcie88 + JSLOTPCIE_X8 + U0PCIE_X8 + + + + diff --git a/turismo_scm.xml b/turismo_scm.xml new file mode 100644 index 0000000..b031126 --- /dev/null +++ b/turismo_scm.xml @@ -0,0 +1,254 @@ + + + +turismo_scm +scm-module + + + + VENICEDD1 + MOD_SEEPROM_512 + + + TURISMO_SOCKET + + + U0VENICE0yesIBM Power8DD1 + U2MOD_SEEPROM_5120PRIMARY_SBE_VPD225624c512512 + U1MOD_SEEPROM_5121PRIMARY_FRU_AND_MODULE_VPD225624c512512 + U3MOD_SEEPROM_5122REDUNDANT_FRU_AND_MODULE_VPD225624c512512 + U4MOD_SEEPROM_5123REDUNDANT_SBE_VPD225624c512512 + + + JBSMTURISMO_SOCKET0 + + + + + dmi11 + U0DMI7 + JBSMDMI3 + + + dmi5 + U0DMI2 + JBSMDMI0 + + + dmi2 + U0DMI0 + JBSMDMI1 + + + dmi8 + U0DMI1 + JBSMDMI2 + + + + + clock20 + U0OSC0_TOD_REFCLK + JBSMOSC0_TOD_REFCLK + + + clock17 + U0OSC0_PCIE_REFCLK + JBSMOSC0_PCIE_REFCLK + + + clock2 + U0OSC0_CHIP_REFCLK + JBSMLPC_CLK + + + + + psi122 + U0PSI + JBSMPSI + + + + + spi62 + JBSMSPI + U0SPI + + + + + lpc2 + JBSMLPC + U0LPC + + + + + pcie5 + U0PCIE_IOP1 + JBSMPCIE1 + + + pcie2 + U0PCIE_IOP0 + JBSMPCIE0 + + + + + power155 + U0VDD0 + JBSMVDD + + + power149 + U0VIO + JBSMVIO + + + power152 + U0VCS0 + JBSMVCS + + + power146 + U0VPCI + JBSMVPCI + + + power143 + U0AVDD + JBSMAVDD + + + + + i2c11 + No +
A0
+ 400 + U0I2CM_PROM1 + U3I2C + + + i2c125 + U0I2C0 + JBSMI2C_0 + + + i2c2 + No +
0xA0
+ 400 + U1I2C + U0I2CM_PROM + + + i2c8 + No +
A2
+ 400 + U0I2CM_PROM1 + U4I2C + + + i2c5 + No +
A2
+ 400 + U0I2CM_PROM + U2I2C + + + i2c128 + U0I2CM_HOTPLUG + JBSMI2C_HOTPLUG + + + + + fsi65 + U0FSI_CASCADE3 + JBSMFSI0_CENT3 + + + fsi74 + U0FSI_CASCADE6 + JBSMFSI0_CENT6 + + + fsi2 + U0MFSI3 + JBSMMFSI3 + + + fsi62 + U0FSI_CASCADE2 + JBSMFSI0_CENT2 + + + fsi113 + U0MFSI2 + JBSMMFSI2 + + + fsi56 + U0FSI_CASCADE0 + JBSMFSI0_CENT0 + + + fsi110 + U0MFSI1 + JBSMMFSI1 + + + fsi77 + U0FSI_CASCADE7 + JBSMFSI0_CENT7 + + + fsi116 + U0FSI_SLAVE0 + JBSMFSI_A + + + fsi59 + U0FSI_CASCADE1 + JBSMFSI0_CENT1 + + + + + powerbus53 + No + 0x00000000 + No + 2 + 0x00000000 + U0A0 + JBSMA0 + + + powerbus47 + No + 0x00000000 + No + 2 + 0x00000000 + U0A2 + JBSMA2 + + + powerbus50 + No + 0x00000000 + No + 2 + 0x00000000 + U0A1 + JBSMA1 + + + + -- cgit v1.2.1 From 04ac644ac0b84b181a1bbdd6ed636bcc64302f3e Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Thu, 14 Aug 2014 12:57:49 -0500 Subject: Add schema and xslt files --- schema/mrw.xsd | 9886 ++++++++++++++++++++++++++++++++++++++++++++++ xslt/mrwCecChips.xsl | 73 + xslt/mrwCentVRDs.xsl | 67 + xslt/mrwChipIDs.xsl | 69 + xslt/mrwDMIBusses.xsl | 79 + xslt/mrwFSIBusses.xsl | 92 + xslt/mrwI2CBusses.xsl | 335 ++ xslt/mrwMemoryBusses.xsl | 100 + xslt/mrwMruIds.xsl | 105 + xslt/mrwPCIEBusses.xsl | 328 ++ xslt/mrwPowerBusses.xsl | 191 + xslt/mrwTargets.xsl | 83 + 12 files changed, 11408 insertions(+) create mode 100644 schema/mrw.xsd create mode 100644 xslt/mrwCecChips.xsl create mode 100644 xslt/mrwCentVRDs.xsl create mode 100644 xslt/mrwChipIDs.xsl create mode 100644 xslt/mrwDMIBusses.xsl create mode 100644 xslt/mrwFSIBusses.xsl create mode 100644 xslt/mrwI2CBusses.xsl create mode 100644 xslt/mrwMemoryBusses.xsl create mode 100644 xslt/mrwMruIds.xsl create mode 100644 xslt/mrwPCIEBusses.xsl create mode 100644 xslt/mrwPowerBusses.xsl create mode 100644 xslt/mrwTargets.xsl diff --git a/schema/mrw.xsd b/schema/mrw.xsd new file mode 100644 index 0000000..1afd4c8 --- /dev/null +++ b/schema/mrw.xsd @@ -0,0 +1,9886 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Usually, a location code shows the card hierarchy in the system, + which each level of plug giving a segment in the full location code. + The absolute attribute controls if that segment is part of the full + location code or not, and can also be used for cases, typically fans + and power supplies, that don't obey the hierarchy. + + absolute="yes": + Don't use the location code segments in the previous hierarchy while + making this location code. + For example, for a fan, with location absolute="yes" and value A1 + the location code would be Ufcs-A1, even if it was plugged on a card + with a P1 location code + If it didn't say absolute="yes", the location code would be Ufcs-P1-A1. + + absolute="ignore". + Ignore this card's contribution to the location code hierarchy. + For example on the Laramie-0/Wyoming-0/Pryor-0 plugging hierarchy, + the wyoming has absolute="ignore", which gives a location code for + the pryor to be Ufcs-P1-C8, where the P1 is from the Laramie and the + C8 is from the pryor, without a contribution from the wyoming. + + + + + + + + + + + + + + + + This page is generated automatically from the MRW schema files. + Any updates or corrections must be done in the schema files. + + + + + + + + + + An endpoint address, or a register address. + + + + + + + + + + + + + + + + An alias name to refer to an element. + + + + + + + + + A reference to a specific assembly element. + + + + + + + + + + Cache associativity. + + + + + + + + + + + + + + + A bitmask value + + + + + + + + + Bit(s) of i2c port expander which is part of the secondary pgood checks, can be multiple of these. + + + + + + + + + The blink rate in Hertz, like 0, 2, etc, or empty. + + + + + + + + + TBD............................ + + + + + + + + + Bus width, in bytes. + + + + + + + + + + + + + + + + Defines the CAPI setting of a unit. + + + + + + + + + A reference to a card. + + + + + + + + + + A cache size. + + + + + + + + + + + + + + + + A cache line size. + + + + + + + + + + + + + + + + A cache block size. + + + + + + + + + + + + + + + + The human-readable card type, such as planar, dimm, etc. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + The four hex-digit CCIN value. + + + + + + + + + + + + + + The CFAM ID number/name. + + + + + + + + + Defines a CFAM unit. + + + + + + + + + + + + + + The CFAM units in this part. + + + + + + + + + + + + + + The channel number of a DDR unit. + + + + + + + + + Denotes when to check PGOOD during PSEQ. + + + + + + + + + Defines a connection-point's child in an assembly plug hierarchy. + + + + + + + + + A reference to a chiplet. + + + + + + + + + The cmfsi number of an FSI cascade master unit. + + + + + + + + + Defines the color of an LED. + + + + + + + + + + + + + + + + + + What this configuration is determined by, such as an MTM. + + + + + + + + + + + + + + + The value for the configuration-type, such as the actual MTM value. + + + + + + + + + A reference to a connector. + + + + + + + + + A reference to a connector instance. + + + + + + + + + Says this is the last segment of this bus and it has an endpoint + that is a connector instead of a part. + + + + + + + + + + + + + + + Describes the contents of a particular part, when applicable. + + + + + + + + + + The core processor type, such as "PowerPC440". + + + + + + + + + + The maximum current of a part. + + + + + + + + + + + + + + + + The nominal current of a part. + + + + + + + + + + + + + + + + + Number of data TLB entries + + + + + + + + + N way associativity for the data TLB + + + + + + + + + Contains the default value that should be set in the GPIO. + + + + + + + + + A human-readable description of the containing element. + + + + + + + + + Defines an /dev/aio_brk unit. + + + + + + + + + + + + + + + + Defines a set of /dev/aio_brk units. + + + + + + + + + + + + + + Defines an /dev/dd_ffdc_all unit. + + + + + + + + + + + + + + + + Defines a set of /dev/dd_ffdc_all units. + + + + + + + + + + + + + + Defines an /dev/dd_ffdc_all unit. + + + + + + + + + + + + + + + + Defines a set of /dev/dd_ffdc_all units. + + + + + + + + + + + + + + Defines an /dev/dd_ffdc_driver unit. + + + + + + + + + + + + + + + + Defines a set of /dev/dd_ffdc_driver units. + + + + + + + + + + + + + + Defines an /dev/dd_ffdc_process unit. + + + + + + + + + + + + + + + + Defines a set of /dev/dd_ffdc_process units. + + + + + + + + + + + + + + Defines an /dev/dd_ffdc_thread unit. + + + + + + + + + + + + + + + + Defines a set of /dev/dd_ffdc_thread units. + + + + + + + + + + + + + + Defines an /dev/dma unit. + + + + + + + + + + + + + + + + Defines a set of /dev/dma units. + + + + + + + + + + + + + + Defines an /dev/iomux unit. + + + + + + + + + + + + + + + + + Defines a set of /dev/iomux units. + + + + + + + + + + + + + + Defines an /dev/jtag-irq unit. + + + + + + + + + + + + + + + + + Defines a set of /dev/jtag-irq units. + + + + + + + + + + + + + + Defines an /dev/mbx unit. + + + + + + + + + + + + + + + + + Defines a set of /dev/mbx units. + + + + + + + + + + + + + + Defines an /dev/mbx/host unit. + + + + + + + + + + + + + + + + Defines a set of /dev/mbx/host units. + + + + + + + + + + + + + + Defines an internal FSP /dev mem unit + + + + + + + + + + + + + + + + + Defines a set of FSP /dev mem units + + + + + + + + + + + + + + Defines an internal FSP /dev misc unit + + + + + + + + + + + + + + + + + Defines a set of FSP /dev misc units + + + + + + + + + + + + + + Defines an internal FSP /dev mmc unit + + + + + + + + + + + + + + + + + Defines a set of FSP /dev mmc units + + + + + + + + + + + + + + Defines an internal FSP /dev rtc unit + + + + + + + + + + + + + + + + + Defines a set of FSP /dev rtc units + + + + + + + + + + + + + + Defines an internal FSP /dev mmc-host unit + + + + + + + + + + + + + + + + + Defines a set of FSP /dev mmc-host units + + + + + + + + + + + + + + Defines an internal FSP /dev mtd unit + + + + + + + + + + + + + + + + + Defines a set of FSP /dev mtd units + + + + + + + + + + + + + + Defines an internal FSP /dev mtdblock unit + + + + + + + + + + + + + + + + + Defines a set of FSP /dev mtdblock units + + + + + + + + + + + + + + Defines an internal FSP /dev scp unit + + + + + + + + + + + + + + + + + + Defines a set of FSP /dev scp units + + + + + + + + + + + + + + Defines an internal FSP /dev tone unit + + + + + + + + + + + + + + + + + + Defines a set of FSP /dev tone units + + + + + + + + + + + + + + Defines an internal FSP /dev uart unit + + + + + + + + + + + + + + + + + + Defines a set of FSP /dev uart units + + + + + + + + + + + + + + The device ID of a PCIe card. + + + + + + + + + + + + + + + A DIO number. + + + + + + + + + Defines a DIO + + + + + + + + + + + + + + + + + + + + + + + + + Defines a set of dio configs + + + + + + + + + + + + + + Specifies an IN or OUT direction. + + + + + + + + + + + + + + + + + + + + + The downstream n_/p_ lane swap values for powerbus and DMI bus links. + It's a bitmask where if the bit is set then the corresponding + lane is swapped. Bit 31 is tx_clk_invert. + + + + + + + + + + + + + + Defines the amount of memory in a DRAM module. + + + + + + + + + + + + + + + + Defines the type of a DRAM (memory) module. + + + + + + + + + + + + + + + A GPIO's driver type + + + + + + + + + + + + + + + + The engineering change (EC) level of a hardware part. + This is only needed when different + levels are functionally different and the system being defined requires + a specific level. + + + + + + + + + Defines whether or not the containing element can be an ecmd target. + + + + + + + + + The engineering change (EC) level at which a hardware part for a particular CCIN + is to operate. + + + + + + + + + + Defines the enable-power units + + + + + + + + + + + + + + + + + Defines a set of enable-power units. + + + + + + + + + + + + + + Defines a enable unit + + + + + + + + + + + + + + + + Defines a enable master unit + + + + + + + + + + + + + + + + Defines a set of enable units + + + + + + + + + + + + + + Defines a set of enable master-units + + + + + + + + + + + + + + Defines the enclosure/drawer type of a platform. + + + + + + + + + + + + + + + + Defines an engine number. + + + + + + + + + + Defines an internal CFAM engine unit + + + + + + + + + + + + + + + + Defines a set of CFAM engines + + + + + + + + + + + + + + + Defines an ethernet unit + + + + + + + + + + + + + + + + + + Defines a set of ethernet units + + + + + + + + + + + + + + + The external ID for an entity. + + + + + + + + + What to do upon a PGOOD fault. + + + + + + + + + An I2C address. + + + + + + + + + Defines the host interface to the flash module. + + + + + + + + + + + + + + + + Defines the amount of space in a flash module. + + + + + + + + + + + + + + + + Defines the technology type of a flash module. + + + + + + + + + + + + + + + Defines the frequency of a hardware part. + + + + + + + + + + + + + + + + The function of an LED indicator or GPIO pin, etc. + + + + + + + + + Defines a GPIO unit. + + + + + + + + + + The identification string for the containing entity. + + + + + + + + + To support varying cable configuration for different node configurations, + this element defines what set of configurations the containing element + is applicable for. + + + + + + + + + + + + + + + + + + + + + ID of a secondary pgood I/O expander. + + + + + + + + + + Number of instruction TLB entries + + + + + + + + + N way associativity for the instruction TLB + + + + + + + + + + Specifies the PCIE IOP instance number in the processor chip. + + + + + + + + + + + + + + + + + Is the entity on standby power. + + + + + + + + + Defines an LED rollups for a card or part. + + + + + + + + + + + + + + + + + + + Defines a set of LED rollups. + + + + + + + + + + + + + + + The ID of an FSI link. + + + + + + + + + The location code for the containing entity. + + + + + + + + + + + + + + + + The location code for the containing entity. + + + + + + + + + + + + + + + + Indicates whether the power thermal location is to be enforced. + + + + + + + + + + + + + + + + If the processor has a logically unified L1 instruction and data cache + + + + + + + + + i.e. the DMI_REFCLOCK_SWIZZLE. The bit number to set in the refclock enable + field of the FSI GP8 register in P8 to enable the refclock to this DMI bus. + + + + + + + + + The four hex-digit MRU ID instance number. + + + + + + + + + The MRU type of this card/part. This overrides the default mapping + based on card-type/part-type that is normally correct. + + + + + + + + + + + + + + + + + + + + + + + + + + The mux group number of the containing unit. + + + + + + + + + The mux select numeric value of the containing unit. + + + + + + + + + The name of an entity + + + + + + + + + n/a + + + + + + + + + + + + + + + Defines the amount of memory in a NVRAM module. + + + + + + + + + + + + + + + + + TBD............................ + + + + + + + + + + The function of an LED when it is off. + + + + + + + + + Defines a connection-point's child in an assembly plug hierarchy. + + + + + + + + + Defines the class of a part, + such as chip, sp, etc. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + A reference to an associated/target part. + + + + + + + + + A reference to a part instance. + + + + + + + + + The hardware part number. + + + + + + + + + The hardware part type, + such as seeprom, io, etc. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines the power characteristics of a PCIe card in a system. + + + + + + + + + + + + + + + + + + + + + The cooling type of a PCIe card. + + + + + + + + + + + + + + The default cooling type of a PCIe card. + + + + + + + + + + + + + + + Defines the power characteristics of PCIe cards in a system. + + + + + + + + + + + + + + Specified is the containing entry is on a per-cpu basis + + + + + + + + + + Identifies a PCI Host Bridge (PHB) in a PCI-E unit. + + + + + + + + + + If the processor has a physically unified L1 instruction and data cache + + + + + + + + + The name of a pin. + + + + + + + + + A pin "number", which may include characters as well (e.g. "H27"). + + + + + + + + + Defines a port number. + + + + + + + + + Defines the position of a plug. + + + + + + + + + Defines an internal FSP ppp unit + + + + + + + + + + + + + + + + + Defines a set of FSP ppp units + + + + + + + + + + + + + + Defines the power consumption of a hardware part. + + + + + + + + + + + + + + + Defines the default power consumption of a hardware part. + + + + + + + + + + + + + + + + The processor family, such as "IBM Power8". + + + + + + + + + TLB reservation size + + + + + + + + + + + + + + + + The target location code of an LED to be rolled up + from this card/part's LED. This may be an explicit location code string or it may + contain special pattern strings: + Ux = substitute the assembly's location code + Ux-Px = substitute the card's location code within this assembly + + + + + + + + + + + + + + + + Defines a set of LED rollup target location codes + + + + + + + + + + + + + + The replaceable unit type. This is cru, fru, mru, or the card-id + of the card acting as the FRU in the case of combined card FRUs. + + + + + + + + + + Specifies if the RX MSB and LSB are swapped along this segment of the bus. + + + + + + + + + + + + + + + Specifies if the TX MSB and LSB are swapped along this segment of the bus. + + + + + + + + + + + + + + + The number of bytes a SEEPROM device requires to set its internal address/offset. + + + + + + + + + The size of the SEEPROM memory in KB. + + + + + + + + + The SEEPROM write-page boundary in bytes. + + + + + + + + + A reference to a selection group. + + + + + + + + + + Defines a slot number. + + + + + + + + + Defines the first PCIE lane in a pcie-root-unit. Can be either 0 or 8. + + + + + + + + + + + + + + + Defines a sub-type, when necessary + + + + + + + + + + + + + + + If the processor has a split TLB organization + + + + + + + + + The subsystem device ID of a PCIe card. + + + + + + + + + + + + + + The subsystem vendor ID of a PCIe card. + + + + + + + + + + + + + + If the processor supports the tlbia instruction + + + + + + + + + If the processor CPU has a performance monitor + + + + + + + + + If the processor supports the instructions stfiwx/fres/frsqrte/fsel + + + + + + + + + If the processor support an external control facility + + + + + + + + + If the processor support bridge facilities + + + + + + + + + + The human-readable system type, such as apollo, pegasus, etc. + + + + + + + + + The FRU type for thermal sensors. + + + + + + + + + In a LED rollup, identifies the card's or part's location code. This is optional and + it is generally not required. The implicit value is "the location code of the card/part with + the specified ID". It would only be provided if there is an exception case where most of + the cards/parts rollup in the same way, but some specific instance of the card/part in this + assembly rolls up differently + + + + + + + + + + + + + + + + The name of a chiplet target. + + + + + + + + + The number of threads per core in the processor. + + + + + + + + + A human-readable title string for a containing entity. + This can be thought of as an extension of the id element which + may be added for readability. + + + + + + + + + A power bus type. + + + + + + + + + The name of a hardware unit. + + + + + + + + + A unit type + + + + + + + + + A unit ID + + + + + + + + + + The upstream n_/p_ lane swap values for powerbus and DMI bus links. + It's a bitmask where if the bit is set then the corresponding + lane is swapped. Bit 31 is tx_clk_invert. + + + + + + + + + + + + + + The value associated with containing element. + + + + + + + + + The vendor ID of a PCIe card. + + + + + + + + + + + + + + A reference to a virtual connector. + + + + + + + + + + The angle from which an LED is visible. + + + + + + + + + + + + + + + + + + + + + + + Specifies if the LED angle of view is front. + + + + + + + + + + + + + + + + Specifies if the LED angle of view is internal. + + + + + + + + + + + + + + + + Specifies if the LED angle of view is rear. + + + + + + + + + + + + + + + + + Encodes the size of a VPD chip. + Number after the 'c' is the size in kbits. + + + + + + + + + + + + + + + + + + + Defines the voltage of a hardware part. + + + + + + + + + + + + + + + + + Defines the output voltage of a part + + + + + + + + + + + + + + + + + Defines the VRM for a power rail. + + + + + + + + + Defines the width of a PCI-E endpoint. + + + + + + + + + + + Defines a connection to a Analog to Digital Converter + + + + + + + + + + + + + + + + Defines the the ADC busses + + + + + + + + + + + + + + + Defines an adc unit. + + + + + + + + + + + + + + + + Defines a set of adc units. + + + + + + + + + + + + + + Defines the set of plug assemblies for a system. + + + + + + + + + + + + + + This is the "assembly manifest" for this system. It + lists the specific assemblies (aka "enclosures") included in + this system config, with the position in which they are used. + It lists each assembly by name, referring to the assemblies section for + details about the assembly topologies. + + + + + + + + + + + + + + Defines a plug assembly for a system. + + + + + + + + + + + + + + + + + A reference to an assembly used within a system. + + + + + + + + + + + + + + + + + + + Defines the set of busses in a card. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines a card in a system. + + + + + + + + + + + + + + + + + + + + + + + + + + Defines the set of cards available to a system. + + + + + + + + + + + + + + Defines a card actually used in a system, along with the data + that may be unique to that system's usage of the card such as + EC level, replaceable unit type, etc. + + + + + + + + + + + + + + + + + Defines the set of cards actually used in a system. + + + + + + + + + + + + + + Defines the CCIN of a hardware part. + + + + + + + + + + + + + + + + + + + + + + Defines a chiplet. + + + + + + + + + + + + + + + + + Defines a set of chiplets. + + + + + + + + + + + + + + Defines a set of CCINs. + + + + + + + + + + + + + + Defines an CFSI bus. + + + + + + + + + + + + + + + + Defines the CFSI busses. + + + + + + + + + + + + + + + Defines a clock bus. + + + + + + + + + + + + + + + + Defines the set of clock busses available to a system. + + + + + + + + + + + + + + + Contains entries that make up a specific configuration + + + + + + + + + + + + + + + + + Defines a set of configuration specific settings + + + + + + + + + + + + + + Contains 1 specific configuration data entry. + + + + + + + + + + + + + + + + + + + Contains a list of configuration entries. + + + + + + + + + + + + + + + Defines the characteristics of a connection point for an assembly plug. + + + + + + + + + + + + + + + Defines the characteristics of a connector. + + + + + + + + + + + + + + + + Maps actual to virtual connector in a selection group. + + + + + + + + + + + + + + + Defines an instance of a connector. + + + + + + + + + + + + + + + + + Defines the set of instanced of connectors in the containing entity. + + + + + + + + + + + + + + Maps actual to virtual connectors in a selection group. + + + + + + + + + + + + + + This is a reference to a connector used in the containing elements. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines a cooling zone of the containing entity. + + + + + + + + + + + + + + + + + + + + + + + + + + Defines the cooling zones of the containing entity. + + + + + + + + + + + + + + + + + Defines an 8-bit bitmask that lists which cooling zones something belongs in. + Each bit represents a cooling zone where the lsb is for zone 1. + + + + + + + + + + + + + + Defines a fan zone management in the containing entity. + + + + + + + + + + + + + + + + + + + + Defines fan zone managements for the containing entity. + + + + + + + + + + + + + + + Defines the processor cores in the containing entity. + + + + + + + + + + + + + + + + Contains CPU attributes needed by the OS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Contains attributes of the L1 data cache + + + + + + + + + + + + + + + + + + Defines a DDR bus. + + + + + + + + + + + + + + + + Defines the DDR busses. + + + + + + + + + + + + + + Defines a DDR master unit. + + + + + + + + + + + + + + + + + + + Defines a set of DDR master units. + + + + + + + + + + + + + + Defines a DDR slave unit. + + + + + + + + + + + + + + + + + + Defines a set of DDR slave units. + + + + + + + + + + + + + + Defines a DDR unit. + + + + + + + + + + + + + + + + + + Defines a set of DDR units. + + + + + + + + + + + + + + Defines a DIO unit. + + + + + + + + + + + + + + + + + Defines a set of DIO units. + + + + + + + + + + + + + + Defines a DMI bus. + + + + + + + + + + + + + + + + + + + + + + Defines the DMI busses. + + + + + + + + + + + + + + Defines a DMI master unit. + + + + + + + + + + + + + + + + + Defines a set of dmi-master-units. + + + + + + + + + + + + + + + Defines a DMI slave unit. + + + + + + + + + + + + + + Defines a set of dmi-slave-units. + + + + + + + + + + + + + + Defines a DRAM (memory) unit in the containing part. + + + + + + + + + + + + + + + + Defines the set of DRAM (memory) units in the containing part. + + + + + + + + + + + + + + Defines the index of duplication for parts that are split into more than 1 part definition. + Necessary for ServerWiz to find the correct part definition. + + + + + + + + + + Defines the endpoint of a bus. + + + + + + + + + + + + + + + + + + + Defines the units that represent error indicators + + + + + + + + + + + + + + + + + + + Defines a set of error units. + + + + + + + + + + + + + + Defines an Ethernet bus. + + + + + + + + + + + + + + + + Defines the Ethernet busses. + + + + + + + + + + + + + + Defines an EX (core) unit. + + + + + + + + + + + + + + + + Defines a set of EX (core) units. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines information about a fan in the containing entity. + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines the fan information for the containing entity. + + + + + + + + + + + + + + + Defines an fan controller unit. + + + + + + + + + + + + + + + Defines a set of fan controller units. + + + + + + + + + + + + + + Defines the flash storage internal unit within a part. + + + + + + + + + + + + + + + + + Defines the set of flash storage internal units within a part. + + + + + + + + + + + + + + Defines an FSI bus. + + + + + + + + + + + + + + + + Defines the FSI busses. + + + + + + + + + + + + + + Defines an FSI cascade master unit. + + + + + + + + + + + + + + + + + + Defines a set of cascade FSI master units. + + + + + + + + + + + + + + Defines an FSI master unit. + + + + + + + + + + + + + + + + + + + + + + + Defines a set of FSI master units. + + + + + + + + + + + + + + Defines an FSI slave unit. + + + + + + + + + + + + + + + + + Defines a set of FSI slave units. + + + + + + + + + + + + + + Defines a GPIO bus. + + + + + + + + + + + + + + + + Defines the GPIO busses. + + + + + + + + + + + + + + + Defines a GPIO master-unit. + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines a set of GPIO master units. + + + + + + + + + + + + + + + Defines a GPIO slave unit. + + + + + + + + + + + + + + + + + + + + + + + + Defines a set of GPIO units. + + + + + + + + + + + + + + Defines a GPIO unit. + + + + + + + + + + + + + + + + + + + + + + + + + Defines a set of GPIO units. + + + + + + + + + + + + + + Defines a GX bus. + + + + + + + + + + + + + + + + Defines the GX busses. + + + + + + + + + + + + + + Index into the HX VPD keyword this link uses, if applicable. Usually used for ITE Mezzanine cards. + + + + + + + + + + Defines an I2C bus. + + + + + + + + + + + + + + + + + + + Defines the I2C busses. + + + + + + + + + + + + + + Defines an I2C master unit. + + + + + + + + + + + + + + + + + + + + + + + + Defines a set of I2C master units. + + + + + + + + + + + + + + Defines an I2C slave unit. + + + + + + + + + + + + + + + + + + + + Defines a set of I2C slave units. + + + + + + + + + + + + + + Describes an IM Keyword and value for an MTM + + + + + + + + + + + + + + + + Describes a list of IM Keywords and values for MTMs + + + + + + + + + + + + + + + Defines a reference to an IM keyword. + + + + + + + + + Defines a set of IM keyword IDs. + + + + + + + + + + + + + + Contains attributes of the L1 instruction cache + + + + + + + + + + + + + + + + + + Contains internal attributes. (internal means serverwiz ignores them) + + + + + + + + + + + + + + + + + + + + + Defines the internal units within a part. These are units which do not + represent connections to other hardware. + + + + + + + + + + + + + + + + + + + Defines the jtag-master unit characteristics of a part. + + + + + + + + + + + + + + + + + + Defines a set of jtag-master units. + + + + + + + + + + + + + + + Contains attributes of the L2 cache + + + + + + + + + + + + + + + + + + Contains attributes of the L3 cache + + + + + + + + + + + + + + + + + + Defines the layout characteristics of a system + + + + + + + + + + + + + + + + + + + + + Defines a LED unit. + + + + + + + + + + + + + + + Defines a set of LED units. + + + + + + + + + + + + + + Defines an LED bus. + + + + + + + + + + + + + + + + Defines the LED busses. + + + + + + + + + + + + + + + Defines a LED driver unit. + + + + + + + + + + + + + + + + + + + + Defines a set of LED driver units. + + + + + + + + + + + + + + Defines a virtual connection between an LED and the FRU/part that + it is an indicator for. + + + + + + + + + + + + + + + + + + Defines a set of ledgroup virtual busses + + + + + + + + + + + + + + An led-group-unit is used to define the logical association between an + LED and what FRU it is an indicator for. It is not a physical + connection. + + + + + + + + + + + + + + Defines the set of LED group units + + + + + + + + + + + + + + + The same as led-group-unit. + + + + + + + + + + + + + + The same as led-group-units. + + + + + + + + + + + + + + + Defines an LPC bus. + + + + + + + + + + + + + + + + Defines an LPC *master* unit. + + + + + + + + + + + + + + + Defines a set of LPC *master* units. + + + + + + + + + + + + + + Defines an net-emac unit. + + + + + + + + + + + + + + + + Defines a set of net-emac units. + + + + + + + + + + + + + + Defines an net-mbx unit. + + + + + + + + + + + + + + + + Defines a set of net-mbx units. + + + + + + + + + + + + + + Defines an LPC slave unit. + + + + + + + + + + + + + + + Defines a set of LPC slave units. + + + + + + + + + + + + + + Defines the LPC busses. + + + + + + + + + + + + + + + IOMUX Voltage Mode Control Value, ie the MC value. + + + + + + + + + + + + + + + Describes a Machine Type Model + + + + + + + + + + + + + + + + Describes a list of Machine Type Models + + + + + + + + + + + + + + + A supported Machine Type Model + + + + + + + + + Describes a list of supported Machine Type Models + + + + + + + + + + + + + + + Defines the number of good cores in a processor + + + + + + + + + Defines number of current phases + + + + + + + + + Defines a non-volatile RAM unit in the containing part. + + + + + + + + + + + + + + + Defines the set of non-volatile RAM units in the containing part. + + + + + + + + + + + + + + Defines the characteristics/contents of a type of hardware part. + These are "black-box" parts that we just represent the interface(s) to + (e.g. chips). The set of parts enumerated may or may not be present in + this system. + This is one of a "bucket of parts" from which many different system + types may be built. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines an instance of a hardware part. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines the set of instances of parts in the containing entity. + + + + + + + + + + + + + + This is a reference to a part used in the containing elements. + + + + + + + + + + + + + + + + + + Defines a set of parts for a system. + + + + + + + + + + + + + + This is the "parts manifest" for this layout. It lists the parts actually + used, referring to part elements in the parts section without duplicating + any information. The only additional information included for parts here + is information which may vary from system-to-system for the same part, + such as the EC level and replaceable unit category. + + + + + + + + + + + + + + Defines a PCI-E bus. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PCIE max-virtual-functions attribute. + + + + + + + + + PCIE MSI attribute. + + + + + + + + + + PCIE slot index. + + + + + + + + + + If slot is CAPI enabled + + + + + + + + + + + + + + + If the slot is hot plug enabled + + + + + + + + + + + + + + + + If slot is DSMP (Distributed SMP) enabled + + + + + + + + + + + + + + + + If the endpoint is a physical pci slot + + + + + + + + + + + + + + + PCI card size. + + + + + + + + + + + + + + + + + + + + PCI generation + + + + + + + + + + the PCIE lane swap value + + + + + + + + + + + + + + + + + Size of the 64b DMA window + + + + + + + + + + Size of the 32b MMIO window + + + + + + + + + Size of the 64b MMIO window + + + + + + + + + The 3 bit PCIE lane swap value. + + + + + + + + + + + + + + The 3 bit PCIE lane reversal value. + + + + + + + + + + + + + + + If slot is LSI enabled + + + + + + + + + + + + + + + Size of the 32b DMA window + + + + + + + + + PCI bus width + + + + + + + + + + + + + + + + + Defines the PCI-E busses. + + + + + + + + + + + + + + Defines a endpoint of a PCI-E unit. + + + + + + + + + + + + + + + + Defines a set of endpoints of a PCI-E unit. + + + + + + + + + + + + + + Defines an internal PCIE PHB unit. + + + + + + + + + + + + + + + + Defines a set of PCIE PHB units + + + + + + + + + + + + + + + Defines a PCI-E root unit. + + + + + + + + + + + + + + + + + + + Defines a set of PCI-E root units. + + + + + + + + + + + + + + + Defines a PCI-E downstream bridge unit. This is the unit on a PCIE switch + that connects dopwnstream to an endpoint. + + + + + + + + + + + + + + + + + + + Defines a set of PCI-E downstream bridge units. + + + + + + + + + + + + + + + Defines a PCI-E upstream bridge unit. This is the unit on a PCIE switch + that connects upstream to the master pci-root. + + + + + + + + + + + + + + + + + + + Defines a set of PCI-E upstream bridge units. + + + + + + + + + + + + + + Defines a LED driver unit. + + + + + + + + + + + + + + + + + + + + + Defines a set of LED driver units. + + + + + + + + + + + + + + + The ID of the PGOOD this secondary pgood utilizes. + + + + + + + + + Defines a power good unit + + + + + + + + + + + + + + + + + + + + + Defines a set of pgood units + + + + + + + + + + + + + + Indicates whether the card is pluggable at standby. + + + + + + + + + Defines a plug in an assembly. + + + + + + + + + + + + + + + + + + + + + Defines cabling scheme. + + + + + + + + + + + + + + + A list of card instances from the cabling diagram. + + + + + + + + + + + + + + A single card instance from the cabling diagram. + + + + + + + + + + + + + + Defines a single cable connection. + + + + + + + + + + + + + + + + + + + + + + + + + + Indicates the type of cable represented by the containing element. + + + + + + + + + + + + + + + + + Binary identification code for this cable. + + + + + + + + + Indicates a virtual or real object. + + + + + + + + + + + + + + + The identification for the source card instance of a cable. + + + + + + + + + The identification for the connector instance within the source card of a cable. + + + + + + + + + The instance of the source connector from the source card. + + + + + + + + + The identification for the target card instance of a cable. + + + + + + + + + The identification for the connector instance within the target card of a cable. + + + + + + + + + The instance of the target connector from the target card. + + + + + + + + + Indicates positive or negative polarity of something. + + + + + + + + + + + + + + + + The Power On Reset value + + + + + + + + + + + + + + + + + Defines the power connection/bus + + + + + + + + + + + + + + + + + Defines a set of power connections + + + + + + + + + + + + + + + + The power efficiency rating of a part. + + + + + + + + + + + + + + + + Defines a power rail. + + + + + + + + + + + + + + + + + Defines a set of power rails. + + + + + + + + + + + + + + Defines the power unit characteristics of a part. + + + + + + + + + + + + + + + + + + Defines a set of power units. + + + + + + + + + + + + + + + Defines the power input unit characteristics of a part. + + + + + + + + + + + + + + + + + + + + Defines a set of power input units. + + + + + + + + + + + + + + + Defines the power output unit characteristics of a part. + + + + + + + + + + + + + + + + + + + + Defines a set of power input units. + + + + + + + + + + + + + + Defines the power sequencing unit characteristics of a part. + + + + + + + + + + + + + + + Defines a set of power sequencing units. + + + + + + + + + + + + + + Defines a power bus. + + + + + + + + + + + + + + + + + + + + + + Defines the power busses. + + + + + + + + + + + + + + Defines a power bus unit. + + + + + + + + + + + + + + + Defines a power bus units. + + + + + + + + + + + + + + Defines a bus used for presence detect + + + + + + + + + + + + + + + + Defines a set of presence detect busses + + + + + + + + + + + + + + Defines an endpoint unit of a presence detect line. + + + + + + + + + + + + + + + Defines a set of presence detect units + + + + + + + + + + + + + + Defines a presence detect master unit. (a gpio) + + + + + + + + + + + + + + + + + + + + + Defines a set of presence detect master units. + + + + + + + + + + + + + + Defines a PSI bus. + + + + + + + + + + + + + + + + Defines the PSI busses. + + + + + + + + + + + + + + Defines a PWM bus. + + + + + + + + + + + + + + + + Defines the PWM busses. + + + + + + + + + + + + + + Defines the PSI master unit characteristics of a part. + + + + + + + + + + + + + + + Defines a set of PSI master units. + + + + + + + + + + + + + + Defines the PSI unit characteristics of a part. + + + + + + + + + + + + + + + + Defines a set of PSI units. + + + + + + + + + + + + + + Defines the pwm-dac unit characteristics of a part. + + + + + + + + + + + + + + + + Defines a set of pwm-dac units. + + + + + + + + + + + + + + + Defines the pwm-master unit characteristics of a part. + + + + + + + + + + + + + + + + + Defines a set of pwm-master units. + + + + + + + + + + + + + + Defines the pwm-slave unit characteristics of a part. + + + + + + + + + + + + + + + Defines a set of pwm-slave units. + + + + + + + + + + + + + + Defines the ref-clockin unit characteristics of a part. + + + + + + + + + + + + + + + + Defines a set of ref-clockin units. + + + + + + + + + + + + + + + Defines an I2C slave unit. + + + + + + + + + + + + + + Defines a set of reference clock source units + + + + + + + + + + + + + + Defines a chip register + + + + + + + + + + + + + + + + + + Defines a set of chip registers + + + + + + + + + + + + + + + Defines a resistance value + + + + + + + + + + Identifies a variations to which a part-instance is restricted. + + + + + + + + + Defines a s16550 bus + + + + + + + + + + + + + + + + Defines a set of s16550 busses + + + + + + + + + + + + + + Defines an s16550 master unit. + + + + + + + + + + + + + + + + + + + + + Defines a set of s16550 master units. + + + + + + + + + + + + + + + Defines a SAS bus. + + + + + + + + + + + + + + + + Defines the SAS busses. + + + + + + + + + + + + + + Defines a SAS device unit. + + + + + + + + + + + + + + + Defines a set of SAS device units. + + + + + + + + + + + + + + + Defines a SAS master unit. + + + + + + + + + + + + + + Defines a set of SAS master units. + + + + + + + + + + + + + + Defines the SAS unit characteristics of a part. + + + + + + + + + + + + + + + Defines a set of SAS units. + + + + + + + + + + + + + + Defines smartchip bus + + + + + + + + + + + + + + + + + Defines a set of smartchip busses + + + + + + + + + + + + + + Defines a smartchip slave unit. + + + + + + + + + + + + + + + Defines a set of smartchip slave units. + + + + + + + + + + + + + + Defines a smartchip master unit. + + + + + + + + + + + + + + + + + + + + + Defines a set of smartchip master units. + + + + + + + + + + + + + + Defines a secondary PGOOD unit + + + + + + + + + + + + + + + + + + + + + Defines a set of secondary PGOOD units. + + + + + + + + + + + + + + Defines a group of related cards from which a particular one may + be configured. + + + + + + + + + + + + + + + Defines a used group of related cards from which a particular one may + be configured. + + + + + + + + + + + + + + + + + Defines the set of selection groups used in the containing element. + Selection groups represent groups of cards that can plug + into the same slot. + + + + + + + + + + + + + + Defines a sink for a power rail. + + + + + + + + + + + + + + + + Defines the source of a bus. + + + + + + + + + + + + + + + + + + Defines the spcn-master unit characteristics of a part. + + + + + + + + + + + + + + + + + + + + Defines a set of spcn-master units. + + + + + + + + + + + + + + The speed of a part or bus, in MHz. + + + + + + + + + Defines a SPI bus. + + + + + + + + + + + + + + + + Defines the SPI busses. + + + + + + + + + + + + + + Defines a SPCN uart bus. + + + + + + + + + + + + + + + + Defines the SPCN uart busses + + + + + + + + + + + + + + + Defines the spi-master unit characteristics of a part. + + + + + + + + + + + + + + + + + + Defines a set of spi-master units. + + + + + + + + + + + + + + Defines the spi-slave unit characteristics of a part. + + + + + + + + + + + + + + + + Defines a set of spi-slave units. + + + + + + + + + + + + + + Defines the 'station' parameter number of a PCIE switch. + + + + + + + + + + Defines a DIO bus used to connect to a tachometer + + + + + + + + + + + + + + + + Defines a set of tach busses + + + + + + + + + + + + + + Defines the tach-master unit characteristics of a part. + + + + + + + + + + + + + + + Defines a set of tach-master units. + + + + + + + + + + + + + + Defines the tach-slave unit characteristics of a part. + + + + + + + + + + + + + + + + + Defines a set of tach-slave units. + + + + + + + + + + + + + + + Defines the thermal properties of listed MTMs. + + + + + + + + + + + + + + Defines the thermal properties of the specified MTM. + + + + + + + + + + + + + + + + + The type of entity for which these properties apply. + + + + + + + + + + + + + + The ID (name, not the external-id) of the MTM for which these properties apply. + + + + + + + + + + Defines the thermal properties of the containing entity. + + + + + + + + + + + + + + + + + Defines a wire used to connect to a speaker. + + + + + + + + + + + + + + + + + + Defines a set of tone wires + + + + + + + + + + + + + + Defines the tone unit characteristics of a part. + + + + + + + + + + + + + + + + Defines a set of tone units. + + + + + + + + + + + + + + Defines a uart bus + + + + + + + + + + + + + + + + + Defines a set of uart busses + + + + + + + + + + + + + + Defines the uart-slave unit characteristics of a part. + + + + + + + + + + + + + + + + Defines a set of uart-slave units. + + + + + + + + + + + + + + Defines the units within a part. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Defines a USB bus + + + + + + + + + + + + + + + + Defines a set of USB busses + + + + + + + + + + + + + + Defines the usb device unit characteristics of a part. + + + + + + + + + + + + + + + Defines a set of USB device units. + + + + + + + + + + + + + + + Defines the usb-slave unit characteristics of a part. + + + + + + + + + + + + + + + + + Defines a set of USB master units. + + + + + + + + + + + + + + Field or lab-only use of a part. + + + + + + + + + + + + + + + If the bus should be used for FRU presence detect. In the case of I2c, it is via data line sensing. + + + + + + + + + + + + + + + Defines a variation which can each be referenced by ID in other elements. + + + + + + + + + + + + + + + Defines a set of variations which can each be referenced by ID in other elements. + + + + + + + + + + + + + + Defines the version of a chip, bus, standard, etc. + + + + + + + + + Defines a connector within a selection group. + + + + + + + + + + + + + + Defines a set of connectors within a selection group. + + + + + + + + + + + + + + The name of an HTML file containing supplemental documentation to be + included in the generated workbook. + + + + + + + + + Defines the XFI bus + + + + + + + + + + + + + + + + Defines a set of XFI master units. + + + + + + + + + + + + + + + + An XFI (ethernet) device unit + + + + + + + + + + + + + + + + + + + Defines a set of XFI device units. + + + + + + + + + + + + + + + + Defines the XFI master unit characteristics of a part. + + + + + + + + + + + + + + + Defines a set of XFI master units. + + + + + + + + + + + + + + + + + Defines the characteristics of a system. + This is the top-level element of a Machine Readable Workbook. + + + + + + + + + + + + + + + + + + + + diff --git a/xslt/mrwCecChips.xsl b/xslt/mrwCecChips.xsl new file mode 100644 index 0000000..68a07fe --- /dev/null +++ b/xslt/mrwCecChips.xsl @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CEC Chip Information + + +

CEC Chip Information

+
+
+ + + + + + + + + + + + + + + + + + +
TargetInstance PathScom PathScan PathMailbox Path
:n:p
+ +

+ + + + + + diff --git a/xslt/mrwCentVRDs.xsl b/xslt/mrwCentVRDs.xsl new file mode 100644 index 0000000..621d27b --- /dev/null +++ b/xslt/mrwCentVRDs.xsl @@ -0,0 +1,67 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Centaur VMEM Regulators + + +

Centaur VMEM Regulators

+
+
+ + + + + + + + + + + + + + +
TargetCentaurRegulator
n:p
+

+ + + + + diff --git a/xslt/mrwChipIDs.xsl b/xslt/mrwChipIDs.xsl new file mode 100644 index 0000000..0eb17ed --- /dev/null +++ b/xslt/mrwChipIDs.xsl @@ -0,0 +1,69 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Processor Logical Chip IDs + + +

Processor Logical Chip IDs

+
+
+ + + + + + + + + + + + + + + +
Logical NodeLogical PositionTargetInstance Path
n:p
+

+ + + + + + diff --git a/xslt/mrwDMIBusses.xsl b/xslt/mrwDMIBusses.xsl new file mode 100644 index 0000000..c2fddda --- /dev/null +++ b/xslt/mrwDMIBusses.xsl @@ -0,0 +1,79 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DMI Bus Swap Information + + +

DMI Bus Swap Information

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
MCSTargetCentaurTargetMaster Chip TX_MSBSWAP (Downstream Dir)Slave Chip TX_MSBSWAP (Upstream Dir)Master Chip TX_LANE_INVERT (Downstream Dir)Slave Chip TX_LANE_INVERT (Upstream Dir)MCS Refclock Enable Mapping (DMI_REFCLOCK_SWIZZLE)
n:p:mcsn:p
+

+ + + + + diff --git a/xslt/mrwFSIBusses.xsl b/xslt/mrwFSIBusses.xsl new file mode 100644 index 0000000..b322ad0 --- /dev/null +++ b/xslt/mrwFSIBusses.xsl @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FSI Connections + + +

FSI Connections

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MasterTargetTypeEngineLinkSlavePortTarget
n:pnan:pna
+

+ + + + + + diff --git a/xslt/mrwI2CBusses.xsl b/xslt/mrwI2CBusses.xsl new file mode 100644 index 0000000..95f0db9 --- /dev/null +++ b/xslt/mrwI2CBusses.xsl @@ -0,0 +1,335 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + I2C Devices + + +

I2C Devices

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
I2C SlaveI2C MasterEnginePortAddressDetails
+ +
Restrict-to: + + 		<a href="#i2c">Details</a>
+



+ + + + + + <a name="i2c"></a> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
I2C Device
+ +
+ Device + + +
+ Part Type + + +
+ Card + + () +
+ Instance Path + + +
+ Address + + +
+ Speed + + +
Content
Device Size
+
+ I2C Master +
+
+ Device + + +
I2C Engine
I2C Port
+ Part Type + + +
+ Card + + () +
+ Instance Path + + +
FSP Path Information
+
+ + + + + + + + + + + +
FSI Path
Firmware Device Path:
+ + + + + + + + + + + + + + + + + + +
FSI Path Segment
Master: (Link )
Card: ()
Slave: (port )
+
+
+
FSP Path Information
Firmware Device Path:
+
+
+ +

+ + + + + + + + Target + + + :n:p + + + + + + + +
+ + + + + +
+ + + + + + + + + + + + + + + + + + + + +
I2C Path
Master: + +
Card: + () +
Slave: + +
+
+
+ + + + + + diff --git a/xslt/mrwMemoryBusses.xsl b/xslt/mrwMemoryBusses.xsl new file mode 100644 index 0000000..cd81b28 --- /dev/null +++ b/xslt/mrwMemoryBusses.xsl @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Memory Bus Connections + + +

Memory Bus Connections

+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Processor MCS TargetCentaur MBA TargetMBA PortMBA SlotCentaur TargetDIMM TargetDIMM Instance PathProc->Centaur FSI Link
+ n:p:mcs + + n:p:mba + + n:p + + n:p +
+

+ + + + + diff --git a/xslt/mrwMruIds.xsl b/xslt/mrwMruIds.xsl new file mode 100644 index 0000000..c27d77f --- /dev/null +++ b/xslt/mrwMruIds.xsl @@ -0,0 +1,105 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MRU IDs + + +

MRU IDs

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MRU IDMRU ID ValueInstance PathLocation CodeHW IDHW TypeMRU TypeMRU Instance#Parent MRUecmd Target
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; + + Part: &nbsp; + + + Card: &nbsp; + + + Unit: &nbsp; + + + Chiplet: &nbsp; + + &nbsp;&nbsp;&nbsp;&nbsp;
+

+ + + + + + diff --git a/xslt/mrwPCIEBusses.xsl b/xslt/mrwPCIEBusses.xsl new file mode 100644 index 0000000..4d2b55e --- /dev/null +++ b/xslt/mrwPCIEBusses.xsl @@ -0,0 +1,328 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PCIE Connections + + +

PCIE Connections

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SourceIOPWidthSwitchEndpointDetails
(Station: Port: )None<a href="#dev">Details</a>
+



+ + + + + + <a name="dev"></a> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Source
+ Processor + n:p
+ Instance Path +
+ IOP +
+ Lane Mask +
+ DSMP Capable +
+ Lane Swap Bits +
+ Lane Reversal Bits +
+ Lane Swap Bits if Bifurcated + + Lanes = + , + Lanes = + +
+ Lane Reversal Bits if Bifurcated + + Lanes = + , + Lanes = + +
Switch
+ Part +
+ Station +
+ Port +
+ Upstream Station +
+ Upstream Port +
+ Instance Path +
Endpoint
+ Card +
+ Part +
+ Instance Path +
+ Width +
+ Slot Index +
+ Card Size +
+ Gen +
+ Hot Plug +
+ Is Slot +
+ CAPI +
+ LSI +
+ Default Cooling Type +
+ Default Power Consumption + Watts
+
+
+ +

+ + + + + + diff --git a/xslt/mrwPowerBusses.xsl b/xslt/mrwPowerBusses.xsl new file mode 100644 index 0000000..39aeecf --- /dev/null +++ b/xslt/mrwPowerBusses.xsl @@ -0,0 +1,191 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PowerBus Connections + + +

PowerBus Connections

+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EndpointEndpoint
+ Port + + +
+ Chip Target + np
+ Location Code + + +
+ Instance Path + + +
+ RX Upstream MSB Swap + + +
+ TX Downstream MSB Swap + + +
+ Downstream TX_LANE_INVERT + + +
+ Upstream TX_LANE_INVERT + + +
+ Bus Width + + B +
+ Node Config + + +
+
+
+ + + + +

+ + + + + diff --git a/xslt/mrwTargets.xsl b/xslt/mrwTargets.xsl new file mode 100644 index 0000000..5700b1d --- /dev/null +++ b/xslt/mrwTargets.xsl @@ -0,0 +1,83 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ecmd Targets + + +

ecmd Targets

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ecmd
Common
Name		NodePositionUnitInstance PathDescription
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
+

+ + + + + -- cgit v1.2.1 From 74b089d759cc0948fb38674bd4dfe42d0841c011 Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Thu, 14 Aug 2014 12:58:29 -0500 Subject: Update permissions --- CENTAUR.xml | 24 ++++++++++++++++++++++++ DDR3_DRAM_ABSTRACT.xml | 24 ++++++++++++++++++++++++ DIMM_SPD.xml | 24 ++++++++++++++++++++++++ LANCER_B0.xml | 24 ++++++++++++++++++++++++ MOD_SEEPROM_512.xml | 24 ++++++++++++++++++++++++ PCA9538.xml | 24 ++++++++++++++++++++++++ PCIE_X16_ABSTRACT.xml | 24 ++++++++++++++++++++++++ PCIE_X8_ABSTRACT.xml | 24 ++++++++++++++++++++++++ PEX8718_PALMETTO.xml | 24 ++++++++++++++++++++++++ PGOOD_LAYERBRIDGE.xml | 24 ++++++++++++++++++++++++ TULETA_FSP2.xml | 24 ++++++++++++++++++++++++ TUSB7340.xml | 24 ++++++++++++++++++++++++ VENICE.xml | 24 ++++++++++++++++++++++++ VRD_NOI2C.xml | 24 ++++++++++++++++++++++++ ddr3_dimm_generic.xml | 24 ++++++++++++++++++++++++ mru-type-mapping.xml | 24 ++++++++++++++++++++++++ pcie_x16_card.xml | 24 ++++++++++++++++++++++++ pcie_x8_card.xml | 24 ++++++++++++++++++++++++ turismo_scm.xml | 24 ++++++++++++++++++++++++ 19 files changed, 456 insertions(+) diff --git a/CENTAUR.xml b/CENTAUR.xml index 4a73df2..84fbbb5 100644 --- a/CENTAUR.xml +++ b/CENTAUR.xml @@ -1,3 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/TUSB7340.xml b/TUSB7340.xml index 1a25548..9e35417 100644 --- a/TUSB7340.xml +++ b/TUSB7340.xml @@ -1,3 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/mru-type-mapping.xml b/mru-type-mapping.xml index ef7940e..9300aeb 100644 --- a/mru-type-mapping.xml +++ b/mru-type-mapping.xml @@ -1,3 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pcie_x8_card.xml b/pcie_x8_card.xml index e94f6a6..3697a67 100644 --- a/pcie_x8_card.xml +++ b/pcie_x8_card.xml @@ -1,3 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/turismo_scm.xml b/turismo_scm.xml index b031126..f693029 100644 --- a/turismo_scm.xml +++ b/turismo_scm.xml @@ -1,3 +1,27 @@ + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.1 From 1d823401e9315bba4ce94b2aaeb4c25d073f3bd2 Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Thu, 14 Aug 2014 13:19:11 -0500 Subject: Move XML declaration to top --- CENTAUR.xml | 4 ++-- DDR3_DRAM_ABSTRACT.xml | 4 ++-- DIMM_SPD.xml | 4 ++-- LANCER_B0.xml | 12 ++++++------ MOD_SEEPROM_512.xml | 2 +- PCA9538.xml | 4 ++-- PCIE_X16_ABSTRACT.xml | 4 ++-- PCIE_X8_ABSTRACT.xml | 4 ++-- PEX8718_PALMETTO.xml | 2 +- PGOOD_LAYERBRIDGE.xml | 6 +++--- TULETA_FSP2.xml | 8 ++++---- TUSB7340.xml | 4 ++-- VENICE.xml | 38 +++++++++++++++++++------------------- VRD_NOI2C.xml | 4 ++-- ddr3_dimm_generic.xml | 2 +- mru-type-mapping.xml | 2 +- pcie_x16_card.xml | 2 +- pcie_x8_card.xml | 2 +- schema/mrw.xsd | 2 +- turismo_scm.xml | 2 +- xslt/mrwCecChips.xsl | 2 +- xslt/mrwCentVRDs.xsl | 8 ++++---- xslt/mrwChipIDs.xsl | 2 +- xslt/mrwDMIBusses.xsl | 8 ++++---- xslt/mrwFSIBusses.xsl | 2 +- xslt/mrwI2CBusses.xsl | 2 +- xslt/mrwMemoryBusses.xsl | 2 +- xslt/mrwMruIds.xsl | 3 +-- xslt/mrwPCIEBusses.xsl | 2 +- xslt/mrwPowerBusses.xsl | 8 ++++---- xslt/mrwTargets.xsl | 2 +- 31 files changed, 76 insertions(+), 77 deletions(-) diff --git a/CENTAUR.xml b/CENTAUR.xml index 84fbbb5..9de00a1 100644 --- a/CENTAUR.xml +++ b/CENTAUR.xml @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - port1 port2 port3 - + mba23mba1 port0 port1 diff --git a/DDR3_DRAM_ABSTRACT.xml b/DDR3_DRAM_ABSTRACT.xml index cea43b2..8f97321 100644 --- a/DDR3_DRAM_ABSTRACT.xml +++ b/DDR3_DRAM_ABSTRACT.xml @@ -1,3 +1,4 @@ + @@ -22,13 +23,12 @@ - - + DDR3_DRAM_ABSTRACT chip diff --git a/DIMM_SPD.xml b/DIMM_SPD.xml index acef8c3..15752a8 100644 --- a/DIMM_SPD.xml +++ b/DIMM_SPD.xml @@ -1,3 +1,4 @@ + @@ -22,13 +23,12 @@ - - + DIMM_SPD chip diff --git a/LANCER_B0.xml b/LANCER_B0.xml index 77f5bc2..df5b606 100644 --- a/LANCER_B0.xml +++ b/LANCER_B0.xml @@ -1,3 +1,4 @@ + @@ -22,13 +23,12 @@ - - + LANCER_B0 chip @@ -52,28 +52,28 @@ 0.9 0.01 0.02 - + 1.2V VLOGIC 1.2 0.01 0.02 - + 1.8V VIO 1.8 0.01 0.02 - + 3.3V VCC 3.3 0.01 0.02 - + diff --git a/MOD_SEEPROM_512.xml b/MOD_SEEPROM_512.xml index 34521b3..3e6f720 100644 --- a/MOD_SEEPROM_512.xml +++ b/MOD_SEEPROM_512.xml @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - @@ -22,13 +23,12 @@ - - + PCA9538 chip diff --git a/PCIE_X16_ABSTRACT.xml b/PCIE_X16_ABSTRACT.xml index 1b6db8c..bc14f14 100644 --- a/PCIE_X16_ABSTRACT.xml +++ b/PCIE_X16_ABSTRACT.xml @@ -1,3 +1,4 @@ + @@ -22,13 +23,12 @@ - - + PCIE_X16_ABSTRACT blackbox diff --git a/PCIE_X8_ABSTRACT.xml b/PCIE_X8_ABSTRACT.xml index 49bec8a..1fcdb20 100644 --- a/PCIE_X8_ABSTRACT.xml +++ b/PCIE_X8_ABSTRACT.xml @@ -1,3 +1,4 @@ + @@ -22,13 +23,12 @@ - - + PCIE_X8_ABSTRACT blackbox diff --git a/PEX8718_PALMETTO.xml b/PEX8718_PALMETTO.xml index 541d412..6f512d4 100644 --- a/PEX8718_PALMETTO.xml +++ b/PEX8718_PALMETTO.xml @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - @@ -22,7 +23,6 @@ - PGOOD - + - \ No newline at end of file + diff --git a/TULETA_FSP2.xml b/TULETA_FSP2.xml index aa81dc4..d9a2fc1 100644 --- a/TULETA_FSP2.xml +++ b/TULETA_FSP2.xml @@ -1,3 +1,4 @@ + @@ -22,14 +23,13 @@ - - + TULETA_FSP2 chip @@ -2303,7 +2303,7 @@ - + - \ No newline at end of file + diff --git a/TUSB7340.xml b/TUSB7340.xml index 9e35417..404d173 100644 --- a/TUSB7340.xml +++ b/TUSB7340.xml @@ -1,3 +1,4 @@ + @@ -22,13 +23,12 @@ - - + TUSB7340 chip diff --git a/VENICE.xml b/VENICE.xml index edff857..e68e3b1 100644 --- a/VENICE.xml +++ b/VENICE.xml @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - mcs1mcs1 mcs2mcs2 mcs3mcs3 - + mc1 mcs4mcs4 mcs5mcs5 mcs6mcs6 mcs7mcs7 - + @@ -96,7 +96,7 @@ OSC0_TOD_REFCLKtod0 OSC1_CHIP_REFCLKproc1 OSC1_PCIE_REFCLKpcie1 - OSC1_TOD_REFCLKtod1 + OSC1_TOD_REFCLKtod1 @@ -113,7 +113,7 @@ I2CM_PROC_PROM101 I2CM_HOTPLUG11 I2CM_LIGHTPATH10 - + OSC0_OSCSW_CTL0 OSC0_OSCSW_CTL1 @@ -128,9 +128,9 @@ SPISPI - + - PSI + PSI FSI_SLAVE00 @@ -163,7 +163,7 @@ MFSI5135cfam0 MFSI6136cfam0 MFSI7137cfam0 - + LPC @@ -171,19 +171,19 @@ A0A A1A - A2A + A2A X0X X1X X2X - X3X + X3X PCIE_IOP000 PCIE_IOP0_108 PCIE_IOP110 - + + - DMI0mcs0 DMI1mcs1 @@ -229,7 +229,7 @@ 1.5 2 1 - + @@ -289,7 +289,7 @@ - + yes 32 @@ -297,7 +297,7 @@ 128 4-way - + yes 64 @@ -305,7 +305,7 @@ 128 8-way - + yes 512 @@ -313,7 +313,7 @@ 128 8-way - + yes 512 @@ -321,7 +321,7 @@ 128 8-way - + 8 512 @@ -339,7 +339,7 @@ no 8 - + diff --git a/VRD_NOI2C.xml b/VRD_NOI2C.xml index c7bd9cf..ce9a52a 100644 --- a/VRD_NOI2C.xml +++ b/VRD_NOI2C.xml @@ -1,3 +1,4 @@ + @@ -22,13 +23,12 @@ - - + VRD_NOI2C vrd diff --git a/ddr3_dimm_generic.xml b/ddr3_dimm_generic.xml index 7d9d822..c7b7f02 100644 --- a/ddr3_dimm_generic.xml +++ b/ddr3_dimm_generic.xml @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - ddr3_dimm_generic diff --git a/mru-type-mapping.xml b/mru-type-mapping.xml index 9300aeb..ec69f7b 100644 --- a/mru-type-mapping.xml +++ b/mru-type-mapping.xml @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - @@ -22,7 +23,6 @@ - pcie_x16_card diff --git a/pcie_x8_card.xml b/pcie_x8_card.xml index 3697a67..9d84b61 100644 --- a/pcie_x8_card.xml +++ b/pcie_x8_card.xml @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - pcie_x8_card diff --git a/schema/mrw.xsd b/schema/mrw.xsd index 1afd4c8..c25bc0e 100644 --- a/schema/mrw.xsd +++ b/schema/mrw.xsd @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - @@ -22,7 +23,6 @@ - turismo_scm diff --git a/xslt/mrwCecChips.xsl b/xslt/mrwCecChips.xsl index 68a07fe..94f87d0 100644 --- a/xslt/mrwCecChips.xsl +++ b/xslt/mrwCecChips.xsl @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - @@ -22,12 +23,11 @@ - - @@ -44,7 +44,7 @@

Centaur VMEM Regulators



- + diff --git a/xslt/mrwChipIDs.xsl b/xslt/mrwChipIDs.xsl index 0eb17ed..e6830b2 100644 --- a/xslt/mrwChipIDs.xsl +++ b/xslt/mrwChipIDs.xsl @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - @@ -22,12 +23,11 @@ - - @@ -44,7 +44,7 @@

DMI Bus Swap Information



- +
Target
diff --git a/xslt/mrwFSIBusses.xsl b/xslt/mrwFSIBusses.xsl index b322ad0..59fb9ec 100644 --- a/xslt/mrwFSIBusses.xsl +++ b/xslt/mrwFSIBusses.xsl @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - @@ -22,7 +23,6 @@ - @@ -22,7 +23,6 @@ - @@ -22,7 +23,6 @@ - - diff --git a/xslt/mrwPCIEBusses.xsl b/xslt/mrwPCIEBusses.xsl index 4d2b55e..fa9346a 100644 --- a/xslt/mrwPCIEBusses.xsl +++ b/xslt/mrwPCIEBusses.xsl @@ -1,3 +1,4 @@ + @@ -22,7 +23,6 @@ - @@ -22,12 +23,11 @@ - - @@ -154,7 +154,7 @@ - @@ -22,7 +23,6 @@ - Date: Fri, 5 Sep 2014 06:52:47 -0500 Subject: Centaur/Venice renamed for OpenPOWER --- CENTAUR.xml | 164 ------------------------- OPNPWR_CENTAUR.xml | 140 +++++++++++++++++++++ OPNPWR_VENICE.xml | 323 +++++++++++++++++++++++++++++++++++++++++++++++++ VENICE.xml | 347 ----------------------------------------------------- 4 files changed, 463 insertions(+), 511 deletions(-) delete mode 100644 CENTAUR.xml create mode 100644 OPNPWR_CENTAUR.xml create mode 100644 OPNPWR_VENICE.xml delete mode 100644 VENICE.xml diff --git a/CENTAUR.xml b/CENTAUR.xml deleted file mode 100644 index 9de00a1..0000000 --- a/CENTAUR.xml +++ /dev/null @@ -1,164 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CENTAUR - chip - DD1 - membuf - yes - - mba01mba0 - port0 - port1 - port2 - port3 - - mba23mba1 - port0 - port1 - port2 - port3 - - - - L4L40 - - - - - I2CMASTER_DIMMS0 - 6 - 0 - SDA_M0 - I2C Master for DIMMs - - - I2CSPR_DIMMS0 - 6 - 1 - SDA_M0 - I2C SPR for DIMMs - - - - FSI_SLAVE00 - FSI_SLAVE11 - - - GPIO_PORT070 - - - DDR3_CH0_SLOT000mba01 - DDR3_CH0_SLOT101mba01 - DDR3_CH1_SLOT000mba23 - DDR3_CH1_SLOT101mba23 - DDR3_CH2_SLOT010mba01 - DDR3_CH2_SLOT111mba01 - DDR3_CH3_SLOT010mba23 - DDR3_CH3_SLOT111mba23 - - - DMI - - - - VMEM - VMEM - 1.35 - 10 - 12 - - - VPP - VPP - 2.5 - 3 - 4 - - - VCACHE - VCACHE - 1.035 - 18 - 21 - - - VCORE - VCORE - 0.9 - 18 - 21 - - - AVDD - AVDD - 0.9 - 18 - 21 - - - - - - - - - - shift - 3 - - - fsi2pib - 4 - - - scratchpad - 5 - - - i2cm - 6 - - - gpio - 7 - - - fsi2pib2 - 8 - - - - - - - diff --git a/OPNPWR_CENTAUR.xml b/OPNPWR_CENTAUR.xml new file mode 100644 index 0000000..3ca6f0f --- /dev/null +++ b/OPNPWR_CENTAUR.xml @@ -0,0 +1,140 @@ + + + + + + OPNPWR_CENTAUR + chip + DD1 + membuf + yes + + mba01mba0 + port0 + port1 + port2 + port3 + + mba23mba1 + port0 + port1 + port2 + port3 + + + + L4L40 + + + + + I2CMASTER_DIMMS0 + 6 + 0 + SDA_M0 + I2C Master for DIMMs + + + I2CSPR_DIMMS0 + 6 + 1 + SDA_M0 + I2C SPR for DIMMs + + + + FSI_SLAVE00 + FSI_SLAVE11 + + + GPIO_PORT070 + + + DDR3_PORTA_SLOT000mba01 + DDR3_PORTA_SLOT101mba01 + DDR3_PORTC_SLOT000mba23 + DDR3_PORTC_SLOT101mba23 + DDR3_PORTB_SLOT010mba01 + DDR3_PORTB_SLOT111mba01 + DDR3_PORTD_SLOT010mba23 + DDR3_PORTD_SLOT111mba23 + + + DMI + + + + VMEM + VMEM + 1.35 + 10 + 12 + + + VPP + VPP + 2.5 + 3 + 4 + + + VCACHE + VCACHE + 1.035 + 18 + 21 + + + VCORE + VCORE + 0.9 + 18 + 21 + + + AVDD + AVDD + 0.9 + 18 + 21 + + + + + + + + + + shift + 3 + + + fsi2pib + 4 + + + scratchpad + 5 + + + i2cm + 6 + + + gpio + 7 + + + fsi2pib2 + 8 + + + + + + + diff --git a/OPNPWR_VENICE.xml b/OPNPWR_VENICE.xml new file mode 100644 index 0000000..d6a239e --- /dev/null +++ b/OPNPWR_VENICE.xml @@ -0,0 +1,323 @@ + + + + + + OPNPWR_VENICE + chip + DD1 + cpu + IBM Power8 + yes + + ex1ex1 + core1core1 + + ex2ex2 + core2core2 + + ex3ex3 + core3core3 + + ex4ex4 + core4core4 + + ex5ex5 + core5core5 + + ex6ex6 + core6core6 + + ex9ex9 + core9core9 + + ex10ex10 + core10core10 + + ex11ex11 + core11core11 + + ex12ex12 + core12core12 + + ex13ex13 + core13core13 + + ex14ex14 + core14core14 + + occocc0 + nxnx0 + porepore0 + mc0 + mcs0mcs0 + mcs1mcs1 + mcs2mcs2 + mcs3mcs3 + + mc1 + mcs4mcs4 + mcs5mcs5 + mcs6mcs6 + mcs7mcs7 + + + + + OSC0_CHIP_REFCLKproc0 + OSC0_PCIE_REFCLKpcie0 + OSC0_TOD_REFCLKtod0 + OSC1_CHIP_REFCLKproc1 + OSC1_PCIE_REFCLKpcie1 + OSC1_TOD_REFCLKtod1 + + + + I2C0 + SDA0 + + I2C Slave for BMC connection + + + + I2CM_PROM60cfam0 + I2CM_PROC_PROM00 + I2CM_PROM161cfam0 + I2CM_PROC_PROM101 + I2CM_HOTPLUG11 + I2CM_LIGHTPATH10 + + + OSC0_OSCSW_CTL0 + OSC0_OSCSW_CTL1 + OSC1_OSCSW_CTL0 + OSC1_OSCSW_CTL1 + + + OSC0_USE_OSC0 + OSC0_USE_OSC1 + OSC1_USE_OSC0 + OSC1_USE_OSC1 + + + SPISPI + + + PSI + + + FSI_SLAVE00 + FSI_SLAVE11 + + + FSI_CASCADE0 0120cfam0 + FSI_CASCADE1 0121cfam0 + FSI_CASCADE2 0122cfam0 + FSI_CASCADE3 0123cfam0 + FSI_CASCADE4 0124cfam0 + FSI_CASCADE5 0125cfam0 + FSI_CASCADE6 0126cfam0 + FSI_CASCADE7 0127cfam0 + FSI_CASCADE8 1120cfam0 + FSI_CASCADE9 1121cfam0 + FSI_CASCADE101122cfam0 + FSI_CASCADE111123cfam0 + FSI_CASCADE121124cfam0 + FSI_CASCADE131125cfam0 + FSI_CASCADE141126cfam0 + FSI_CASCADE151127cfam0 + + + MFSI0130cfam0 + MFSI1131cfam0 + MFSI2132cfam0 + MFSI3133cfam0 + MFSI4134cfam0 + MFSI5135cfam0 + MFSI6136cfam0 + MFSI7137cfam0 + + + + LPC + + + A0A + A1A + A2A + X0X + X1X + X2X + X3X + + + PCIE_IOP000 + PCIE_IOP0_108 + PCIE_IOP110 + + + + + DMI_M0Dmcs0 + DMI_M0Cmcs1 + DMI_M0Amcs2 + DMI_M0Bmcs3 + DMI_M1Dmcs4 + DMI_M1Cmcs5 + DMI_M1Amcs6 + DMI_M1Bmcs7 + + + + VDD0 + VDD0 + 1.0 + 180 + 212 + + + VCS0 + VCS + 1.05 + 18 + 21 + + + VIO + VIO + 1.05 + 18 + 21 + + + VPCI + VPCI + 1.2 + 5 + 3 + + + AVDD + AVDD + 1.5 + 2 + 1 + + + + + + + + + + PHB00 + PHB11 + PHB22 + + + + + + shift + 3 + + + + fsi2pib + 4 + + + + scratchpad + 5 + + + + i2cm + 6 + + + + mailbox + 10 + + + + cMFSI + 12 + + + + MFSI + 13 + + + + + + cfam0 + + + + + + + + yes + 32 + 128 + 128 + 4-way + + + + yes + 64 + 128 + 128 + 8-way + + + + yes + 512 + 128 + 128 + 8-way + + + + yes + 512 + 128 + 128 + 8-way + + + + 8 + 512 + 4 + 512 + 4 + 128 + no + no + no + no + no + yes + no + no + 8 + + + + + + + diff --git a/VENICE.xml b/VENICE.xml deleted file mode 100644 index e68e3b1..0000000 --- a/VENICE.xml +++ /dev/null @@ -1,347 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VENICE - chip - DD1 - cpu - IBM Power8 - yes - - ex1ex1 - core1core1 - - ex2ex2 - core2core2 - - ex3ex3 - core3core3 - - ex4ex4 - core4core4 - - ex5ex5 - core5core5 - - ex6ex6 - core6core6 - - ex9ex9 - core9core9 - - ex10ex10 - core10core10 - - ex11ex11 - core11core11 - - ex12ex12 - core12core12 - - ex13ex13 - core13core13 - - ex14ex14 - core14core14 - - occocc0 - nxnx0 - porepore0 - mc0 - mcs0mcs0 - mcs1mcs1 - mcs2mcs2 - mcs3mcs3 - - mc1 - mcs4mcs4 - mcs5mcs5 - mcs6mcs6 - mcs7mcs7 - - - - - OSC0_CHIP_REFCLKproc0 - OSC0_PCIE_REFCLKpcie0 - OSC0_TOD_REFCLKtod0 - OSC1_CHIP_REFCLKproc1 - OSC1_PCIE_REFCLKpcie1 - OSC1_TOD_REFCLKtod1 - - - - I2C0 - SDA0 - - I2C Slave for BMC connection - - - - I2CM_PROM60cfam0 - I2CM_PROC_PROM00 - I2CM_PROM161cfam0 - I2CM_PROC_PROM101 - I2CM_HOTPLUG11 - I2CM_LIGHTPATH10 - - - OSC0_OSCSW_CTL0 - OSC0_OSCSW_CTL1 - OSC1_OSCSW_CTL0 - OSC1_OSCSW_CTL1 - - - OSC0_USE_OSC0 - OSC0_USE_OSC1 - OSC1_USE_OSC0 - OSC1_USE_OSC1 - - - SPISPI - - - PSI - - - FSI_SLAVE00 - FSI_SLAVE11 - - - FSI_CASCADE0 0120cfam0 - FSI_CASCADE1 0121cfam0 - FSI_CASCADE2 0122cfam0 - FSI_CASCADE3 0123cfam0 - FSI_CASCADE4 0124cfam0 - FSI_CASCADE5 0125cfam0 - FSI_CASCADE6 0126cfam0 - FSI_CASCADE7 0127cfam0 - FSI_CASCADE8 1120cfam0 - FSI_CASCADE9 1121cfam0 - FSI_CASCADE101122cfam0 - FSI_CASCADE111123cfam0 - FSI_CASCADE121124cfam0 - FSI_CASCADE131125cfam0 - FSI_CASCADE141126cfam0 - FSI_CASCADE151127cfam0 - - - MFSI0130cfam0 - MFSI1131cfam0 - MFSI2132cfam0 - MFSI3133cfam0 - MFSI4134cfam0 - MFSI5135cfam0 - MFSI6136cfam0 - MFSI7137cfam0 - - - - LPC - - - A0A - A1A - A2A - X0X - X1X - X2X - X3X - - - PCIE_IOP000 - PCIE_IOP0_108 - PCIE_IOP110 - - - - - DMI0mcs0 - DMI1mcs1 - DMI2mcs2 - DMI3mcs3 - DMI4mcs4 - DMI5mcs5 - DMI6mcs6 - DMI7mcs7 - - - - VDD0 - VDD0 - 1.0 - 180 - 212 - - - VCS0 - VCS - 1.05 - 18 - 21 - - - VIO - VIO - 1.05 - 18 - 21 - - - VPCI - VPCI - 1.2 - 5 - 3 - - - AVDD - AVDD - 1.5 - 2 - 1 - - - - - - - - - - PHB00 - PHB11 - PHB22 - - - - - - shift - 3 - - - - fsi2pib - 4 - - - - scratchpad - 5 - - - - i2cm - 6 - - - - mailbox - 10 - - - - cMFSI - 12 - - - - MFSI - 13 - - - - - - cfam0 - - - - - - - - yes - 32 - 128 - 128 - 4-way - - - - yes - 64 - 128 - 128 - 8-way - - - - yes - 512 - 128 - 128 - 8-way - - - - yes - 512 - 128 - 128 - 8-way - - - - 8 - 512 - 4 - 512 - 4 - 128 - no - no - no - no - no - yes - no - no - 8 - - - - - - - -- cgit v1.2.1 From 31f4f39cfd990028538e152b5da69b5af2c0a44c Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Mon, 15 Sep 2014 06:57:41 -0500 Subject: New turismo_scm.xml --- turismo_scm.xml | 174 ++++++++++++++++++++++++-------------------------------- 1 file changed, 75 insertions(+), 99 deletions(-) diff --git a/turismo_scm.xml b/turismo_scm.xml index fe697b2..70cb8ef 100644 --- a/turismo_scm.xml +++ b/turismo_scm.xml @@ -1,47 +1,23 @@ - - - - - - - - - - - - - - - - - - - - - - - - - + turismo_scm scm-module - VENICEDD1 MOD_SEEPROM_512 + OPNPWR_VENICEDD1 TURISMO_SOCKET - U0VENICE0yesIBM Power8DD1 - U2MOD_SEEPROM_5120PRIMARY_SBE_VPD225624c512512 - U1MOD_SEEPROM_5121PRIMARY_FRU_AND_MODULE_VPD225624c512512 - U3MOD_SEEPROM_5122REDUNDANT_FRU_AND_MODULE_VPD225624c512512 - U4MOD_SEEPROM_5123REDUNDANT_SBE_VPD225624c512512 + U0OPNPWR_VENICE0yesDD1IBM Power8 + U2MOD_SEEPROM_5120PRIMARY_SBE_VPD225651224c512 + U1MOD_SEEPROM_5121PRIMARY_FRU_AND_MODULE_VPD225651224c512 + U3MOD_SEEPROM_5122REDUNDANT_FRU_AND_MODULE_VPD225651224c512 + U4MOD_SEEPROM_5123REDUNDANT_SBE_VPD225651224c512 JBSMTURISMO_SOCKET0 @@ -49,31 +25,31 @@ - dmi11 - U0DMI7 - JBSMDMI3 + dmi14 + U0DMI_M1D + JBSMDMI_M1D - dmi5 - U0DMI2 - JBSMDMI0 + dmi8 + U0DMI_M0C + JBSMDMI_M0C - dmi2 - U0DMI0 - JBSMDMI1 + dmi11 + U0DMI_M0D + JBSMDMI_M0D - dmi8 - U0DMI1 - JBSMDMI2 + dmi17 + U0DMI_M1C + JBSMDMI_M1C - clock20 - U0OSC0_TOD_REFCLK - JBSMOSC0_TOD_REFCLK + clock2 + U0OSC0_CHIP_REFCLK + JBSMLPC_CLK clock17 @@ -81,9 +57,9 @@ JBSMOSC0_PCIE_REFCLK - clock2 - U0OSC0_CHIP_REFCLK - JBSMLPC_CLK + clock20 + U0OSC0_TOD_REFCLK + JBSMOSC0_TOD_REFCLK @@ -108,22 +84,22 @@ - - pcie5 - U0PCIE_IOP1 - JBSMPCIE1 - pcie2 U0PCIE_IOP0 JBSMPCIE0 + + pcie5 + U0PCIE_IOP1 + JBSMPCIE1 + - power155 - U0VDD0 - JBSMVDD + power152 + U0VCS0 + JBSMVCS power149 @@ -131,9 +107,9 @@ JBSMVIO - power152 - U0VCS0 - JBSMVCS + power155 + U0VDD0 + JBSMVDD power146 @@ -150,8 +126,8 @@ i2c11 No -
A0
400 +
A0
U0I2CM_PROM1 U3I2C @@ -163,53 +139,63 @@ i2c2 No -
0xA0
400 +
0xA0
U1I2C U0I2CM_PROM + + i2c128 + U0I2CM_HOTPLUG + JBSMI2C_HOTPLUG + i2c8 No -
A2
400 +
A2
U0I2CM_PROM1 U4I2C i2c5 No -
A2
400 +
A2
U0I2CM_PROM U2I2C - - i2c128 - U0I2CM_HOTPLUG - JBSMI2C_HOTPLUG - + + fsi62 + U0FSI_CASCADE2 + JBSMFSI0_CENT2 + + + fsi2 + U0MFSI3 + JBSMMFSI3 + fsi65 U0FSI_CASCADE3 JBSMFSI0_CENT3 + + fsi77 + U0FSI_CASCADE7 + JBSMFSI0_CENT7 + fsi74 U0FSI_CASCADE6 JBSMFSI0_CENT6 - fsi2 - U0MFSI3 - JBSMMFSI3 - - - fsi62 - U0FSI_CASCADE2 - JBSMFSI0_CENT2 + fsi59 + U0FSI_CASCADE1 + JBSMFSI0_CENT1 fsi113 @@ -221,57 +207,47 @@ U0FSI_CASCADE0 JBSMFSI0_CENT0 - - fsi110 - U0MFSI1 - JBSMMFSI1 - - - fsi77 - U0FSI_CASCADE7 - JBSMFSI0_CENT7 - fsi116 U0FSI_SLAVE0 JBSMFSI_A - fsi59 - U0FSI_CASCADE1 - JBSMFSI0_CENT1 + fsi110 + U0MFSI1 + JBSMMFSI1 - powerbus53 + powerbus47 No 0x00000000 No 2 0x00000000 - U0A0 - JBSMA0 + U0A2 + JBSMA2 - powerbus47 + powerbus50 No 0x00000000 No 2 0x00000000 - U0A2 - JBSMA2 + U0A1 + JBSMA1 - powerbus50 + powerbus53 No 0x00000000 No 2 0x00000000 - U0A1 - JBSMA1 + U0A0 + JBSMA0 -- cgit v1.2.1 From cb1a389b34ef2506c84bdf51d16091d0e5b2772b Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Mon, 15 Sep 2014 06:59:54 -0500 Subject: Move PEX8718_PALMETTO.xml to palmetto-xml --- PEX8718_PALMETTO.xml | 74 ---------------------------------------------------- 1 file changed, 74 deletions(-) delete mode 100644 PEX8718_PALMETTO.xml diff --git a/PEX8718_PALMETTO.xml b/PEX8718_PALMETTO.xml deleted file mode 100644 index 6f512d4..0000000 --- a/PEX8718_PALMETTO.xml +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PEX8718_PALMETTO - chip - pcie-switch - x0pxxxx - PLX 18 lane PCIe Gen3 Switch - - - I2CSDA - - - INBOUND_X8OUT800 - - - RESETRESET - - - S0_X2IN200 - S1_X2IN211 - S2_X1IN122 - S3_X1IN133 - - - - 0.9V - VLOGIC - 0.9 - 0.01 - 0.02 - - - 1.8V - VCC - 1.8 - - 0.01 - 0.02 - - - - - - -- cgit v1.2.1 From 377c476bc4120800624403bd359dbf332e9206e6 Mon Sep 17 00:00:00 2001 From: Matt Spinler Date: Wed, 29 Oct 2014 14:00:55 -0500 Subject: Create stylesheet to make processor->APSS SPI bus HTML. Added missing I2C LIGHTPAD connection to SCM, for board VPD and TPM. Added 24c256 VPD option for Habanero. --- VPD.xml | 39 +++++++++++++++ schema/mrw.xsd | 1 + turismo_scm.xml | 133 +++++++++++++++++++++++++++------------------------- xslt/mrwProcSpi.xsl | 43 +++++++++++++++++ 4 files changed, 152 insertions(+), 64 deletions(-) create mode 100644 VPD.xml create mode 100755 xslt/mrwProcSpi.xsl diff --git a/VPD.xml b/VPD.xml new file mode 100644 index 0000000..a15fe94 --- /dev/null +++ b/VPD.xml @@ -0,0 +1,39 @@ + + + + + + VPD + chip + seeprom + x0pxxxx + VPD + PLANAR_VPD + 24c64 + + + + I2C + SDA + + + + + + 3.3V + 3.3V + 3.3 + 0.01 + 0.02 + + + + + + + + + diff --git a/schema/mrw.xsd b/schema/mrw.xsd index c25bc0e..30cee0f 100644 --- a/schema/mrw.xsd +++ b/schema/mrw.xsd @@ -3537,6 +3537,7 @@ + diff --git a/turismo_scm.xml b/turismo_scm.xml index 70cb8ef..231c488 100644 --- a/turismo_scm.xml +++ b/turismo_scm.xml @@ -1,5 +1,5 @@ - + turismo_scm scm-module @@ -24,16 +24,6 @@ - - dmi14 - U0DMI_M1D - JBSMDMI_M1D - - - dmi8 - U0DMI_M0C - JBSMDMI_M0C - dmi11 U0DMI_M0D @@ -44,18 +34,28 @@ U0DMI_M1C JBSMDMI_M1C + + dmi8 + U0DMI_M0C + JBSMDMI_M0C + + + dmi14 + U0DMI_M1D + JBSMDMI_M1D + - - clock2 - U0OSC0_CHIP_REFCLK - JBSMLPC_CLK - clock17 U0OSC0_PCIE_REFCLK JBSMOSC0_PCIE_REFCLK + + clock2 + U0OSC0_CHIP_REFCLK + JBSMLPC_CLK + clock20 U0OSC0_TOD_REFCLK @@ -97,14 +97,9 @@ - power152 - U0VCS0 - JBSMVCS - - - power149 - U0VIO - JBSMVIO + power146 + U0VPCI + JBSMVPCI power155 @@ -112,30 +107,22 @@ JBSMVDD - power146 - U0VPCI - JBSMVPCI + power149 + U0VIO + JBSMVIO power143 U0AVDD JBSMAVDD + + power152 + U0VCS0 + JBSMVCS + - - i2c11 - No - 400 -
A0
- U0I2CM_PROM1 - U3I2C - - - i2c125 - U0I2C0 - JBSMI2C_0 - i2c2 No @@ -149,6 +136,14 @@ U0I2CM_HOTPLUG JBSMI2C_HOTPLUG + + i2c11 + No + 400 +
A0
+ U0I2CM_PROM1 + U3I2C + i2c8 No @@ -165,43 +160,48 @@ U0I2CM_PROM U2I2C + + i2c2 + U0I2CM_LIGHTPATH + JBSMI2C LIGHTPATH + + + i2c125 + U0I2C0 + JBSMI2C_0 + - - fsi62 - U0FSI_CASCADE2 - JBSMFSI0_CENT2 - fsi2 U0MFSI3 JBSMMFSI3 - - fsi65 - U0FSI_CASCADE3 - JBSMFSI0_CENT3 - fsi77 U0FSI_CASCADE7 JBSMFSI0_CENT7 - - fsi74 - U0FSI_CASCADE6 - JBSMFSI0_CENT6 - fsi59 U0FSI_CASCADE1 JBSMFSI0_CENT1 + + fsi65 + U0FSI_CASCADE3 + JBSMFSI0_CENT3 + fsi113 U0MFSI2 JBSMMFSI2 + + fsi62 + U0FSI_CASCADE2 + JBSMFSI0_CENT2 + fsi56 U0FSI_CASCADE0 @@ -217,37 +217,42 @@ U0MFSI1 JBSMMFSI1 + + fsi74 + U0FSI_CASCADE6 + JBSMFSI0_CENT6 + - powerbus47 + powerbus50 No 0x00000000 No 2 0x00000000 - U0A2 - JBSMA2 + U0A1 + JBSMA1 - powerbus50 + powerbus53 No 0x00000000 No 2 0x00000000 - U0A1 - JBSMA1 + U0A0 + JBSMA0 - powerbus53 + powerbus47 No 0x00000000 No 2 0x00000000 - U0A0 - JBSMA0 + U0A2 + JBSMA2 diff --git a/xslt/mrwProcSpi.xsl b/xslt/mrwProcSpi.xsl new file mode 100755 index 0000000..316b951 --- /dev/null +++ b/xslt/mrwProcSpi.xsl @@ -0,0 +1,43 @@ + + + + + + + + + + + + Processor SPI Connections + + +

Processor SPI Connections

+
+
+
MCS
+ + + + + + + + + + + + +
Processor TargetProcessor Instance PathEndpoint
n:p
+

+ + + + + + -- cgit v1.2.1