From b56eb303f4a4b0396d254efae579fe1c525f8d22 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 2 Jul 2018 14:03:44 +1000 Subject: Fix interrupt masking Using the wrong bits in SR isn't a very good idea Signed-off-by: Benjamin Herrenschmidt --- cf-code/cf-fsi-fw.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cf-code/cf-fsi-fw.S b/cf-code/cf-fsi-fw.S index adcf964..a65dd05 100644 --- a/cf-code/cf-fsi-fw.S +++ b/cf-code/cf-fsi-fw.S @@ -365,7 +365,7 @@ _start: move.l %a0,(0x46*4) /* Mask interrupts */ - move.w #0x2007,%sr + move.w #0x2700,%sr /* Configure GPIOs to output */ bsr config_gpio_out @@ -406,7 +406,7 @@ wait_cmd: beq 1f count_stop stop #0x2000 - move.w #0x2007,%sr + move.w #0x2700,%sr bra wait_cmd /* Neither continuous clocks nor STOP, use some nops -- cgit v1.2.1