| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Needs to be explicitely enabled
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The "value" register doesn't return the last data written when
read but returns the value sampled on the line, which may or
may not be the value written for an output GPIO. For example
it can be delayed by the synchronizers.
So whenever the CF reads the value to adjust its caches it needs
to use the "data read" register intead, otherwise it can clobber
values set by Linux when doing handshaking.
Also don't use %d0 for DTRA, use %d1 to avoid interrupts clobber
and do read/modify/write cycles on it as it's not a permanent
cached value, just a temporary.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The send path isn't the most critical and optimizing here
is hard for little return. Also on systems like Romulus where
both clk and data are in the same GPIO register, we already
don't need the test for value change since we use a single
write to write both value and clock.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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bset/bclk instructions are shorter when using a register,
this results in a small perf. improvement.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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This will be used by the kernel GPIO driver to synchronize
with the CF when accessing GPIO shared with FSI.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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seems to be the best value for performance
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Break sends a break command. It has 16000 recovery cycles as
per the existing GPIO based driver, though that might be
unnecessary in practice.
"idle clocks" sends up to 255 clocks with data line held high,
and can be used to flush things out for example after changing
the send delay, or before sending a DPOLL command as some CFAMs
seem to require extra clocks there.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Change to use the C preprocessor (use the ARM one for that) for
asm files so we can force-include a per-machine GPIO definition
file and use some preprocessor macros to define the cache registers.
This allows us to deal with the cases where the clock and data
use a different cache vs. the same cache.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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