| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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It was missing the dependency on the cf-fsi-fw.h file
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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For diagnostics purposes
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Stores may be asynchronous, I'm not entirely certain
what ordering the CF provides with the subsequent
read of the command in SRAM, so ensure the store did
make it by reading back first.
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The current sequence is possible in the main command loop
and in the arbitration sequence:
- STOP enables interrupt and stops execution
- Interrupt occurs (stale from previous command)
- No command (or arbitration response)
- Command is written
- Interrupt occurs again, is taken, does nothing
- STOP executes, doesn't wake up
We need to ensure that we only take the interrupt on
STOP, so we need to re-mask after every STOP. (We could
alternatively modify the SR in the interrupt stack to
return from the handler with IRQs disabled but this is
easier).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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And keep them masked during breaks
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Relying on the command-status is dicey, the GPIO arbitration
code needs a more reliable way to know we are actually running
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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We now use a portion of the ucode itself for version information
and to configure the base of SRAM, this will allow the driver
to use a pool allocator with less constraints.
We put the status register as part of the command register, this
speeds things up a bit and remove the need to clear it from
the host.
We also turn some SRAM stores from byte to long stores, they seem
to be faster (still room for improvement)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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With of course the notable exception of the exception vectors,
but this will make it easier should we want to relocate the
code.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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This will make it easier to share the reserved memory
from Linux as the ucode is now fully self contained.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Needs to be explicitely enabled
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The "value" register doesn't return the last data written when
read but returns the value sampled on the line, which may or
may not be the value written for an output GPIO. For example
it can be delayed by the synchronizers.
So whenever the CF reads the value to adjust its caches it needs
to use the "data read" register intead, otherwise it can clobber
values set by Linux when doing handshaking.
Also don't use %d0 for DTRA, use %d1 to avoid interrupts clobber
and do read/modify/write cycles on it as it's not a permanent
cached value, just a temporary.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The send path isn't the most critical and optimizing here
is hard for little return. Also on systems like Romulus where
both clk and data are in the same GPIO register, we already
don't need the test for value change since we use a single
write to write both value and clock.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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bset/bclk instructions are shorter when using a register,
this results in a small perf. improvement.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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This will be used by the kernel GPIO driver to synchronize
with the CF when accessing GPIO shared with FSI.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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seems to be the best value for performance
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Break sends a break command. It has 16000 recovery cycles as
per the existing GPIO based driver, though that might be
unnecessary in practice.
"idle clocks" sends up to 255 clocks with data line held high,
and can be used to flush things out for example after changing
the send delay, or before sending a DPOLL command as some CFAMs
seem to require extra clocks there.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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