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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2018-06-03 19:37:45 +1000 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2018-06-03 19:37:45 +1000 |
| commit | 389e7936ba57d70e28e75a3ab2ee80930682056e (patch) | |
| tree | 1a16900dfc1763bca108d3cf7997506c9d9a1da1 | |
| parent | 539a40d9324792b58b6cf550611d52afa891f931 (diff) | |
| download | cf-fsi-389e7936ba57d70e28e75a3ab2ee80930682056e.tar.gz cf-fsi-389e7936ba57d70e28e75a3ab2ee80930682056e.zip | |
Configure send/echo delay
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| -rw-r--r-- | cf-code/cf-fsi-fw.S | 5 | ||||
| -rw-r--r-- | cf-fsi-fw.h | 4 | ||||
| -rw-r--r-- | cf-fsi-test.c | 4 |
3 files changed, 11 insertions, 2 deletions
diff --git a/cf-code/cf-fsi-fw.S b/cf-code/cf-fsi-fw.S index a6cacee..f7bdcc6 100644 --- a/cf-code/cf-fsi-fw.S +++ b/cf-code/cf-fsi-fw.S @@ -275,7 +275,7 @@ start_command: bne 0b 2: /* Done sending, ready to receive, first echo delay */ - moveq #16,%d3 + move.b %a1@(ECHO_DLY_REG),%d3 /* d3 is already 0 */ clock_out_zeros %d3 /* Set GPIO and transceivers to input */ @@ -360,7 +360,8 @@ start_command: send_delay: /* Send delay after every command */ - moveq #16,%d3 + moveq.l #0,%d3 + move.b %a1@(SEND_DLY_REG),%d3 clock_out_zeros %d3 /* Configure GPIOs to output */ diff --git a/cf-fsi-fw.h b/cf-fsi-fw.h index 1897ea6..db59efc 100644 --- a/cf-fsi-fw.h +++ b/cf-fsi-fw.h @@ -49,6 +49,10 @@ /* Response CRC */ #define STAT_RCRC 0x06 +/* Echo and Send delay */ +#define ECHO_DLY_REG 0x08 +#define SEND_DLY_REG 0x09 + /* Command data area * * Last byte of message must be left aligned diff --git a/cf-fsi-test.c b/cf-fsi-test.c index 59a3f07..019777f 100644 --- a/cf-fsi-test.c +++ b/cf-fsi-test.c @@ -612,6 +612,10 @@ int main(int argc, char *argv[]) readb(sysreg + SRAM_BASE + STAT_REG), ntohl(readl(sysreg + SRAM_BASE + INT_CNT))); + /* Configure echo & send delay */ + writeb(16, sysreg + SRAM_BASE + ECHO_DLY_REG); + writeb(16, sysreg + SRAM_BASE + SEND_DLY_REG); + /* Enable interrupt */ writel(0x2, sysreg + CVIC_BASE + CVIC_EN_REG); |
