summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
* MIPS: rename M6201 core to M6250Vicente Olivert Riera2016-11-091-3/+3
| | | | | | | | | m6201 is the -march option for GCC, but the real core name is M6250. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Reviewed-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* MIPS: rename M5101 core to M5150Vicente Olivert Riera2016-11-091-3/+3
| | | | | | | | m5101 is the -march option for GCC, but the real core name is M5150. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Reviewed-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* MIPS: remove M5100 coreVicente Olivert Riera2016-11-091-5/+0
| | | | | | | | | This is a microcontroller class (MCU) core which is not suitable for running Linux. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Reviewed-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/Config.in.mips: add support for XBurst coresVicente Olivert Riera2016-11-091-0/+14
| | | | | | | | | | | | | | | The Ingenic XBurst is a MIPS32R2 microprocessor. It has a bug in the FPU that can generate incorrect results in certain cases. The problem shows up when you have several fused madd instructions in sequence with dependant operands. Using the -mno-fused-madd option prevents gcc from emitting these instructions. This patch adds changes to the toolchain wrapper to use that option. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* MIPS: add support for M6201 coresVicente Olivert Riera2016-10-191-0/+5
| | | | | | | | | | | | | | | -march=m6201 is not yet supported in GCC upstream, so disabling all versions when selecting this core. Note that M6201 implies a MIPS R6 CPU, and some GCC versions are already disabled for R6, so we don't need to disable those ones for M6201 as well. The external Codescape IMG GNU Linux Toolchain has support for this core. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* MIPS: add support for P6600 coresVicente Olivert Riera2016-10-151-0/+5
| | | | | | | | | | | | | | | -march=p6600 is not yet supported in GCC upstream, so disabling all versions when selecting this core. Note that P6600 implies a MIPS R6 CPU, and some GCC versions are already disabled for R6, so we don't need to disable those ones for P6600 as well. The external Codescape IMG GNU Linux Toolchain has support for this core. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: add support for P5600 coresVicente Olivert Riera2016-10-151-0/+5
| | | | | Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: add support for I6400 coresVicente Olivert Riera2016-10-151-0/+5
| | | | | | | | | | | | -march=i6400 support starts from GCC-6, so disable previous versions when selecting this core. Note that I6400 implies a MIPS R6 CPU, and some GCC versions are already disabled for R6, so we don't need to disable those ones for I6400 as well. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: add support for M5101 coresVicente Olivert Riera2016-10-151-0/+5
| | | | | | | | | | | | | | -march=m5101 support starts from GCC-6, so disable previous versions when selecting this core. Note that M5101 implies a MIPS R5 CPU, and some GCC versions are already disabled for R5, so we don't need to disable those ones for M5101 as well. Also disable external toolchains that don't support this core. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: add support for M5100 coresVicente Olivert Riera2016-10-151-0/+5
| | | | | | | | | | | | | | -march=m5100 support starts from GCC-6, so disable previous versions when selecting this core. Note that M5100 implies a MIPS R5 CPU, and some GCC versions are already disabled for R5, so we don't need to disable those ones for M5100 as well. Also disable external toolchains that don't support this core. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: add support for interAptiv coresVicente Olivert Riera2016-10-151-0/+5
| | | | | | | | | | -march=interaptiv support starts from GCC-6, so disable previous versions when selecting this core. Also disable external toolchains that don't support this core. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: add mips64r5 generic architecture variantVicente Olivert Riera2016-10-151-1/+8
| | | | | | | | -march=mips64r5 support started from GCC-5, so disable previous versions when the CPU is R5. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: add mips32r5 generic architecture variantVicente Olivert Riera2016-10-151-1/+8
| | | | | | | | -march=mips32r5 support started from GCC-5, so disable previous versions when the CPU is R5. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: state that the current architecture variants are genericVicente Olivert Riera2016-10-151-6/+6
| | | | | Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: target architecture variants select the appropriate CPU ISAVicente Olivert Riera2016-10-151-0/+6
| | | | | Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* MIPS: add default CPU ISAsVicente Olivert Riera2016-10-151-0/+14
| | | | | | | Meant to be used by the target architecture variants. Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch: remove support for sh64Gustavo Zacarias2016-09-082-13/+2
| | | | | | | It's been deprecated for quite some time now. Signed-off-by: Gustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* bfin: change default to bf532, internal toolchain !bf6xxWaldemar Brodkorb2016-08-271-1/+1
| | | | | | | | | The default Blackfin processor in Buildroot isn't supported by gcc 6.1.0, so use bf532 as default. Disable any bf6xx processors for internal toolchain users. Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* m68k: disable BR2_BINFMT_FLAT_SEP_DATA for coldfireWaldemar Brodkorb2016-08-231-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | BR2_BINFMT_FLAT_SEP_DATA can be used to create XIP userland and works fine for m68k. Unfortunately a lot of basic packages as pcre are not compileable because of a CPU or hardware limitation. The reason for failing are very big functions used in the libraries or application code. Typical errors are: Fatal error: Tried to convert PC relative branch to absolute jump or error: value -yyyyy out of range Add kernel patch from 4ec5542679264bc06a0356ef92f06ad7a0abe06d to make BR2_BINFMT_FLAT_ONE compiled firmware work fine. Fixes: http://autobuild.buildroot.net/results/20b/20b1586757450d6aad8583ad7a787a7ca11acef1/ http://autobuild.buildroot.net/results/d31/d311955ada1ffcd7f69e82965c8fe33eabe488cd/ Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> [Thomas: add comment in Config.in file about sep-data existing on m68k, but being disabled due to build issues with numerous packages.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* m68k: flat one memory region works with small kernel patchWaldemar Brodkorb2016-08-231-1/+0
| | | | | | | | | | | Greg Ungerer fixed recently a bug in the Linux kernel, which allows to use one memory region again. Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> [Thomas: cherry-picked from next to master, in order to be able to use BR2_BINFMT_FLAT_ONE by default on m68k, since BR2_BINFMT_FLAT_SEP_DATA causes too much problems.] Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch: define dependencies for the binfmt flat formatsWaldemar Brodkorb2016-07-051-0/+3
| | | | | | | | | | | | | | | | | | | The situation looks like following for elf2flt and binfmt FLAT: * Only gcc for bfin/m68k implements -msep-data (BR2_BINFMT_FLAT_SEP_DATA) and -mid-shared-library (BR2_BINFMT_FLAT_SHARED), so the corresponding options are made only visible on those architectures. * When the default of BR2_BINFMT_FLAT_ONE is used on m68k, broken binaries are produced, which mainly end up in SIGILL, so do not use it for m68k. Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> [Thomas: - also add the dependencies on m68k/bfin to BR2_BINFMT_FLAT_SHARED - rework commit log.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* m68k: remove BR2_GCC_TARGET_ARCHWaldemar Brodkorb2016-06-071-4/+0
| | | | | | | | | | Setting BR2_GCC_TARGET_ARCH is possible, but breaks external toolchain users. m68k/cf defconfigs just working without it. Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* toolchain: add coldfire supportWaldemar Brodkorb2016-04-302-1/+21
| | | | | | | | Add support for m68k/coldfire. A gcc patch is required to avoid gcc ICE. Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* i386: properly define BR2_ARCH for all x86 subarchitecturesThomas Petazzoni2016-04-211-0/+2
| | | | | | | | | | | | | | We were not defining BR2_ARCH for two of the x86 subarchitecture, which means the architecture part of the GNU_TARGET_NAME tuple was empty, leading to weird build failures. This commit fixes that by defining the appropriate values. Fixes bug #8861. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/x86: remove support for i386Thomas Petazzoni2016-04-181-5/+0
| | | | | | | | | | | | The Linux kernel doesn't even support i386 anymore, there is no NPTL support for i386 and uClibc-ng only supports NPTL on x86, so there is essentially no usable thread implementation. Most likely glibc and musl also don't support i386 either. So it's time to remove the support for this architecture variant. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: add Cortex-M4 entryThomas Petazzoni2016-03-201-0/+5
| | | | | | | | | | | | This commit adds the option to select the Cortex-M4 ARM core, in the same family as Cortex-M3. This will be useful to enable the internal toolchain backend for this ARM core, and provide some defconfigs for Cortex-M4 platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Reviewed-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: Cortex-M3 provides only Thumb-2Thomas Petazzoni2016-03-201-1/+0
| | | | | | | | | | | | | | | The Cortex-M cores only support Thumb-2, not Thumb. In fact, Thumb-2 is a superset of Thumb, and we could have a single option for both in Buildroot, since -mthumb on ARMv4/v5 means original Thumb, while -mthumb on ARMv7 means Thumb 2. However, for clarity, it makes sense to have two separate options. But in this case, Cortex-M3 should not advertise that it supports Thumb, as in fact selecting Thumb would generate Thumb-2 code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Reviewed-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: introduce and use BR2_ARM_CPU_ARMV7MThomas Petazzoni2016-03-201-0/+4
| | | | | | | | | | | All ARM cores should select a BR2_ARM_CPU_* option. Currently, the cortex-m3 does not, which this commit fixes by introducing a BR2_ARM_CPU_ARMV7M option. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Acked-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/m68k: re-enable the architectureWaldemar Brodkorb2016-03-202-7/+14
| | | | | | | This allows to build a m68k toolchain with uClibc. Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: add the cortex A17 variant supported by gcc 5.xEzequiel García2016-02-221-0/+9
| | | | | | | | | Add the Cortex A17 variant. This core is considered a replacement of the Cortex A12 and is supported by gcc 5 / binutils 2.25+ Suggested-by: Ross Green <greenfross@netscape.net> Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch: remove BR2_ARCH_HAS_ATOMICS optionThomas Petazzoni2016-02-0613-40/+0
| | | | | | | | Now that BR2_ARCH_HAS_ATOMICS is no longer used anywhere, we can remove it from arch/Config.in*, as well as from the documentation. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
* Add ARM11 MPCore CPU target supportSergi Granell2016-01-031-0/+9
| | | | | | | | | | | | | | | gcc differentiates the mpcore-with-vfp from the mcpore-without-vfp CPUs. The former is named just 'mpcore', while the latter is named 'mpcorenovfp'. We only add one entry, 'mpcore' and let the user select whether or not to use the VFP. We then name the CPU according to the user's selection. Signed-off-by: Sergi Granell <xerpi.g.12@gmail.com> Tested-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Acked-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch/arm: add help text to BR2_ARM_ENABLE_VFPThomas Petazzoni2015-12-271-0/+4
| | | | Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: only expose VFP in FP strategy when the CPU *has* a VFP unitYann E. MORIN2015-12-271-6/+6
| | | | | | | | | There's no point in offering the user an option to select an FP strategy when the CPU does not actually have a VFP unit. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: only expose EABIhf when the CPU *has* a VFP unitYann E. MORIN2015-12-271-1/+1
| | | | | | | | | There's no point in offering the user an option to select EABIhf when the CPU does not really have a VFP unit. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: add option to enable an optional VFP unitYann E. MORIN2015-12-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the VFP selection for ARM is a little bit muddy: - some CPUs definitely do not have a VFP or NEON, - some CPUs definitely do have a VFP or NEON, - some CPUs may have a VFP or NEON. However, we currently conflate the availability of the VFP/NEON with the possibility to use them. Even is the user chooses a floating point strategy with a 'lower' solution (i.e. VFPv2 when a VFPv3 exists, or not using NEON when the CPU has it), some packages are still using the CPU-defined HW availaibility rather thean the usr's selection. Furthermore, for CPU that may have a VFP/NEON, there is no way for the user to actually specify that the HW is indeed available; the user can only specify the floating point strategy. This means that some packages or some package versions, like nodejs for example, can not be properly selected on some CPU cores, like Cortex-A9 which only may have a VFP. Like we have an option to enable an optional NEON unit, add a similar option to enable an optional VFP unit. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: reorder NEON optionYann E. MORIN2015-12-271-9/+9
| | | | | | | | | | | | | | | Stating whether to use the NEON extensions when it is optional in the CPU really is completing the definition of the CPU we've just selected. Move the ENABLE_NEON option just after the choice of the CPU variant, and before any "software" option (ABI/VFP). This will make sense in a moment, when we introduce a similar option for enabling an optional VFP unit. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch: add tune options for powerpc e5500 and e6500Arnout Vandecappelle2015-11-171-0/+2
| | | | | | | | | | These were forgotten when the subarches were added in cd88e49. Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Cc: Alvaro Gamez <alvaro.gamez@hazent.com> Cc: Gustavo Zacarias <gustavo@zacarias.com.ar> Tested-by: Alvaro G. M <alvaro.gamez@hazent.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch/arm: VFP and Thumb1 are not compatibleYann E. MORIN2015-11-031-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc will refuse to build with both --with-mode=thumb and --with-fpu=vfp, with error messages during ./configure, like: checking for suffix of object files... configure: error: in `/home/ymor in/dev/buildroot/O/build/host-gcc-initial-4.9.3/build/arm-buildroot-lin ux-uclibcgnueabihf/libgcc': configure: error: cannot compute suffix of object files: cannot compile See `config.log' for more details. And config.log informatively contains: sorry, unimplemented: Thumb-1 hard-float VFP ABI This is an error message that comes deep from gcc source files. If gcc says it does not support VFP with Thumb1, then let's disable that combination in our menuconfig. Prefer VFP over Thumb1, i.e. hide Thumb1 when we're not soft-float. Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Cc: Gustavo Zacarias <gustavo@zacarias.com.ar> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: use EABIhf by default with VFPBenoît Thébaudeau2015-10-251-0/+1
| | | | | | | | | | Set EABIhf as the default target ABI for the ARM processors that have or may have a VFP unit, since this ABI is the most efficient in that case. Of course, EABI can still be selected manually if needed. [Peter: only default to EABIHF when we are sure the CPU has a VFP] Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch/Config.in.x86: drop trailing dot (.) from x1000 URLPeter Korsgaard2015-10-201-1/+2
| | | | | | And add an empty line below for clarity. Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* arch/x86: add support for Intel X1000Ray Kinsella2015-10-201-0/+12
| | | | | | | | | | | | The Intel X1000 is the Pentium class microprocessor that ships with Galileo Gen 1/2. This patch adds changes to arch and toolchain-wrapper to omit the lock prefix for the X1000. [Thomas: tweak commit log and Config.in help text.] Signed-off-by: Ray Kinsella <ray.kinsella@intel.com> Reviewed-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch: add support for mips32r6 and mips64r6 variantsVicente Olivert Riera2015-10-121-2/+10
| | | | | | | | | | | | | | | - Add support for mips32r6 and mips64r6 target architecture variants - Disable unsupported gcc versions - Disable unsupported binutils versions - Disable unsupported external toolchains - Disable unsuported C libraries - Add a hook in order to make glibc compile for MIPS R6. [Thomas: slightly tweak the glibc hack explanation, to make it hopefully clearer.] Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* toolchain: add sparc64 architecture supportWaldemar Brodkorb2015-10-102-3/+21
| | | | | | | | | Introduce sparc64 architecture to buildroot. Signed-off-by: Waldemar Brodkorb <wbx@openadk.org> Acked-by: Gustavo Zacarias <gustavo@zacarias.com.ar> Tested-by: Gustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/mips: remove some remaining mips1/2/3/4 bitsVicente Olivert Riera2015-10-091-6/+2
| | | | | | Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Reviewed-by: Gustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch/arm: add missing arm1136j-s variantPeter Korsgaard2015-08-241-0/+6
| | | | | | Identical to arm1136jf-s, except that is doesn't have a vfp unit. Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
* ARC: allow selection of MMU page sizeAlexey Brodkin2015-07-181-0/+38
| | | | | | | | | | | | | | | | | | Modern ARC cores (those sporting MMU of version 3 and 4) allow selection of different page sizes (4, 8 or 16 kB) during ASIC design creation. And it's important to build a toolchain with page size setting that matches hardware. Otherwise user-space applications will fail on execution due to unexpected data layout/alignment etc. [Thomas: slightly improve help text, fix indentation of help text.] Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Anton Kolesov <akolesov@synopsys.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Arnout Vandecappelle <arnout@mind.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arch: aarch64 always has a MMUThomas Petazzoni2015-07-121-0/+1
| | | | | | | | Following the addition of AArch64 big endian, the AArch64 little endian option had lost its 'select BR2_ARCH_HAS_MMU_MANDATORY', so let's reintroduce it. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* aarch64: add big endian(aarch64_be) supportBamvor Jian Zhang2015-07-122-3/+13
| | | | | | | | | Add aarch64_be support. Note that CONFIG_CPU_BIG_ENDIAN should be defined in kernel config when building a big endian kernel. Signed-off-by: Zhang Jian(Bamvor) <bamvor.zhangjian@huawei.com> Acked-by: Gustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* arm: update processor typesGuido Martínez2015-06-281-0/+5
| | | | | | | | | Add the Cortex M3 variant. These microcontrollers don't support regular ARM instructions and don't have an MMU. Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar> Reviewed-by: "Yann E. MORIN" <yann.morin.1998@free.fr> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
OpenPOWER on IntegriCloud