<feed xmlns='http://www.w3.org/2005/Atom'>
<title>buildroot/arch, branch 2018.02</title>
<subtitle>OpenPOWER buildroot sources</subtitle>
<id>https://git.raptorcs.com/git/buildroot/atom?h=2018.02</id>
<link rel='self' href='https://git.raptorcs.com/git/buildroot/atom?h=2018.02'/>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/'/>
<updated>2018-01-01T12:05:16+00:00</updated>
<entry>
<title>arch: add Atom CPUs as Silvermont Architecture target</title>
<updated>2018-01-01T12:05:16+00:00</updated>
<author>
<name>Norbert Lange</name>
<email>nolange79@gmail.com</email>
</author>
<published>2017-10-24T12:22:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=1eecd462ae052cbb056de2d89419f445c4cbd4fa'/>
<id>urn:sha1:1eecd462ae052cbb056de2d89419f445c4cbd4fa</id>
<content type='text'>
The old Atom target is not really fitting for recent Atom CPUs based
on Silvermont, Airmont or Goldmont. Those have more in common with
older Desktop CPUs than old Atoms.

Signed-off-by: Norbert Lange &lt;norbert.lange@andritz.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: default to Cortex-A53 for AArch64</title>
<updated>2017-12-07T21:39:44+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-12-04T20:43:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=ae2ec0ed74207bb6264e9b90bafdb2d8125c3472'/>
<id>urn:sha1:ae2ec0ed74207bb6264e9b90bafdb2d8125c3472</id>
<content type='text'>
Since we re-organised the list of cores (in 52d500aa35) and introduced
some new cores (in e9960da6ec, d632d9e5a9, 6317a199ec), the default for
AArch64 was accidently changed from A53 to A35.

So, restore the default to A53 for AArch64.

Reported-by: daggs &lt;daggs@gmx.com&gt;
Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: daggs &lt;daggs@gmx.com&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: add armv8.1a cores</title>
<updated>2017-11-24T22:30:43+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-09-03T13:17:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=6317a199ecb525309e8172237a15b46776fe3a72'/>
<id>urn:sha1:6317a199ecb525309e8172237a15b46776fe3a72</id>
<content type='text'>
The armv8.1a generation is a cumulative extension to armv8a. It adds new
extensions, and makes some previously optional ones now mandatory.

Since gcc correctly enables the appropriate extensions based on the core
name, we don't really need to introduce a separate config for armv8.1a,
and we can piggyback on armv8a.

All those new cores are aarch64 only (gcc fails to build in arm mode).

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: add some non-cortex armv8a cores</title>
<updated>2017-11-24T22:30:36+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-09-03T13:17:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=d632d9e5a984a8da01156f28a2180e344f6a07a7'/>
<id>urn:sha1:d632d9e5a984a8da01156f28a2180e344f6a07a7</id>
<content type='text'>
Some need gcc-5, some gcc-6 and some gcc-7.

The thunderx familly does not build in 32-bit mode (gcc complains
that the CPU is unknown, and even gcc master only knows them as
aarch64-only).

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: add some armv8a cortex variants</title>
<updated>2017-11-24T22:18:08+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-09-03T13:17:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=e9960da6ec84d0fc4f3d7ef8d9db5b1e29d79358'/>
<id>urn:sha1:e9960da6ec84d0fc4f3d7ef8d9db5b1e29d79358</id>
<content type='text'>
Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: add cortex-A32</title>
<updated>2017-11-24T22:11:52+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-09-03T13:17:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=ffc9d6024312017a9fc7ecf6c112e60bd8288af4'/>
<id>urn:sha1:ffc9d6024312017a9fc7ecf6c112e60bd8288af4</id>
<content type='text'>
The cortex-A32 is an armv8a core, but it lacks the optional AArch64
extensions, so can only work in 32-bit mode.

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: armv8 is really armv8a</title>
<updated>2017-11-24T22:01:41+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-09-03T13:17:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=003b1f3c74689986f9f6e7f8ce96b4e422c94a93'/>
<id>urn:sha1:003b1f3c74689986f9f6e7f8ce96b4e422c94a93</id>
<content type='text'>
For armv8, there are different profiles: A, M and R, like there is for
armv7.

So, rename our internal symbol to mirror what we do for armv7.

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: simplify hiding non 64-bit cores</title>
<updated>2017-11-24T22:01:03+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-09-03T13:17:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=a9f95de2c0d81d40ef4b062447f1d7deba34788c'/>
<id>urn:sha1:a9f95de2c0d81d40ef4b062447f1d7deba34788c</id>
<content type='text'>
Now that the cores are all oredered correctly, we can just enclose all
the non 64-bit cores inside a big if-block, rather than have each of
them have the dependency.

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: re-order cores choice</title>
<updated>2017-11-24T22:00:37+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-09-03T13:17:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=52d500aa35acb8b3570dcfcc36ac71e083656e5a'/>
<id>urn:sha1:52d500aa35acb8b3570dcfcc36ac71e083656e5a</id>
<content type='text'>
Currently, the logic for ordering the ARM cores in the choice is all
but obvious. ;-)

Reorder the choice by architecture generation, starting with armv4,
ending with armv8.

Add a comment before each generation, just for ease of use. Add a
separate comment for armv7a and armv7m.

Finally, order cores alphabetically inside the same generation (except
for armv7m cores, listed after all armv7a cores).

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/mips: inverse the mfpxx logic</title>
<updated>2017-11-24T21:45:48+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2017-09-03T09:53:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=e25d704e10230f7ea095b4bbb5660e73fbefdf29'/>
<id>urn:sha1:e25d704e10230f7ea095b4bbb5660e73fbefdf29</id>
<content type='text'>
Currently, the possibility to choose the floating point mode (32, xx or
64) is conditional on having a sufficiently recent gcc version.

Which means that the architecture selection depends on the gcc version.

But that's opposite to what we've always done in Buildroot: the software
versions are conditional to the architecture options. There is nothing
we can do about the hardware: it is there, we can't change it, while we
can restrict ourselves to using software that is working on said
hardware.

Thus, we inverse the logic, to move the condition onto the software
side: whenever mfpxx is selected, we restrict the toolchain selection to
at least a gcc-5.

And now, the blind BR2_TOOLCHAIN_HAS_MFPXX_OPTION symbol is no longer
needed, so we get rid of it.

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Cc: Vicente Olivert Riera &lt;Vincent.Riera@imgtec.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
</feed>
