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<title>buildroot/arch, branch 2017.02</title>
<subtitle>OpenPOWER buildroot sources</subtitle>
<id>https://git.raptorcs.com/git/buildroot/atom?h=2017.02</id>
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<updated>2017-01-25T21:53:53+00:00</updated>
<entry>
<title>arch: add OpenRISC architecture support</title>
<updated>2017-01-25T21:53:53+00:00</updated>
<author>
<name>Waldemar Brodkorb</name>
<email>wbx@openadk.org</email>
</author>
<published>2017-01-25T06:35:07+00:00</published>
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<id>urn:sha1:a818e29e76d9a083877094ed7bb3e9cfd31f3a46</id>
<content type='text'>
Add support for OpenRISC. See here for more details about
OpenRISC http://openrisc.io.

All buildroot included upstream binutils versions are supported.
Gcc support is not upstream, to be able to enable musl C library
support later, we use the branch with musl support.
At the moment it is possible to build a musl based toolchain,
but bootup in Qemu fails.

Gdb is only working to debug bare-metal code, there is no support
for gdbserver/gdb on Linux, yet.

[Peter: drop ?= for GCC_SOURCE]
Signed-off-by: Waldemar Brodkorb &lt;wbx@openadk.org&gt;
Tested-by: Romain Naour &lt;romain.naour@gmail.com&gt;
Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.arm: support thumb2 instructions for ARMv8 in 32bit mode</title>
<updated>2016-12-08T21:32:17+00:00</updated>
<author>
<name>Peter Korsgaard</name>
<email>peter@korsgaard.com</email>
</author>
<published>2016-12-07T09:25:22+00:00</published>
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<id>urn:sha1:933732b82b148cbf7e79c77d85810528787ef1e7</id>
<content type='text'>
The ARMv8 cores all support thumb2 instructions when running in aarch32 mode.

Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.arm: only enable BR2_ARM_CPU_HAS_NEON for ARMv8 in 32bit mode</title>
<updated>2016-12-08T21:32:16+00:00</updated>
<author>
<name>Peter Korsgaard</name>
<email>peter@korsgaard.com</email>
</author>
<published>2016-12-07T09:25:21+00:00</published>
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<id>urn:sha1:0976cd6cd64a128a2ac921e4f35f0e7cbe306692</id>
<content type='text'>
A number of packages use BR2_ARM_CPU_HAS_NEON to know if the target handles
aarch32 neon instructions, which is only true for ARMv8 cores when they are
running in 32bit mode.

Notice: These cores do support neon-like instructions using a different
encoding in 64bit mode (it is a required part of ARMv8, similar to the FPU).

Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.arm: only enable BR2_ARM_CPU_HAS_ARM for ARMv8 in 32bit mode</title>
<updated>2016-12-08T21:32:14+00:00</updated>
<author>
<name>Peter Korsgaard</name>
<email>peter@korsgaard.com</email>
</author>
<published>2016-12-07T09:25:20+00:00</published>
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<id>urn:sha1:6d97af8763a10180ff935a3dff90b217d79246e6</id>
<content type='text'>
Fixes:
http://autobuild.buildroot.net/results/5e6/5e67cc067a06f7364cde1a8393ea72608fe7fef1/

A number of packages use BR2_ARM_CPU_HAS_ARM to know if the target handles
classic A32 instructions, which is only true for ARMv8 cores when they are
running in 32bit mode.

Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.arm: add Cortex-A57 and Cortex-A72</title>
<updated>2016-12-05T22:07:14+00:00</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2016-11-30T21:12:11+00:00</published>
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<id>urn:sha1:2131f1b3817d594ce24ac9ba263f104077cf7c49</id>
<content type='text'>
Add two popular ARM64 cores to the list of supported cores: Cortex-A57
and Cortex-A72.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Yann E. MORIN &lt;yann.morin.1998@free.fr&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.arm: Add Cortex-A53 CPU</title>
<updated>2016-12-05T22:07:13+00:00</updated>
<author>
<name>Matt Flax</name>
<email>flatmax@flatmax.org</email>
</author>
<published>2016-11-30T21:12:10+00:00</published>
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<id>urn:sha1:785a73fb8f64d14c68b0c035aa40b203a2a17378</id>
<content type='text'>
Adds the Cortex-A53 CPU to the target architecture variant choice. This
sets the toolchain to use Cortex-A53 as the target. The effect is that
various Cortex-A53 tunings are enabled for the compilation of packages.

Signed-off-by: Matt Flax &lt;flatmax@flatmax.org&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Yann E. MORIN &lt;yann.morin.1998@free.fr&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.arm: specify ABI for ARM64</title>
<updated>2016-12-05T22:07:11+00:00</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2016-11-30T21:12:09+00:00</published>
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<id>urn:sha1:5e8cb2ee759780c38e06aa8e83d98bb1f2943cc2</id>
<content type='text'>
There's currently only one widely supported ABI for ARM64, called lp64,
so we define BR2_GCC_TARGET_ABI to the appropriate value.

Note that there is another ABI for ARM64 being worked on, ilp32, but its
support is not fully upstream in the kernel, so we're not adding support
for it for the moment.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Yann E. MORIN &lt;yann.morin.1998@free.fr&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.arm: add FPU related options for ARMv8 cores</title>
<updated>2016-12-05T22:07:10+00:00</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2016-11-30T21:12:08+00:00</published>
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<id>urn:sha1:d690b7444a819a53a756cd3b6047584802d55d92</id>
<content type='text'>
The ARMv8 cores have a mandatory FPU unit called FP-ARMv8, so we:

 - add a new hidden Config.in option for the availability of this
   unit (BR2_ARM_CPU_HAS_FP_ARMV8)

 - allow the selection of a possible choice in the "Floating point
   strategy", and add two new choices: BR2_ARM_FPU_FP_ARMV8 and
   BR2_ARM_FPU_NEON_FP_ARMV8.

 - specify the -mfpu values for BR2_ARM_FPU_FP_ARMV8 and
   BR2_ARM_FPU_NEON_FP_ARMV8 cases, when used on ARM 32 bits (-mfpu
   doesn't exist on ARM64, instead -mcpu modifiers are used, so they
   will be added on a per-core basis).

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
[yann.morin.1998@free.fr: drop the FP strategy dependency]
Signed-off-by: Yann E. MORIN &lt;yann.morin.1998@free.fr&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: drop legacy dependency for floating point strategy</title>
<updated>2016-12-05T22:07:09+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2016-11-30T21:12:07+00:00</published>
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<id>urn:sha1:743e6639123890f6cbcecdc8d4b935e82a548aca</id>
<content type='text'>
The floating point strategy currently depends on EABI || EABIHF. The
reason was that, wayback when we also supported OABI, we only exposed FP
for EABI or EABIHF, and hide it for OABI, which did not support FP.

It's been a while now that we do not support OABI, but the dependency
stuck all along.

Remove it as it is no longer needed, and is always true.

However, the choice is empty for AArch64, as we still have no entry for
their floating point strategy yet.

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.arm: add BR2_ARM_CPU_ARMV8</title>
<updated>2016-12-05T22:07:08+00:00</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2016-11-30T21:12:06+00:00</published>
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<id>urn:sha1:c37189b35ed09fc1f51debd2e51aac2520a4a213</id>
<content type='text'>
In order to prepare the addition of ARM64 cores, add the blind
BR2_ARM_CPU_ARMV8 option.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Yann E. MORIN &lt;yann.morin.1998@free.fr&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
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