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<title>buildroot/arch, branch 2015.11</title>
<subtitle>OpenPOWER buildroot sources</subtitle>
<id>https://git.raptorcs.com/git/buildroot/atom?h=2015.11</id>
<link rel='self' href='https://git.raptorcs.com/git/buildroot/atom?h=2015.11'/>
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<updated>2015-11-16T23:16:39+00:00</updated>
<entry>
<title>arch: add tune options for powerpc e5500 and e6500</title>
<updated>2015-11-16T23:16:39+00:00</updated>
<author>
<name>Arnout Vandecappelle</name>
<email>arnout@mind.be</email>
</author>
<published>2015-11-06T14:05:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=b3f7f949f0935535bff5d2fd51e3e14308b714bc'/>
<id>urn:sha1:b3f7f949f0935535bff5d2fd51e3e14308b714bc</id>
<content type='text'>
These were forgotten when the subarches were added in cd88e49.

Signed-off-by: Arnout Vandecappelle (Essensium/Mind) &lt;arnout@mind.be&gt;
Cc: Alvaro Gamez &lt;alvaro.gamez@hazent.com&gt;
Cc: Gustavo Zacarias &lt;gustavo@zacarias.com.ar&gt;
Tested-by: Alvaro G. M &lt;alvaro.gamez@hazent.com&gt;
Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: VFP and Thumb1 are not compatible</title>
<updated>2015-11-03T22:50:01+00:00</updated>
<author>
<name>Yann E. MORIN</name>
<email>yann.morin.1998@free.fr</email>
</author>
<published>2015-11-02T23:34:37+00:00</published>
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<id>urn:sha1:e4b1fa69cdd46ea9874de243f52c6938de19674d</id>
<content type='text'>
gcc will refuse to build with both --with-mode=thumb and --with-fpu=vfp,
with error messages during ./configure, like:

    checking for suffix of object files... configure: error: in `/home/ymor
    in/dev/buildroot/O/build/host-gcc-initial-4.9.3/build/arm-buildroot-lin
    ux-uclibcgnueabihf/libgcc':
    configure: error: cannot compute suffix of object files: cannot compile
    See `config.log' for more details.

And config.log informatively contains:

    sorry, unimplemented: Thumb-1 hard-float VFP ABI

This is an error message that comes deep from gcc source files.

If gcc says it does not support VFP with Thumb1, then let's disable that
combination in our menuconfig.

Prefer VFP over Thumb1, i.e. hide Thumb1 when we're not soft-float.

Signed-off-by: "Yann E. MORIN" &lt;yann.morin.1998@free.fr&gt;
Cc: Gustavo Zacarias &lt;gustavo@zacarias.com.ar&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Acked-by: Arnout Vandecappelle (Essensium/Mind) &lt;arnout@mind.be&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: use EABIhf by default with VFP</title>
<updated>2015-10-25T18:56:20+00:00</updated>
<author>
<name>Benoît Thébaudeau</name>
<email>benoit.thebaudeau.dev@gmail.com</email>
</author>
<published>2015-10-25T15:19:40+00:00</published>
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<id>urn:sha1:cc0773f2a89f30b252532e771cf4ffa513f57f2d</id>
<content type='text'>
Set EABIhf as the default target ABI for the ARM processors that have or
may have a VFP unit, since this ABI is the most efficient in that case.
Of course, EABI can still be selected manually if needed.

[Peter: only default to EABIHF when we are sure the CPU has a VFP]
Signed-off-by: Benoît Thébaudeau &lt;benoit.thebaudeau.dev@gmail.com&gt;
Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</content>
</entry>
<entry>
<title>arch/Config.in.x86: drop trailing dot (.) from x1000 URL</title>
<updated>2015-10-20T09:32:03+00:00</updated>
<author>
<name>Peter Korsgaard</name>
<email>peter@korsgaard.com</email>
</author>
<published>2015-10-20T09:32:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.raptorcs.com/git/buildroot/commit/?id=8da1239a12276baa9e8193c7ed49da3234d2900c'/>
<id>urn:sha1:8da1239a12276baa9e8193c7ed49da3234d2900c</id>
<content type='text'>
And add an empty line below for clarity.

Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</content>
</entry>
<entry>
<title>arch/x86: add support for Intel X1000</title>
<updated>2015-10-20T08:04:52+00:00</updated>
<author>
<name>Ray Kinsella</name>
<email>ray.kinsella@intel.com</email>
</author>
<published>2015-10-19T11:02:52+00:00</published>
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<id>urn:sha1:968f5d5e59195e6e6a9a349ec9a118fb3a50b8b3</id>
<content type='text'>
The Intel X1000 is the Pentium class microprocessor that ships with
Galileo Gen 1/2. This patch adds changes to arch and toolchain-wrapper
to omit the lock prefix for the X1000.

[Thomas: tweak commit log and Config.in help text.]

Signed-off-by: Ray Kinsella &lt;ray.kinsella@intel.com&gt;
Reviewed-by: Arnout Vandecappelle (Essensium/Mind) &lt;arnout@mind.be&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch: add support for mips32r6 and mips64r6 variants</title>
<updated>2015-10-12T19:33:56+00:00</updated>
<author>
<name>Vicente Olivert Riera</name>
<email>Vincent.Riera@imgtec.com</email>
</author>
<published>2015-10-12T10:08:06+00:00</published>
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<id>urn:sha1:99122d67808b91ae1011d440a78f46b0083564b0</id>
<content type='text'>
- Add support for mips32r6 and mips64r6 target architecture variants
- Disable unsupported gcc versions
- Disable unsupported binutils versions
- Disable unsupported external toolchains
- Disable unsuported C libraries
- Add a hook in order to make glibc compile for MIPS R6.

[Thomas: slightly tweak the glibc hack explanation, to make it
hopefully clearer.]

Signed-off-by: Vicente Olivert Riera &lt;Vincent.Riera@imgtec.com&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>toolchain: add sparc64 architecture support</title>
<updated>2015-10-10T10:51:45+00:00</updated>
<author>
<name>Waldemar Brodkorb</name>
<email>wbx@openadk.org</email>
</author>
<published>2015-08-29T07:57:33+00:00</published>
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<id>urn:sha1:4a92f6754a39d8dc22a8285fef36b0b58619cb24</id>
<content type='text'>
Introduce sparc64 architecture to buildroot.

Signed-off-by: Waldemar Brodkorb &lt;wbx@openadk.org&gt;
Acked-by: Gustavo Zacarias &lt;gustavo@zacarias.com.ar&gt;
Tested-by: Gustavo Zacarias &lt;gustavo@zacarias.com.ar&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/mips: remove some remaining mips1/2/3/4 bits</title>
<updated>2015-10-09T21:15:49+00:00</updated>
<author>
<name>Vicente Olivert Riera</name>
<email>Vincent.Riera@imgtec.com</email>
</author>
<published>2015-10-09T13:43:32+00:00</published>
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<id>urn:sha1:25677a717ccaaaf3d9acf32a3d968eaff8f09151</id>
<content type='text'>
Signed-off-by: Vicente Olivert Riera &lt;Vincent.Riera@imgtec.com&gt;
Reviewed-by: Gustavo Zacarias &lt;gustavo@zacarias.com.ar&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>arch/arm: add missing arm1136j-s variant</title>
<updated>2015-08-23T22:43:12+00:00</updated>
<author>
<name>Peter Korsgaard</name>
<email>peter@korsgaard.com</email>
</author>
<published>2015-08-23T22:43:12+00:00</published>
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<id>urn:sha1:7deaa277fd4c89c67de39ea21b4cd081ab85366f</id>
<content type='text'>
Identical to arm1136jf-s, except that is doesn't have a vfp unit.

Signed-off-by: Peter Korsgaard &lt;peter@korsgaard.com&gt;
</content>
</entry>
<entry>
<title>ARC: allow selection of MMU page size</title>
<updated>2015-07-18T12:07:35+00:00</updated>
<author>
<name>Alexey Brodkin</name>
<email>Alexey.Brodkin@synopsys.com</email>
</author>
<published>2015-07-17T09:11:42+00:00</published>
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<id>urn:sha1:3720e28d1595ea0fea349009d7b0360914f32ef6</id>
<content type='text'>
Modern ARC cores (those sporting MMU of version 3 and 4) allow selection
of different page sizes (4, 8 or 16 kB) during ASIC design creation.
And it's important to build a toolchain with page size setting that matches
hardware.

Otherwise user-space applications will fail on execution due to
unexpected data layout/alignment etc.

[Thomas: slightly improve help text, fix indentation of help text.]

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
Cc: Anton Kolesov &lt;akolesov@synopsys.com&gt;
Cc: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Cc: Arnout Vandecappelle &lt;arnout@mind.be&gt;
Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
</content>
</entry>
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