From b1d434d45d417f30c032d0201f34195065ffcedc Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 14 Nov 2016 13:06:07 +1100 Subject: xive: Fix mangling of interrupt server# in opal_get/set_xive() The OPAL API uses mangled server numbers with the link in the bottom 2 bits like a real XICS does, we need to account for it. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Stewart Smith --- hw/xive.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'hw/xive.c') diff --git a/hw/xive.c b/hw/xive.c index 3c25cae2..ba32925a 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1477,7 +1477,7 @@ static int64_t xive_source_get_xive(struct irq_source *is __unused, uint32_t target_id; if (xive_get_eq_info(isn, &target_id, prio)) { - *server = target_id; + *server = target_id << 2; return OPAL_SUCCESS; } else return OPAL_PARAMETER; @@ -1490,6 +1490,9 @@ static int64_t xive_source_set_xive(struct irq_source *is, uint32_t isn, uint32_t idx = isn - s->esb_base; void *mmio_base; + /* Unmangle server */ + server >>= 2; + /* Let XIVE configure the EQ */ if (!xive_set_eq_info(isn, server, prio)) return OPAL_PARAMETER; @@ -1704,15 +1707,10 @@ struct xive_cpu_state { static void xive_ipi_init(struct xive *x, struct cpu_thread *cpu) { struct xive_cpu_state *xs = cpu->xstate; - uint32_t idx = GIRQ_TO_IDX(xs->ipi_irq); - uint8_t *mm = x->esb_mmio + idx * 0x20000; assert(xs); - xive_source_set_xive(&x->ipis.is, xs->ipi_irq, cpu->pir, 0x7); - - /* Clear P and Q */ - in_8(mm + 0x10c00); + xive_source_set_xive(&x->ipis.is, xs->ipi_irq, cpu->pir << 2, 0x7); } static void xive_ipi_eoi(struct xive *x, uint32_t idx) -- cgit v1.2.1