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* cpu: Add OPAL_REINIT_CPUS_TM_SUSPEND_DISABLEDMichael Ellerman2017-10-161-0/+2
| | | | | | | | | | | | | Add a new CPU reinit flag, "TM Suspend Disabled", which requests that CPUs be configured so that TM (Transactional Memory) suspend mode is disabled. Currently this always fails, because skiboot has no way to query the state. A future hostboot change will add a mechanism for skiboot to determine the status and return an appropriate error code. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Enable PCI peer-to-peerFrederic Barrat2017-08-041-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | P9 supports PCI peer-to-peer: a PCI device can write directly to the mmio space of another PCI device. It completely by-passes the CPU. It requires some configuration on the PHBs involved: 1. on the initiating side, the address for the read/write operation is in the mmio space of the target, i.e. well outside the range normally allowed. So we disable range-checking on the TVT entry in bypass mode. 2. on the target side, we need to explicitly enable p2p by setting a bit in a configuration register. It has the side-effect of reserving an outbound (as seen from the CPU) store queue for p2p. Therefore we only enable p2p on the PHBs using it, as we don't want to waste the resource if we don't have to. P9 supports p2p mmio writes. Reads are currently only supported if the two devices are under the same PHB but that is expected to change in the future, and it raises questions about intermediate switches configuration, so we report an error for the time being. The patch adds a new OPAL call to allow the OS to declare a p2p (initiator, target) pair. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sensors: occ: Add support to clear sensor groupsShilpasri G Bhat2017-07-281-1/+2
| | | | | | | | | | Adds a generic API to clear sensor groups. OCC inband sensor groups such as CSM, Profiler and Job Scheduler can be cleared using this API. It will clear the min/max of all sensors belonging to OCC sensor groups. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* psr: occ: Add support to change power-shifting-ratioShilpasri G Bhat2017-07-281-1/+3
| | | | | | | | | | | Add support to set the CPU-GPU power shifting ratio which is used by the OCC power capping algorithm. PSR value of 100 takes all power away from CPU first and a PSR value of 0 caps GPU first. Documentation enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* powercap: occ: Add a generic powercap frameworkShilpasri G Bhat2017-07-281-1/+3
| | | | | | | | | | | This patch adds a generic powercap framework and exports OCC powercap sensors using which system powercap can be set inband through OPAL-OCC command-response interface. Documentation for powercap enhanced by Stewart Smith. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ: Add support for OPAL-OCC command/response interfaceShilpasri G Bhat2017-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for a shared memory based command/response interface between OCC and OPAL. In HOMER, there is an OPAL command buffer and an OCC response buffer which is used to send inband commands to OCC. The OPAL-OCC command/response sequence is as follows: 1. Check if both 'OCC Progress' bit in OCC response flag and 'Cmd Ready' bit in OPAL command flag are set to zero. If yes then proceed with below steps to send a command to OCC. 2. Write the command value, request ID and command specific data to the OPAL command buffer. 3. Clear the response flag and set the 'Cmd Ready' bit in OPAL command flag to indicate command is ready. 4. OCC will poll the command flag every 4ms to check if 'Cmd Ready' bit is set by OPAL. If the bit is set then OCC will set the 'OCC Progress' bit. 5. OCC will process the command and write the response to the OCC response buffer and set the 'Rsp Ready' bit in the response flag and sends an interrupt. 8. OPAL will receive the interrupt and queue the response to the host. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Fix comment around OPAL_IMC_COUNTERS_ enumMadhavan Srinivasan2017-07-171-1/+1
| | | | | | Fixes: 7801be0fcf2a2 ('skiboot: Add opal calls to init/start/stop IMC devices) Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* skiboot: Add opal calls to init/start/stop IMC devicesAnju T Sudhakar2017-06-271-1/+11
| | | | | | | | | | | | | | | | | | | | | | | Add new opal calls to init, start and stop the IMC nest/core units. To initialize the core IMC counters, it takes a physical address per core as an input and writes that address to PDBAR[14:50] bits. It initializes the htm_mode and event_mask, where it selects the time interval at which the counter values must be posted to the given memory location and enables the counters to start running by setting the appropriate bits. To disable/enable the nest IMC counters (stop or resume counting), writes into "command" field of the nest control block in the reserve memory location. To disable/enable the core IMC counters (stop or resume counting), writes into appropriate bits of htm_mode to disable the counters. Acked-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Hemant Kumar <hemant@linux.vnet.ibm.com> Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> [stewart@linux.vnet.ibm.com: use pr_fmt rather than hardcode IMC prefix] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Support setting HID[RADIX] and set it by default on P9Benjamin Herrenschmidt2017-06-261-0/+9
| | | | | | | | | | | | | | | | | This adds new opal_reinit_cpus() flags to setup radix or hash mode in HID[8] on POWER9. By default HID[8] will be set. On P9 DD1.0, Linux will change it as needed. On P9 DD2.0 hash works in radix mode (radix is really "dual" mode) so KVM won't break and existing kernels will work. Newer kernels built for hash will call this to clear the HID bit and thus get the full size of the TLB as an optimization. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* capi: Enable capi mode for PHB4Christophe Lombard2017-06-191-0/+1
| | | | | | | | | | | | | | | | Enable the Coherently attached processor interface. The PHB is used as a CAPI interface. CAPI Adapters can be connected to either PEC0 or PEC2. Single port CAPI adapter can be connected to either PEC0 or PEC2, but Dual-Port Adapter can be only connected to PEC2 CAPP0 attached to PHB0(PEC0 - single port) CAPP1 attached to PHB3(PEC2 - single or dual port) As we did for PHB3, a new specific file 'phb4-capp.h' is created to contain the CAPP register definitions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* SBE: Add passthrough command supportVasant Hegde2017-06-081-0/+4
| | | | | | | | | | | | SBE sends passthrough command. We have to capture this interrupt and send event to HBRT via opal-prd (user space daemon). This patch adds minimal SBE code to capture SBE interrupt and send event to opal-prd. Next patch will add opal-prd (user space) support. CC: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-prd: Add firmware_request & firmware_notify implementationsJeremy Kerr2017-06-061-0/+16
| | | | | | | | | This change adds the implementation of firmware_request() and firmware_notify(). To do this, we need to add a message queue, so that we can properly handle out-of-order messages coming from firmware. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Implement diag dataRussell Currey2017-04-191-2/+69
| | | | | | | | | Implement PHB4 diagnostic data, similar to PHB3. There are a few registers that have changed, but everything is largely the same. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Michael Neuling <mikey@neuling.org>
* npu2: Add OPAL calls for nvlink2 address translation servicesAlistair Popple2017-03-301-1/+4
| | | | | | | | | | | Adds three OPAL calls for interacting with NPU2 devices: opal_npu_init_context, opal_npu_destroy_context and opal_npu_map_lpar. These are used to setup and configure address translation services (ATS) for a process/partition on a given NVLink2 device. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add opal_xive_sync() to sync IRQ sources and queuesBenjamin Herrenschmidt2017-03-161-0/+7
| | | | | | | | For now support two sync options, source and target queue, we'll add sync'ing the presentation layer later. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* System reset IPI facility and Mambo implementationNicholas Piggin2017-03-071-1/+2
| | | | | | | | | | | | | Add an opal call OPAL_SIGNAL_SYSTEM_RESET which allows system reset exceptions to be raised on other CPUs and act as an NMI IPI. There is an initial simple Mambo implementation, but allowances are made for a more complex hardware implementation. This API is based on the POWER8 implementation from Alistair Popple. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart@linux.vnet.ibm.com: minor RST fix] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add some dump facilityBenjamin Herrenschmidt2017-02-231-2/+12
| | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Reserve OPAL API numbers for XIVEStewart Smith2017-01-161-1/+5
| | | | | | (requested by benh) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add *any chip* for allocating interruptsBenjamin Herrenschmidt2017-01-051-0/+5
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Add support for EOIs via OPALBenjamin Herrenschmidt2017-01-051-0/+1
| | | | | | | | | | | opal_xive_eoi() can perform EOIs in XIVE exploitation mode as well as XICS emulation mode. Add a per-interrupt flag requiring the OS to use the OPAL call instead of ESB access. This is meant to be used as a broken HW workaround Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/phb4: Work around broken LSI control on P9 DD1Benjamin Herrenschmidt2017-01-051-0/+1
| | | | | | | | | Exposes a new flag to the OS to indicate that OPAL calls are needed for masking and unmasking and forward the calls to the source so that PHB4 can do the right thing Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: Export opal_xive_reset() arguments in OPAL APIBenjamin Herrenschmidt2017-01-051-0/+9
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive/phb4: Handle bad ESB offsets in PHB4 DD1Benjamin Herrenschmidt2017-01-051-0/+1
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xive: OPAL API updateBenjamin Herrenschmidt2017-01-051-1/+35
| | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* platform: add OPAL_REBOOT_FULL_IPL reboot typeAndrew Donnellan2016-12-231-0/+1
| | | | | | | | | | There may be circumstances in which a user wants to force a full IPL reboot rather than using fast reboot. Add a new reboot type, OPAL_REBOOT_FULL_IPL, that disables fast reboot. On platforms which don't support fast reboot, this will be equivalent to a normal reboot. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Set PSSCR value for idle statesShilpasri G Bhat2016-12-131-0/+15
| | | | | | | | | | | | | | | | | | | | PSSCR(Processor Stop Status and Control Register) is an SPR whose contents control the operation of stop instruction. Currently in DT, the value of PSSCR only included RL(Requested Level) for each idle state. This patch adds MTL(Maximum Transistion Level), TR(Transistion Rate), ESL(Enable State Loss) and EC(Exit Criterion) bits for idle state in the PSSCR configuration. It also adds new idle states stop0_lite, stop1_lite and stop2_lite which are no state loss versions of stop0, stop1 and stop2 respectively. The lite variant has EC and ESL bits of PSSCR set to 0. The thread entering a lite variant of stop state will not lose any state and will wakeup at next instruction following stop if MSR.EE=0 or at the corresponding interrupt handler if MSR.EE=1. This will reduce the exit latency of the idle state and hardware will not allocate the thread resources to other threads while in power saving mode. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ/prd/opal-prd: Queue OCC_RESET event message to host in OpenPOWERShilpasri G Bhat2016-09-261-0/+1
| | | | | | | | | | | | | | | | | During an OCC reset cycle the system is forced to Psafe pstate. When OCC becomes active, the system has to be restored to its last pstate as requested by host. So host needs to be notified of OCC_RESET event or else system will continue to remian in Psafe state until host requests a new pstate after the OCC reset cycle. This patch defines 'OPAL_PRD_MSG_TYPE_OCC_RESET_NOTIFY' to notify OPAL when opal-prd issues OCC reset. OPAL will queue OCC_RESET message to host when it receives opal_prd_msg of type '*_OCC_RESET_NOTIFY'. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* centaur: Mark centaur offline after 10 consecutive access errorsBenjamin Herrenschmidt2016-09-131-0/+1
| | | | | | | | This avoids spamming the logs when the centaur is dead and PRD constantly tries to access it Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* xscom: Map all HMER status codes to OPAL errorsBenjamin Herrenschmidt2016-09-131-0/+7
| | | | | | | | | | Instead of mapping them to just 3 different codes, define an OPAL error code for all known HMER error status, as different recovery path might be needed at the call site, and it allows for more informative logging. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/cpu.c: Add OPAL call to setup Nest MMUAlistair Popple2016-09-061-1/+2
| | | | | | | | | | | | | | | POWER9 has an off core MMU called the Nest MMU which allows other units within a chip to perform address translations. The context and setup for translations is handled by the requesting agents, however the Nest MMU does need to know where in system memory the page tables are located. This patch adds a call to setup the Nest MMU page table pointer on a per-chip basis. Signed-off-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Balbir Singh <bsingharora@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add infrastructure for pointer validation.Balbir Singh2016-08-121-0/+3
| | | | | | | | | | | | | | If the kernel called an OPAL API with vmalloc'd address or any other address range in real mode, we would hit a problem with aliasing. Since the top 4 bits are ignored in real mode, pointers from 0xc.. and 0xd.. (and other ranges) could collide and lead to hard to solve bugs. This patch adds the infrastructure for pointer validation and a simple test case for testing the API Signed-off-by: Balbir Singh <bsingharora@gmail.com> [stewart@linux.vnet.ibm.com: move function to opal-internal.h rather than opal-api.h] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hw/phb4: Add initial supportBenjamin Herrenschmidt2016-07-081-2/+16
| | | | | | | | | | This adds the base support for the PHB4. It currently only support the M32 window, EEH or in general error recovery aren't supported yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: update (C) year, fix indenting] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* XIVE: Base XIVE support for OPAL XICS emulation callsBenjamin Herrenschmidt2016-07-081-4/+4
| | | | | | | | | | | | | This provides basic initialization of the XIVE along with some OPAL calls to emulate an old-style XICS which will initially be used by Linux for backward compatibility. The current implementation is limited to one priority and doesn't expose much to Linux for future exploitation mode yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [stewart@linux.vnet.ibm.com: add (C) header, fix whitespace, missing breaks] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Reserve OPAL API numbers for XICS emulation for XIVEStewart Smith2016-07-061-1/+5
| | | | | | | | | Additionally, we put in some skeleton docs for what's coming, key points being that this is for P9 and above, relies on a device being present in the device tree and is modelled on the PAPR calls. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Move macros associated with power-mgt nodes to opal-api.hShreyas B. Prabhu2016-06-201-2/+19
| | | | | | | | | Move macros associated with cpuidle fields of power-mgt device tree nodes to opal-api.h This patch does not change any functionality. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* slw: Add Power9 idle states to power-mgt dt nodeShreyas B. Prabhu2016-06-201-0/+10
| | | | | | | | | | | | | | | | | | | POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. This SPR subsumes PMICR. This patch adds the supported idle states to power-mgt dt node. It also introduces ibm,cpu-idle-state-psscr and ibm,cpu-idle-state-psscr-mask entries which exposes the value to be written to PSSCR to enter a given stop state. These entries replaces POWER8's counterparts ibm,cpu-idle-state-pmicr and ibm,cpu-idle-state-pmicr-mask. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/opal: Support PCI slot and new APIsGavin Shan2016-06-141-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The various reset requests are completed by PHB's callbacks. All of them (except reset on IODA table or error injection) are covered by PCI slot. opal_pci_poll() faces similar situation. This reimplements opal_pci_reset() and opal_pci_poll() based on the callbacks provided by PCI slot instead of PHB. Also, couple of new APIs are introduced based on the callbacks in PCI slot as below: * opal_pci_get_presence_state(): Check if there is adapter presented behind the specified PHB or PCI slot. * opal_pci_get_power_state(): Returns power supply state (on or off) on the specified PHB or PCI slot. * opal_pci_set_power_state(): Sets power supply state (on or off) on the specified PHB or PCI slot. Besides, the state can be (offline or online) without changing the PCI slot's power state. Eventually, the definition of unused PHB's callbacks are removed. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci: Support PCI slotGavin Shan2016-06-141-0/+10
| | | | | | | | | | | | | | | | | | | Every PCIE bridge port or PHB is expected to be bound with PCI slot , to which various PCI slot's functionalities are attached (e.g. power, link, reset). This supports PCI slot: * PCI slot is reprsented by "struct pci_slot". * "struct pci_slot_ops" represents the functions supported on the PCI slot. It's initialized by PCI slot core at the beginning and allowed to be overrided by platform partially or completely. * On PCI hot plugging event, the PCI devices behind the slot are enumarated. Device sub-tree is populated and sent to OS by OPAL message. * On PCI hot unplugging event, the PCI devices behind the slot are destroyed. Device sub-tree is removed and the slot is powered off. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/fdt: Introduce opal_get_device_tree()Gavin Shan2016-06-141-1/+2
| | | | | | | | | This introduces OPAL API opal_get_device_tree() to get the device sub-tree. It's going to be used in PCI hot add path. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb3: Add support for CAPP DMA modeIan Munsie2016-06-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The XSL used in the Mellanox CX4 card uses a DMA mode of CAPI, which requires a few registers configured specially. In addition to enabling the mode, - The CAPP only owns some of the PHB read buffers, and must be configured to use the correct ones, and the self-snoop configured for the same ones. - The tve needs to be configured to allow the card to access all kernel memory as it uses DMA accesses to read the scheduled process area from the kernel, among other things. These cannot be configured unconditionally, as doing so will break existing CAPI devices that do not use DMA mode. This adds a new mode to the OPAL_PCI_SET_PHB_CAPI_MODE API to enable CAPI in DMA mode. Since the snoop on/off modes write to the capi snoop configuration register, which is configured differently in DMA mode, it uses the redundant bits from the apc master powerbus control register to determine if it should configure the register for DMA mode rather than requiring any more permutations of the mode parameter. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-api: Fix typo in EPOW event handling descriptionVipin K Parashar2016-06-081-1/+1
| | | | | | | Fix typo in EPOW event handling description in include/opal-api.h. Signed-off-by: Vipin K Parashar <vipin@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* hmi: Add handling for NPU checkstopsRussell Currey2016-03-311-0/+1
| | | | | | | | | | | | | | | | | | If the NPU detects an unrecoverable error, it will send a HMI. This is problematic since unhandled HMIs will checkstop the entire system, which is not the intended behaviour of a NPU failure. Instead, the NPU emulated PCI devices should be fenced as part of EEH. Add support for handling NPU HMIs. This works by finding the NPU responsible for the HMI, checking its error registers, and sending a recoverable HMI event. The NPU itself cannot actually recover, but the system should not be brought down. Fence mode is set on the NPU, such that any further operations on the NPU will trigger EEH, and it will be subsequently fenced from the system. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Add OPAL_CONSOLE_FLUSH to the OPAL APIRussell Currey2016-01-121-1/+2
| | | | | | | | | | | | | | | | | | | | | uart consoles only flush output when polled. The Linux kernel calls these pollers frequently, except when in a panic state. As such, panic messages are not fully printed unless the system is configured to reboot after panic. This patch adds a new call to the OPAL API to flush the buffer. If the system has a uart console (i.e. BMC machines), it will incrementally flush the buffer, returning if there is more to be flushed or not. If the system has a different console, the function will have no effect. This will allow the Linux kernel to ensure that panic message have been fully printed out. The existing synchronous flushing mechanism used in OPAL's shutdown and reboot routines has been refactored into a helper that repeatedly calls the new partial flush function. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-api: Assign numbers to OPAL_MSG macros of enum opal_msg_typeVipin K Parashar2015-09-011-8/+8
| | | | | | | | | | | | | This patch assigns numbers to OPAL_MSG macros of enum opal_msg_type to prevent accidental insertion of any new value in between and thus break OPAL API. This is also helpful while backporting mainline kernel changes to distros which run downlevel kernel and thus don't have all OPAL messages defined, avoiding unnecessary bugs due to enum values order mismatch. Signed-off-by: Vipin K Parashar <vipin@linux.vnet.ibm.com> Acked-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Fix spelling mistakesStewart Smith2015-08-261-1/+1
| | | | | | See https://github.com/lucasdemarchi/codespel Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal-api: Add OPAL call to handle abnormal reboots.Vipin K Parashar2015-07-311-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new OPAL call OPAL_CEC_REBOOT2 which will be used to handle abnormal reboot/termination by kernel host. This call will allow host kernel to pass reboot type and additional debug data which needs to be captured/saved somewhere (for later analysis) before going down. Currently it will support two reboot types (0). normal reboot, that will behave similar to that of opal_cec_reboot() call, and (1). platform error reboot, that will trigger a system checkstop using xscom address and FIR bit information obtained via device-tree property 'ibm,sw-checkstop-fir'. For unsupported reboot type, this call will do nothing and return with OPAL_UNSUPPORTED. In future, we can overload this call to support additional reboot types. Signed-off-by: Vipin K Parashar <vipin@linux.vnet.ibm.com> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam.mj@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* occ: Poll OCC throttle status and queue OCC events to hostShilpasri G Bhat2015-07-061-0/+25
| | | | | | | | | | | | | | | | | Add a new class of message definition OPAL_MSG_OCC to opal_message_type to notify the following OCC events to host: 1) OCC Reset 2) OCC Load 3) OCC Throttle Status Change Add an opal poller to periodically read throttle status updated by OCC for each chip and notify any change in throttle status to host. The throttle status indicates the reason why OCC may have limited the max Pstate of the chip. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Reviewed-by: Preeti U Murthy <preeti@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Merge PRD rework from stableStewart Smith2015-05-211-3/+8
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| * prd: Don't expose full opal_prd_msg to kernelJeremy Kerr2015-05-211-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | The kernel is only accessing part of struct opal_prd_msg, and doesn't need to know about the rest. This change moves the "internal" parts of opal_prd_msg to a separate header. In order for the kernel to pass full messages between userspace and firmware, it needs the total size of the struct. We put this in the header for the kernel to access. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* | FSP/LED: Add system attention indicator supportVasant Hegde2015-05-071-1/+2
|/ | | | | | | | | | | | | | | | SAI is controlled by FSP. This patch adds support to get/set this indicator. Also update OPAL interface so that playload can read/set this indicator. During init, we read this indicator state using MBOX command. OPAL uses MBOX interface to update this SAI. FSP sends update notification whenever there is change in SAI state (except for OPAL initiates updates). We use the notification to update cached SAI state. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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