| Commit message (Collapse) | Author | Age | Files | Lines |
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There are significant changes to hardware register addresses and
meanings on newer chip revisions making them unlikely to work
correctly with the existing code. Better to fail clearly and early.
Suggested-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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NPU2 BARs were being assigned and tracked with a global static
array. This worked fine when there was only a single chip/NPU2 in the
system however multiple chips results in the a shared data structure
for BAR management which results in multiple chips getting assigned
the same BAR addresses and other incorrect sharing of BAR properties.
This patch splits the static and dynamic BAR configuration and stores
the dynamic configuration in the per-NPU2 data structure.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The arguments to npu2_scom_write() in npu2_write_bar() resulting in
incorrect BAR setup in some circumstances. This patch swaps the
arguments so they are correct.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Trigging a Host Initiated Reset (when the host detects the FSP has gone
out to lunch and should be rebooted), would cause "Unknown Command" messages
to appear in the OPAL log.
This patch implements those messages
How to trigger FSP RR(HIR):
$ putmemproc 300000f8 0x00000000deadbeef
s1 k0:n0:s0:p00
ecmd_ppc putmemproc 300000f8 0x00000000deadbeef
Log showing unknown command:
/ # cat /sys/firmware/opal/msglog | grep -i ,3
[ 110.232114723,3] FSP: fsp_trigger_reset() entry
[ 188.431793837,3] FSP #0: Link down, starting R&R
[ 464.109239162,3] FSP #0: Got XUP with no pending message !
[ 466.340598554,3] FSP-DPO: Unknown command 0xce0900
[ 466.340600126,3] FSP: Unhandled message ce0900
The message we need to handle is "Get PLID after host initiated FipS
reset/reload". When the FSP comes back from HIR, it asks "hey, so, which
error log explains why you rebooted me?". So, we tell it.
Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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phb4_get_presence_state() needs to set *val to indicate the presence
of something in the slot. Currently it doesn't set *val at all.
The existing logic is correct, so this patch just sets val in the
right places.
This has the nice side effect of improving boot times since we no
longer waste time tring to train links that don't have anything
present.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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NPU and NPU2 don't use diag data, but the kernel will allocate a buffer for
NPU PHBs regardless. Set ibm,phb-diag-data-size to 0 for NPU PHBs to save a
whole precious 8K.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Acked-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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A HW issue can cause accesses to the content of the indirect data
area to pass the actual selection of the target thread. The
workaround is to read the PC_TCTXT_INDIR0 register back before
accessing the data area.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add a counter of total interrupts taken by a CPU, dump the
queue buffer both before and after the current pointer,
and also display the HW state of the queue descriptor and
the PQ state of the IPI.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This is a small 32-entries rolling buffer that logs a few
operations. It's useful to debug odd problems. The output
is printed when opal_xive_dump() is called.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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There should never be duplicate interrupts in a queue.
This adds code to check that when looking at the queue
content. Since it can be a performance loss, this is only
done for debug builds.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Linux hardcodes the PHB diag data buffer at (as of this commit) 8192 bytes.
This has been enough for P7IOC and PHB3, but the 512 PEs of PHB4 pushes
the diag data blob over this size. Rather than just increasing the
hardcoded size in Linux, provide the size of the diag data blob in the
device tree so that the OS can dynamically allocate as much as it needs.
This both enables more space for PHB4 and less wasted memory for P7IOC
and PHB3.
P7IOC communicates both hub and PHB data using this buffer, so when
setting the size, use whichever struct is largest.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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We currently don't expose the trigger page of MSIs to Linux which
breaks re-sending of a queued one. To fix that properly we need
to understand out a subtle API complication:
- The "internal" XIVE_SRC_TRIGGER_PAGE indicates that a trigger
page is supported, whether it's the same page as the EOI page
or not.
- The "external" OPAL_XIVE_IRQ_TRIGGER_PAGE indicates that a
*separate* trigger page exists. To know if triggers are supported
the caller should simply check if a valid (non-0) value is returned
in "out_trig_page" of opal_xive_get_irq_info().
So PHB4 must set XIVE_SRC_TRIGGER_PAGE for MSIs and the xive code
needs to do the "right" thing for setting whether
OPAL_XIVE_IRQ_TRIGGER_PAGE should be set or not.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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There's a new field in the command register to control where
to steer the interrupt. Set it always, these are unused bits
on P8 so shouldn't hurt.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This hack dates back to ancient P8 hostboots. The value
it would use if it detected the "bad" value was incorrect
anyway.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Since it's a non-trivial derivation from HDAT values,
it's useful to log it for diagnostics.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Log more registers, cleanup the output alignment,
and timestamp start/stop of requests
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Skiboot should only send PRD messages to the host kernel if the platform
has enabled opal-prd. This is done via overwriting a function pointer
when the PRD is enabled, but this can be replaced with a simple if check.
Cc: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The IPOLL register addresses have changed from P8.
Also indicate what the specific register bits are for in the #defines.
Signed-off-by: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com>
[Moved inline into prd_init and added a default case -oliver]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This sets up the per chip RNG MMIO BAR and points the per core DARN
BAR at it.
This is needed on P9 to enabled the DARN instruction (otherwise it'll
cause a xstop).
This includes a minor rework of some #defines to abstract MMIO
definitions.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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As the comment in npu_dev_populate_pcie_cap() says,
"We should support FLR" and the NPU device advertises its
support. However, when the kernel issues FLR, skiboot does
nothing which leaves NPU in a state which does not allow
to use NV links again after GPU was reset.
This adds basic handling of FLR (function level reset).
This does not update hreset/freset handlers as they are not going to be
called under any circumstance - EEH is not supported for NPU and
the kernel won't issue OPAL reset otherwise.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Acked-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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If some status interrupts are left unmasked by a previous
firmware run (either HostBoot or some other version of skiboot),
we fail to clear them and end up with a runaway SerIRQ.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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We don't trigger the IPI in set_mfrr() if the CPPR of the
destination is more favored than the MFRR. However, we fail
to re-evaluate it when the CPPR later changes.
This fixes it. The way this is implemented can lead to
spurious IPIs but these are harmless.
(Mikey remove bogus line setting xs->ipi_sent)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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Some interrupts source such as PSI serirq have a special EOI override.
That override will perform the PQ bit EOI operation, so we must not
do a second one in xive_source_eoi().
This bug can cause queue overflows, especially when dealing with
runaway level interrupts.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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PHB4 is currently configured to use half the available PEs due to DD1
limitations, with windows configured to allocate two segments per PE.
phb4_map_pe_mmio_window() currently expects segment numbers to map one-to-one
with PE numbers, so correct phb_map_pe_mmio_window() to use the two-to-one
mapping.
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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Now that fence detection is implemented, EEH for MMIO can be turned on.
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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Fence detection is missing in PHB4, so implement it. The mechanism is the
exact same as in PHB3.
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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Implement PHB4 diagnostic data, similar to PHB3. There are a few
registers that have changed, but everything is largely the same.
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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When resetting, we need to clear the emulation mode queue
for each CPU, otherwise it may contain "stale" interrupts
causing the OS to go completely out of sync.
This fixes problems doing kexecs from emulation to native
back to emulation.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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On such systems, we really need to mask all the sources first,
then synchronize all the XIVEs, before we start whacking their
EQs, VPs etc...
So this reworks the reset sequence to do that, using the new
irq_for_each_source() iterator to get all the registered sources
into a clean off state, and separating the sync pass from the
reset pass.
This also fixes a problem where the ipi_alloc_map wasn't being
properly reset.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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After all IRQs have been masked, sync the XIVE HW before we
start disabling all the queues.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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This patch fixes the SCOM address for OCC_MISC register which is used
for OCC interupts. In P9, OCC sends an interrupt to notify change in
the shared memory like throttle status. This patch handles this
interrupt reason.
Originally-from: Michael Neuling <mikey@neuling.org>
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
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Unlike the other remote VSDs, the NVT one needs a valid size field
that represents the size of the remote PC BAR. Without this, multi
chip machines may checkstop when a processor pool or OS CAM gets
attached to a VP on a different chip.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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As the ECRC is updated properly on root port, we needn't care the
setting on endpoints. This reverts commit 60ce59ccd0e9 ("hw/phb3:
Disable ECRC on Broadcom adapter behind PMC switch"), meaning ECRC
is always enabled on endpoints.
Reported-by: Mark E Schreiter <markes@us.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Tested-by: Mark E Schreiter <markes@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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The issue was reported by Mark: the Samsung NVMe adapter is lost
when it's connected to PMC 8546 PCIe switch, until ECRC is disabled
on the root port. Actually, we found similar issue prevously when
Broadcom adapter is connected to same part of PCIe switch and it
was fixed by commit 60ce59ccd0e9 ("hw/phb3: Disable ECRC on Broadcom
adapter behind PMC switch"). Unfortunately, the commit doesn't fix
the Samsung NVMe adapter lost issue.
This fixes the issues by disable ECRC generation/check on root port
when PMC 8546 PCIe switch ports are found. This can be extended for
other PCIe switches or endpoints in future: Each PHB maintains the
count of PCI devices (PMC 8546 PCIe switch ports currently) which
require to disable ECRC on root port. The ECRC functionality is
enabled when first PMC 8546 switch port is probed and disabled when
last PMC 8546 switch port is destroyed (in PCI hot remove scenario).
Except PHB's reinitialization after complete reset, the ECRC on
root port is untouched.
Reported-by: Mark E Schreiter <markes@us.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Tested-by: Mark E Schreiter <markes@us.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This adds another PHB callback (device_remove()), corresponding to
device_init(). With it, the PHB3 layer can receive notification
upon PCI topology changes. This functionality will be used by the
subsequent patches.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Similar to PHB3, phb4_init_rc_cfg() can be called when the PHB is
initialized or reinitialized after complete reset. In the later case,
we needn't locate the AER capability position again and the cached
position can be used as we do for PCIe capability. So several CPU
cycles can be saved. The error message is shortened and meaningless
comment is dropped as well.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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phb3_init_rc_cfg() can be called when the PHB is initialized or
reinitialized after complete reset. In the later case, we needn't
locate the AER capability position again and the cached position
can be used as we do for PCIe capability. So several CPU cycles
can be saved. The error message is shortened and meaningless
comment is dropped.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This patch adds new function to init core for power9 power management.
SPECIAL_WKUP_* SCOM registers, if set, can hold the cores from going into
idle states. Hence, clear PPM_SPECIAL_WKUP_HYP_REG scom register for each
core during init. (This init are not required for MAMBO)
Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com>
Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Unlike other system buses the NVLink2 links need to be trained at
runtime as training requires interaction from the GPU device
drivers. This patch implements the required training procedures for
NVLink2, which are different than the NVLink1 equivalents.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Adds three OPAL calls for interacting with NPU2 devices:
opal_npu_init_context, opal_npu_destroy_context and opal_npu_map_lpar.
These are used to setup and configure address translation services
(ATS) for a process/partition on a given NVLink2 device.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Allocate memory for the GPU vidmem aperture and create "memory@" dt
nodes to describe GPU memory with a phandle in each pointing to the
emulated PCI device.
Also provide the compressed 47-bit device address in
"ibm,device-tgt-addr".
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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NVLink2 is a new feature introduced on POWER9 systems. It is an
evolution of of the NVLink1 feature included in POWER8+ systems but
adds several new features including support for GPU address
translation using the Nest MMU and cache coherence.
Similar to NVLink1 the functionality is exposed to the OS as a series
of virtual PCIe devices. However the actual hardware interfaces are
significantly different which limits the amount of common code that
can be shared between implementations in the firmware.
This patch adds basic hardware initialisation and exposure of the
virtual NVLink2 PCIe devices to the running OS.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Default to PCIe GEN2 link speeds on DD1 for stability.
Can be overridden using nvram pcie-max-link-speed=4 parameter.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This adds an nvram parameter pcie-max-link-speed to configure the max
speed of the pcie link. This can be set from the petitboot prompt
using:
nvram -p ibm,skiboot --update-config pcie-max-link-speed=4
This takes preference over anything set in the device tree and is
global to all PHBs.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add code to perform indirect form 1 scoms.
POWER8 does form 0 only. POWER9 adds form 1. The form is determined
from the address only. Hardware only allows writes for form 1.
Only hostboot uses these scoms during IPL, so they are unused by
skiboot currently.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Indirect scoms can only set certain bits of data. Ensure only these
are set when trying to write.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Add scom reset registers for POWER9.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Abstract error recovery registers to get ready for POWER9.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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PBA BARs map various regions in HOMER memory used by STOP engines and
OCC. Skip PBA BARs that have incomplete initialization and reserve the
regions that are available in the system.
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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