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* core/bitmap: Test bitmap foreach functionsStewart Smith2017-11-281-0/+11
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Shared slot state synchronisation for hot resetRussell Currey2017-11-211-0/+14
| | | | | | | | | | When a device is shared between two PHBs, it doesn't get reset properly unless both PHBs issue a hot reset at "the same time". Practically this means a hot reset needs to be issued on both sides, and neither should bring the link up until the reset on both has completed. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Track peers of slotsRussell Currey2017-11-211-0/+1
| | | | | | | | | Witherspoon introduced a new concept where one physical slot is shared between two PHBs. Making a slot aware of its peer enables syncing between them where necessary. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/direct-controls: add function to read core gated stateRobert Lippert2017-11-201-0/+21
| | | | | | Change-Id: Ib534503f2528de4d8b1633d9859ae9ff5d010f98 Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/direct-controls: wait for core special wkup bit clearedRobert Lippert2017-11-201-1/+22
| | | | | | | | | | | | | | | When clearing special wakeup bit on a core, wait until the bit is actually cleared by the hardware in the status register until returning success. This may help avoid issues with back-to-back reads where the special wakeup request is cleared but the firmware is still processing the request and the next attempt to set the bit reads an immediate success from the previous operation. Change-Id: I86ec8cbbbddd1a5724f451244907693bc09e01ea Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* sensors: dts: Assert special wakeup on idle cores while reading temperatureShilpasri G Bhat2017-11-202-3/+3
| | | | | | | | | | | | In P9, when a core enters a stop state, its clocks will be stopped to save power and hence we will not be able to perform a scom operation to read the DTS temperature sensor. Hence, assert a special wakeup on cores that have entered a stop state in order to successfully complete the scom operation. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> [rlippert@google.com: Clear special wakeup only when it succeeds] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pcie-slots: Fix coverity possible NULL dereferenceCyril Bur2017-11-131-2/+3
| | | | | | | | | | | Coverity has found a senario where there could be a NULL dereference, it is likely that in practice we wouldn't hit this. Coverity does point out that all other callers of pcie_slot_create() do check for the NULL return, as such it makes sense to add a check. Fixes: CID 173756 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal/hmi: Workaround Power9 hw logic bug for couple of TFMR TB errors.Mahesh Salgaonkar2017-10-231-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | Add a workaround for a HW logic bug in Power9 where TB residue and HDEC parity errors cleared by one thread aren't visible to other threads of same core. The TB reside and HDEC parity error are reported through TFMR bit 45 and 26 respectively. If any of the thread from the core clears the TFMR bit 26 and 45, only thread 0 is able to see that errors are cleared but rest of the threads 1, 2 and 3 do not see those as cleared. This causes TB error recovery to fail for TB residue and HDEC parity errors. TFMR is per core register and any changes made by a one thread should be visible by other threads of the same core. On TB residue error (TFMR bit 45), TB goes into invalid state. Hence avoid handling/clearing TB residue error if TB is valid and running. Use TFMR bit 41 to check validity of TB state. For HDEC parity error (TFMR bit 26), check for other errors on TFMR register and ignore the pre-recovery for HDEC parity error. If TFMR has any other TB error bits set alongwith HDEC parity error we can safely ignore handling of HDEC parity error. Also, while clearing HDEC parity error bit from TFMR, allow only thread 0 to clear it. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal/hmi: Fix TB reside and HDEC parity error recovery for power9Mahesh Salgaonkar2017-10-231-3/+102
| | | | | | | | | | | On TB/HDEC errors, all 4 threads on the affected receives HMI. On power9, every thread on the core has its own copy of TB/HDEC and hence every thread has to clear the dirty data from its own TB/HDEC register before we clear tb errors through TFMR[24]. The HMI recovery would fail even if one thread do not cleanup the respective TB/HDEC register. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core: direct-controls: Fix clearing of special wakeupShilpasri G Bhat2017-10-181-1/+4
| | | | | | | | | | 'special_wakeup_count' is incremented on successfully asserting special wakeup. So we will never clear the special wakeup if we check 'special_wakeup_count' to be zero. Fix this issue by checking the 'special_wakeup_count' to 1 in dctl_clear_special_wakeup(). Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/direct-controls: increase special wakeup timeout on POWER9Nicholas Piggin2017-10-181-3/+6
| | | | | | | | | | Some instances have been observed where the special wakeup assert times out. The current timeout is too short for deeper sleep states. Hostboot uses 100ms, so match that. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Acked-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: Add OPAL_REINIT_CPUS_TM_SUSPEND_DISABLEDMichael Ellerman2017-10-161-0/+10
| | | | | | | | | | | | | Add a new CPU reinit flag, "TM Suspend Disabled", which requests that CPUs be configured so that TM (Transactional Memory) suspend mode is disabled. Currently this always fails, because skiboot has no way to query the state. A future hostboot change will add a mechanism for skiboot to determine the status and return an appropriate error code. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* opal/cpu: Mark the core as bad while disabling threads of the core.Mahesh Salgaonkar2017-10-151-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If any of the core fails to sync its TB during chipTOD initialization, all the threads of that core are disabled. But this does not make linux kernel to ignore the core/cpus. It crashes while bringing them up with below backtrace: [ 38.883898] kexec_core: Starting new kernel cpu 0x0: Vector: 300 (Data Access) at [c0000003f277b730] pc: c0000000001b9890: internal_create_group+0x30/0x304 lr: c0000000001b9880: internal_create_group+0x20/0x304 sp: c0000003f277b9b0 msr: 900000000280b033 dar: 40 dsisr: 40000000 current = 0xc0000003f9f41000 paca = 0xc00000000fe00000 softe: 0 irq_happened: 0x01 pid = 2572, comm = kexec Linux version 4.13.2-openpower1 (jenkins@p89) (gcc version 6.4.0 (Buildroot 2017.08-00006-g319c6e1)) #1 SMP Wed Sep 20 05:42:11 UTC 2017 enter ? for help [c0000003f277b9b0] c0000000008a8780 (unreliable) [c0000003f277ba50] c00000000041c3ac topology_add_dev+0x2c/0x40 [c0000003f277ba70] c00000000006b078 cpuhp_invoke_callback+0x88/0x170 [c0000003f277bac0] c00000000006b22c cpuhp_up_callbacks+0x54/0xb8 [c0000003f277bb10] c00000000006bc68 cpu_up+0x11c/0x168 [c0000003f277bbc0] c00000000002f0e0 default_machine_kexec+0x1fc/0x274 [c0000003f277bc50] c00000000002e2d8 machine_kexec+0x50/0x58 [c0000003f277bc70] c0000000000de4e8 kernel_kexec+0x98/0xb4 [c0000003f277bce0] c00000000008b0f0 SyS_reboot+0x1c8/0x1f4 [c0000003f277be30] c00000000000b118 system_call+0x58/0x6c Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* ipmi: Convert common debug prints to traceVasant Hegde2017-10-101-2/+2
| | | | | | | | | | | | | | | OPAL logs messages for every IPMI request from host. Sometime OPAL console is filled with only these messages. This path is pretty stable now and we have enough logs to cover bad path. Hence lets convert these debug message to trace/info message. [ 1356.423958816,7] opal_ipmi_recv(cmd: 0xf0 netfn: 0x3b resp_size: 0x02) [ 1356.430774496,7] opal_ipmi_send(cmd: 0xf0 netfn: 0x3a len: 0x3b) [ 1356.430797392,7] BT: seq 0x20 netfn 0x3a cmd 0xf0: Message sent to host [ 1356.431668496,7] BT: seq 0x20 netfn 0x3a cmd 0xf0: IPMI MSG done Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci-iov: free memory across fast-rebootStewart Smith2017-10-102-4/+19
| | | | | | | | | | | | | | pci_set_cap needs a callback to free data and we need to call that when we're doing __pci_reset() We also need to free pcrf entries. In the future, __pci_reset() and pci_remove_bus() need to come together to be one canonical place on how to free a PCI device rather than the two we have now. This patch *purely* focuses on the problem of not leaking memory across fast-reboot. Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* fast-reset: by default (if possible)Stewart Smith2017-10-061-2/+2
| | | | Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* i2c: Move tpm i2c wrapper code into coreAndrew Donnellan2017-10-021-0/+107
| | | | | | | | | | | | | The TPM code has a wrapper around the main i2c API to allow synchronous use. Move it into core/i2c.c so it can be used by other possible users. In particular, a future patch will use this to drive OpenCAPI device resets during boot time. Cc: Claudio Carvalho <cclaudio@linux.vnet.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: idle POWER9 power management implementationNicholas Piggin2017-09-282-4/+121
| | | | | | | | | | | | Add pm idle support to POWER9. IPIs are implemented with doorbells. POWER9 can use the EC=ESL=0 (lite) stop when sreset is not available. EC=ESL=1 state with RL=3 is enabled when we have a sreset wakeup. Deep idle states are not implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: idle split pm enable into sreset and ipi componentsNicholas Piggin2017-09-283-36/+68
| | | | | | | | pm idle requires the system reset vector and IPI facilities before it can be enabled. Split these out and manage them individually. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: idle notice if pm state changesNicholas Piggin2017-09-281-4/+18
| | | | | | | | | The idle code checks pm_enabled once at entry, then not again until the idle exit condition is met. Change this to check each opportunity and change idle type if necessary. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: idle move the minimum PM latency into the idle codeNicholas Piggin2017-09-282-4/+3
| | | | | | | | | The caller isn't in a position to know about PM heuristics, so move the minimum timeout before power managmeent into the cpu idle call. There is no functional change. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* cpu: avoid decrementer wakeups in case of cpu_wake_on_job idleNicholas Piggin2017-09-281-8/+7
| | | | | | | | Rather than setting decrementer to max in the case we want to ignore it, just don't set it as a wakeup reason the in LPCR. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core: POWER9 implement OPAL_SIGNAL_SYSTEM_RESETNicholas Piggin2017-09-204-1/+417
| | | | | | | | | | | | | | This implements OPAL_SIGNAL_SYSTEM_RESET, using scom registers to quiesce the target thread and raise a system reset exception on it. It has been tested on DD2 with stop0 ESL=0 and ESL=1 shallow power saving modes. DD1 is not implemented because it is sufficiently different as to make support difficult. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [stewart@linux.vnet.ibm.com: fixup hdat_to_dt test] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/flash: Only expect ELF header for BOOTKERNEL partition flash resourceSuraj Jitindar Singh2017-09-191-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When loading a flash resource which isn't signed (secure and trusted boot) and which doesn't have a subpartition, we assume it's the BOOTKERNEL since previously this was the only such resource. Thus we also assumed it had an ELF header which we parsed to get the size of the partition rather than trusting the actual_size field in the FFS header. A previous commit (9727fe3 DT: Add ibm,firmware-versions node) added the version resource which isn't signed and also doesn't have a subpartition, thus we expect it to have an ELF header. It doesn't so we print the error message "FLASH: Invalid ELF header part VERSION". It is a fluke that this works currently since we load the secure boot header unconditionally and this happen to be the same size as the version partition. We also don't update the return code on error so happen to return OPAL_SUCCESS. To make this explicitly correct; only check for an ELF header if we are loading the BOOTKERNEL resource, otherwise use the partition size from the FFS header. Also set the return code on error so we don't erroneously return OPAL_SUCCESS. Add a check that the resource will fit in the supplied buffer to prevent buffer overrun. Fixes: 9727fe3 (DT: Add ibm,firmware-versions node) Reported-by: Pridhiviraj Paidipeddi <ppaidipe@linux.vnet.ibm.com> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci-slots: Move slot-label construction to a helperOliver O'Halloran2017-09-151-0/+30
| | | | | | | | Move this out of the astbmc specific part into a generic helper. This allows us to use it more commonly. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pcie-slots: Make dynamic slot creation genericOliver O'Halloran2017-09-151-0/+51
| | | | | | | | | | | astbmc has some code to handle devices that are behind a "slot" on a riser card that can't be added to the static slot tables for a system. We probably want to use this code outside the slot table handling so move it somewhere generic and rework it so slot table specifics aren't buried inside it. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/pci-dt-slot: Represent PCIe slots in the devicetreeOliver O'Halloran2017-09-152-0/+231
| | | | | | | | | | | In P9 we get information about the physical PCIe slot topology through the HDAT. As a rule we never directly consume the HDAT inside of Skiboot and we always parse and incorporate the data from HDAT into the Skiboot device tree. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> [stewart@linux.vnet.ibm.com: add (C) header] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Make pci_wait_crs() globalMichael Neuling2017-09-121-1/+1
| | | | | | | We are going need pci_wait_crs() in the PHB4 code so make it global. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* flash: Support adding the no-erase property to flashWilliam A. Kennington III2017-09-051-0/+4
| | | | | | | | | | | | | | | | | | | The mbox protocol explicitly states that an erase is not required before a write. This means that issuing an erase from userspace, through the mtd device, and back returns a successful operation that does nothing. Unfortunately, this makes userspace tools unhappy. Linux MTD devices support the MTD_NO_ERASE flag which conveys that writes do not require erases on the underlying flash devices. We should set this property on all of our devices which do not require erases to be performed. NOTE: This still requires a linux kernel component to set the MTD_NO_ERASE flag from the device tree property. Signed-off-by: William A. Kennington III <wak@google.com> Reviewed-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> [stewart@linux.vnet.ibm.com: slightly reword commit msg based on Suraj's comments] Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* DT: Add ibm,firmware-versions nodeVasant Hegde2017-09-041-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | In P8, hostboot provides mini device tree. It contains /ibm,firmware-versions node which has various firmware component version details. In P9, OPAL is building device tree. This patch adds support to parse VERSION section of PNOR and create "/ibm,firmware-versions" device tree node. Sample output: /sys/firmware/devicetree/base/ibm,firmware-versions # lsprop . occ "6a00709" skiboot "v5.7-rc1-p344fb62" buildroot "2017.02.2-7-g23118ce" capp-ucode "9c73e9f" petitboot "v1.4.3-p98b6d83" sbe "02021c6" open-power "witherspoon-v1.17-128-gf1b53c7-dirty" .... .... Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Mukesh Ojha <mukesh02@linux.vnet.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* init: add missing sync_icache after exception vector patchingNicholas Piggin2017-09-041-0/+2
| | | | | | | | There are two cases where sync_icache is not called immediately after instructions are modified. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* gcov: support GCC 7.1+Stewart Smith2017-08-241-0/+5
| | | | | | __gcov_exit() was added in GCC 7.1 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/test/run-msg: don't depend on unittest mem layoutStewart Smith2017-08-241-1/+1
| | | | | | In the world of unit tests all "RAM" is valid Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/test/run-device: fix memory leak on exitStewart Smith2017-08-241-0/+1
| | | | | | Shuts LeakSanitizer up Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* test/mem_region: fix incorrect ibm,os-reserve region lengthStewart Smith2017-08-242-4/+4
| | | | | | | | | | | We were reserving all of memory up to the heap, which is fine *unless* the system libc chooses to allocate something in that block of memory that we use, which means we have overlapping regions and general pain. This should fix failing unit tests on some systems (e.g. Debian) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* Fix mem leak in core/test/run-time-utilsStewart Smith2017-08-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Fixes the following LeakSanitizer errors: ================================================================= ==32426==ERROR: LeakSanitizer: detected memory leaks Direct leak of 56 byte(s) in 1 object(s) allocated from: #0 0x7fd94a1fa850 in malloc (/lib64/libasan.so.4+0xde850) #1 0x4014d4 in main core/test/run-time-utils.c:30 #2 0x7fd94904c509 in __libc_start_main (/lib64/libc.so.6+0x20509) Direct leak of 8 byte(s) in 1 object(s) allocated from: #0 0x7fd94a1fa850 in malloc (/lib64/libasan.so.4+0xde850) #1 0x4014f0 in main core/test/run-time-utils.c:32 #2 0x7fd94904c509 in __libc_start_main (/lib64/libc.so.6+0x20509) Direct leak of 4 byte(s) in 1 object(s) allocated from: #0 0x7fd94a1fa850 in malloc (/lib64/libasan.so.4+0xde850) #1 0x4014e2 in main core/test/run-time-utils.c:31 #2 0x7fd94904c509 in __libc_start_main (/lib64/libc.so.6+0x20509) Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Move core/vas.c -> hw/vas.cMichael Neuling2017-08-222-449/+0
| | | | | | | It's hardware after all... Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Set FIRs according to workbookMichael Neuling2017-08-221-11/+5
| | | | | | | | | | | This sets the FIR, FIR mask and FIR action registers according to VAS workbook v1.20. It also renames them to make it clear what they are. Without this any VAS error will checkstop the machine, rather than potentially be recoverable. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* VAS: Remove misleading printMichael Neuling2017-08-211-2/+1
| | | | | | | | | | If there are no VAS nodes in the device tree we will still print this misleading message. Chips are already printed as they are inited. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Wait for CRS and switch link when restoring bus numbersRussell Currey2017-08-211-13/+38
| | | | | | | | | | | | | | | | | | | | When a complete reset occurs, after the PHB recovers it propagates a reset down the wire to every device. At the same time, skiboot talks to every device in order to restore the state of devices to what they were before the reset. In some situations, such as devices that recovered slowly and/or were behind a switch, skiboot attempted to access config space of the device before the link was up and the device could respond. Fix this by retrying CRS until the device responds correctly, and for devices behind a switch, making sure the switch has its link up first. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Tested-by: Hari Bathini <hbathini@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Trivial typo fixesRussell Currey2017-08-211-2/+2
| | | | | | Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* pci: Track whether a PCI device is a virtual functionRussell Currey2017-08-212-0/+2
| | | | | | | | | | This can be checked from config space, but we will need to know this when restoring the PCI topology, and it is not always safe to access config space during this period. Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Set mmio enable bits in DD2Sukadev Bhattiprolu2017-08-211-0/+3
| | | | | | | | | POWER9 DD2 added some new "enable" bits that must be set for VAS to work. These bits were unused in DD1. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Acked-By: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/mem_region: Check return value of add_region() (CID 147251)Cyril Bur2017-08-151-1/+5
| | | | | | | | | Just print an error if a region failed to add - at least then there will be a trace somewhere about the problem. Fixes: CID 147251 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/hmi: Fix use of uninitialised value (CID 147808)Cyril Bur2017-08-151-3/+3
| | | | | | | | | | | | | A rework of where some of the xscom regs are for POWER9 has resulted in a scope issue where the same line attempts to simultaneously reference a variable by the same name in global and function scope. Change the value read by xscom_read to *_val Fixes: CID 147808 Fixes: bda5e0ea Fix scom addresses for power9 nx checkstop hmi handling. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* core/flash core/init: Fix unintended sign extensionCyril Bur2017-08-152-4/+6
| | | | | | | | | | | | | | | | | According to Coverity: le16_to_cpu(elf64->e_shnum) is promoted in `le16_to_cpu(elf64->e_shentsize) * le16_to_cpu(elf64->e_shnum)` to type int (32 bits, signed), then sign-extended to type unsigned long long (64 bits, unsigned). If `le16_to_cpu(elf64->e_shentsize) * le16_to_cpu(elf64->e_shnum)` is greater than 0x7FFFFFFF, the upper bits of the result will all be 1. I'm sure in practice this can't happen since this would require either/or e_shnum and e_shentsize to be quite large. Fixes: CID 138019, 137707, 137706, 137708 Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* phb4: Enable PCI peer-to-peerFrederic Barrat2017-08-041-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | P9 supports PCI peer-to-peer: a PCI device can write directly to the mmio space of another PCI device. It completely by-passes the CPU. It requires some configuration on the PHBs involved: 1. on the initiating side, the address for the read/write operation is in the mmio space of the target, i.e. well outside the range normally allowed. So we disable range-checking on the TVT entry in bypass mode. 2. on the target side, we need to explicitly enable p2p by setting a bit in a configuration register. It has the side-effect of reserving an outbound (as seen from the CPU) store queue for p2p. Therefore we only enable p2p on the PHBs using it, as we don't want to waste the resource if we don't have to. P9 supports p2p mmio writes. Reads are currently only supported if the two devices are under the same PHB but that is expected to change in the future, and it raises questions about intermediate switches configuration, so we report an error for the time being. The patch adds a new OPAL call to allow the OS to declare a p2p (initiator, target) pair. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Define vas_get_wcbs_bar interfaceSukadev Bhattiprolu2017-08-011-0/+15
| | | | | | | | | Implement the function vas_get_wcbs_bar() that returns the Window Context Backing store address register. NX driver uses this function to initialize its UMAC Send WC register. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Define vas_get_hvwc_mmio_bar interfaceSukadev Bhattiprolu2017-08-011-0/+13
| | | | | | | | The nest accelerator (NX) will need this interface to initialize its UMAC MMIO BAR. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
* vas: Create MMIO device tree nodeSukadev Bhattiprolu2017-08-011-0/+30
| | | | | | | | Create a device tree node for VAS and add properties that Linux will need to configure/use VAS. Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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