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* external/mambo: allow CPU targeting for most debug utilsNicholas Piggin2019-02-121-97/+229
| | | | | | | | | | | | | | Debug util functions target CPU 0:0:0 by default Some can be overidden explicitly per invocation, and others can't at all. Even for those that can be overidden, it is a pain to type them out when you're debugging a particular thread. Provide a new 'target' function that allows the default CPU target to be changed. Wire that up that default to all other utils. Provide a new 'S' step command which only steps the target CPU. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/cpu: HID update raceNicholas Piggin2019-02-121-2/+2
| | | | | | | | | | | | If the per-core HID register is updated concurrently by multiple threads, updates can get lost. This has been observed during fast reboot where the HILE bit does not get cleared on all cores, which can cause machine check exception interrupts to crash. Fix this by only updating HID on thread0. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Add PVR_TYPE_P9PReza Arbab2019-02-1012-5/+39
| | | | | | | Enable a new PVR to get us running on another p9 variant. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Revert "astbmc: Try IPMI HIOMAP for P8"Joel Stanley2019-02-104-67/+33
| | | | | | | | | | | | | | | | | | | This reverts commit bd9839684d482417e8c60449592f4308e9a91dac as it broke booting on P8 systems, including Garrison (AMI BMC), Firestone (AMI BMC) and QEMU (BMC simulator). Issue https://github.com/open-power/skiboot/issues/217 tracks the failure. The P8 IPMI HIOMAP feature can be re-enabled once this issue is resolved. Reported-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Reported-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Acked-by: Sam Mendoza-Jonas <sam@mendozajonas.com> Tested-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* cpufeatures: Always advertise POWER8NVL as DD2Alexey Kardashevskiy2019-02-101-4/+5
| | | | | | | | | | | | | | | | Despite the major version of PVR being 1 (0x004c0100) for POWER8NVL, these chips are functionally equalent to P8/P8E DD2 levels. This advertises POWER8NVL as DD2. As the result, skiboot adds ibm,powerpc-cpu-features/processor-control-facility for such CPUs and the linux kernel can use hypervisor doorbell messages to wake secondary threads; otherwise "KVM: CPU %d seems to be stuck" would appear because of missing LPCR_PECEDH. Fixes: 7f4c8e8ce0b "dt: add /cpus/ibm, powerpc-cpu-features device tree bindings" Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* skiboot v6.0.16 release notesVasant Hegde2019-02-051-0/+53
| | | | | | | | Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> [stewart: add in the extra patches I merged] Signed-off-by: Stewart Smith <stewart@linux.ibm.com> (cherry picked from commit 9e22b74601cc1d042c4d1d2027f545b4ae304ae8) Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* doc: clarify OPAL_RTC_READ return valuesStewart Smith2019-02-041-0/+4
| | | | | | | | It's a quirky call. There was some discussion ages ago surrounding the fact that we barely document what it returns and when. So, umm... make it slightly less terrible, but still terrible. Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/opal: Print PIR value in exit pathVasant Hegde2019-02-041-2/+2
| | | | | | | | Useful for debugging. CC: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/ipmi: Improve error messageVasant Hegde2019-02-041-1/+2
| | | | | | | Useful for debugging. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/lock: Stop drop_my_locks() from always causing abortReza Arbab2019-02-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The loop in drop_my_locks() looks like this: while((l = list_pop(&this_cpu()->locks_held, struct lock, list)) != NULL) { if (warn) prlog(PR_ERR, " %s\n", l->owner); unlock(l); } Both list_pop() and unlock() call list_del(). This means that on the last iteration of the loop, the list will be empty when we get to unlock_check(), causing this: LOCK ERROR: Releasing lock we don't hold depth @0x30493d20 (state: 0x0000000000000001) [13836.000173140,0] Aborting! CPU 0000 Backtrace: S: 0000000031c03930 R: 000000003001d840 ._abort+0x60 S: 0000000031c039c0 R: 000000003001a0c4 .lock_error+0x64 S: 0000000031c03a50 R: 0000000030019c70 .unlock+0x54 S: 0000000031c03af0 R: 000000003001a040 .drop_my_locks+0xf4 To fix this, change list_pop() to list_top(). Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* p9dsu: Fix p9dsu slot tablesDeb McLemore2019-02-041-15/+30
| | | | | | | | | | | | | Set the attributes on the slot tables to account for builtin or pluggable etypes, this will allow pci enumeration to calculate subordinate buses. Update some slot label strings. Add WIO Slot5 which is standard on the ESS config. Signed-off-by: Deb McLemore <debmc@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* p9dsu: Fix p9dsu default variantDeb McLemore2019-01-251-19/+21
| | | | | | | | | | | Add the default when no riser_id is returned from the ipmi query. This addresses: https://github.com/open-power/boston-openpower/issues/1369 Allow a little more time for BMC reply and cleanup some label strings. Signed-off-by: Deb McLemore <debmc@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Remove POWER9N DD1 supportNicholas Piggin2019-01-2513-407/+92
| | | | | | | | This is not a shipping product and is no longer supported by Linux or other firmware components. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* xive: remove POWER9N DD1 NVT table size workaroundNicholas Piggin2019-01-251-5/+1
| | | | | | Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* phb4: remove POWER9N DD1 creset workaroundNicholas Piggin2019-01-251-5/+0
| | | | | Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* SLW: Print verbose info on errors onlyAkshay Adiga2019-01-251-2/+7
| | | | | | | | | | Change print level from debug to warning for reporting bad EC_PPM_SPECIAL_WKUP_* scom values. To reduce cluttering in the log print only on error. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* SLW: Remove Idle state support tor Power8 DD1Akshay Adiga2019-01-251-50/+0
| | | | | | | | Removing init routines required for Power8 DD1, but was enabled for all Power8 DD versions. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* p8dtu: Configure BMC graphicsAndrew Jeffery2019-01-181-1/+9
| | | | | | | | We can no-longer read the values from the BMC in the way we have in the past. Values were provided by Eric Chen of SMC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* p8dtu: Enable HIOMAP supportAndrew Jeffery2019-01-181-0/+1
| | | | | Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* astbmc: Try IPMI HIOMAP for P8Andrew Jeffery2019-01-184-33/+67
| | | | | | | | | | | | The HIOMAP protocol was developed after the release of P8 in preparation for P9. As a consequence P9 always uses it, but it has rarely been enabled for P8. P8DTU has recently added IPMI HIOMAP support to its BMC firmware, so enable its use in skiboot with P8 machines. Doing so requires some rework to ensure fallback works correctly as in the past the fallback was to mbox, which will only work for P9. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* zaius: zaius_ocapi can be staticStewart Smith2019-01-181-1/+1
| | | | | | Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* zz: platform_ocapi can be staticStewart Smith2019-01-181-1/+1
| | | | | | Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* sparse: Make tree 'constant is so big' warning cleanStewart Smith2019-01-1817-213/+213
| | | | Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* qemu: bt device isn't always hanging off /Stewart Smith2019-01-161-3/+2
| | | | | | | | | | | | | Just use the normal for_each_compatible instead. Otherwise in the qemu model as executed by op-test, we wouldn't go down the astbmc_init() path, thus not having flash. Cc: stable # v6.2+ Fixes: 2f0b6af6e01c5f7b3c762647d06c4f792e2cb3b7 Signed-off-by: Stewart Smith <stewart@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Replace open coded dt_find_by_name_addr()Reza Arbab2019-01-161-12/+1
| | | | | | | | We now have a dt function to do this. Use it. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Remove redundant assignment to p->phb_nvlink.scan_mapReza Arbab2019-01-161-4/+1
| | | | | | | | | | | | | | | | | | | | | | In npu2_populate_devices(), we do p->phb_nvlink.scan_map |= 0x1 << ((dev->bdfn & 0xf8) >> 3); : dev->nvlink.pvd = pci_virt_add_device(&p->phb_nvlink, dev->bdfn, 0x100, dev); /* At this point, dev->nvlink.pvd->bdfn = dev->bdfn */ if (dev->nvlink.pvd) { p->phb_nvlink.scan_map |= 0x1 << ((dev->nvlink.pvd->bdfn & 0xf8) >> 3); : } Because dev->nvlink.pvd->bdfn equals dev->bdfn, the second assignment to scan_map is redundant. Remove it. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Fix missing iteration in tce kill loopReza Arbab2019-01-161-0/+1
| | | | | | | | | When killing multiple pages, npu2_tce_kill() loops doing single page kills, but never advances the address. Fix this. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Remove unused npu2_dev_nvlink::vendor_capReza Arbab2019-01-162-4/+0
| | | | | | | | This variable is never used. Remove it. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Remove unused npu2_dev::procedure_dataReza Arbab2019-01-162-3/+0
| | | | | | | | This variable is never used. Remove it. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Remove unused npu2::lxive_cacheReza Arbab2019-01-161-1/+0
| | | | | | | | This variable is never used. Remove it. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Remove unused npu2::bdf2pe_cacheReza Arbab2019-01-163-32/+0
| | | | | | | | | | This cache is written but never read. Wiring it up would gain us little (except added complexity), and it obviously hasn't been missed thus far, so remove it altogether. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* npu2: Remove dead code from npu2_cfg_write_bar()Reza Arbab2019-01-161-4/+0
| | | | | | | | We assign pci_cmd, but it never gets used. Remove it. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* Remove duplicate npu2-common.o from $(HW_OBJS)Reza Arbab2019-01-161-1/+1
| | | | | | | | We've listed npu2-common.o twice. Remove one. Signed-off-by: Reza Arbab <arbab@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* capp/phb4: Prevent HMI from getting triggered when disabling CAPPVaibhav Jain2019-01-161-0/+11
| | | | | | | | | | | | | | | | | | | | | While disabling CAPP an HMI gets triggered as soon as ETU is put in reset mode. This is caused as before we can disabled CAPP, it detects PHB link going down and triggers an HMI requesting Opal to perform CAPP recovery. This has an un-intended side effect of spamming the Opal logs with malfunction alert messages and may also confuse the user. To prevent this we mask the CAPP FIR error 'PHB Link Down' Bit(31) when we are disabling CAPP just before we put ETU in reset in phb4_creset(). Also now since bringing down the PHB link now wont trigger an HMI and CAPP recovery, hence we manually set the PHB4_CAPP_RECOVERY flag on the phb to force recovery during creset. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* phb4/capp: Implement sequence to disable CAPP and enable fast-resetVaibhav Jain2019-01-161-3/+64
| | | | | | | | | | | | | | | | | | | | We implement h/w sequence to disable CAPP in disable_capi_mode() and with it also enable fast-reset for CAPI mode in phb4_set_capi_mode(). Sequence to disable CAPP is executed in three phases. The first two phase is implemented in disable_capi_mode() where we reset the CAPP registers followed by PEC registers to their init values. The final third final phase is to reset the PHB CAPI Compare/Mask Register and is done in phb4_init_ioda3(). The reason to move the PHB reset to phb4_init_ioda3() is because by the time Opal PCI reset state machine reaches this function the PHB is already un-fenced and its configuration registers accessible via mmio. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* capp/phb4: Introduce PHB4 flag, PHB4_CAPP_DISABLE to disable CAPPVaibhav Jain2019-01-162-1/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a PHB4 flag PHB4_CAPP_DISABLE and scaffolding necessary to handle it during CRESET flow. The flag is set when CAPP is request to switch to PCIe mode via call to phb4_set_capi_mode() with mode OPAL_PHB_CAPI_MODE_PCIE. This starts the below sequence that ultimately ends in newly introduced phb4_slot_sm_run_completed() 1. Set PHB4_CAPP_DISABLE to phb4->flags. 2. Start a CRESET on the phb slot. This also starts the opal pci reset state machine. 3. Wait for slot state to be PHB4_SLOT_CRESET_WAIT_CQ. 4. Perform CAPP recovery as PHB is still fenced, by calling do_capp_recovery_scoms(). 5. Call newly introduced 'disable_capi_mode()' to disable CAPP. 6. Wait for slot reset to complete while it transitions to PHB4_SLOT_FRESET and optionally to PHB4_SLOT_LINK_START. 7. Once slot reset is complete opal pci-core state machine will call slot->ops.completed_sm_run(). 8. For PHB4 this branches newly introduced 'phb4_slot_sm_run_completed()'. 9. Inside this function we mark the CAPP as disabled and un-register the opal syncer phb4_host_sync_reset(). 10. Optionally if the slot reset was unsuccessful disable fast-reboot. **************************** Notes: **************************** a. Function 'disable_capi_mode()' performs various sanity tests on CAPP to to determine if its ok to disable it and perform necessary xscoms to disable it. However the current implementation proposed in this patch is a skeleton one that just does sanity tests. A followup patch will be proposed that implements the xscoms necessary to disable CAPP. b. The sequence expects that Opal PCI reset state machine makes forward progress hence needs someone to call slot->ops.run_sm(). This can be either from phb4_host_sync_reset() or opal_pci_poll(). Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* capp/phb4: Force CAPP to PCIe mode during kernel shutdownVaibhav Jain2019-01-161-0/+34
| | | | | | | | | | | | | | | | | | This patch introduces a new opal syncer for PHB4 named phb4_host_sync_reset(). We register this opal syncer when CAPP is activated successfully in phb4_set_capi_mode() so that it will be called at kernel shutdown during fast-reset. During kernel shutdown the function will then repeatedly call phb->ops->set_capi_mode() to switch switch CAPP to PCIe mode. In case set_capi_mode() indicates its OPAL_BUSY, which indicates that CAPP is still transitioning to new state; it calls slot->ops.run_sm() to ensure that Opal slot reset state machine makes forward progress. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* phb4/capp: Update and re-factor phb4_set_capi_mode()Vaibhav Jain2019-01-161-35/+53
| | | | | | | | | | | | | | | | | | Presently phb4_set_capi_mode() performs certain CAPP checks like, checking of CAPP ucode loaded or checks if CAPP is still in recovery, even when the requested mode is to switch to PCI mode. Hence this patch updates and re-factors phb4_set_capi_mode() to make sure CAPP related checks are only performed when request to enable CAPP is made by mode==OPAL_PHB_CAPI_MODE_CAPI/DMA_TVT1. We also update other possible modes requests to return a more appropriate status code based on if CAPP is activated or not. Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* capp/phb: Introduce 'struct capp' to hold capp related info in 'struct phb'Vaibhav Jain2019-01-165-8/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously struct proc_chip member 'capp_phb3_attached_mask' was used for Power-8 to keep track of PHB attached to the single CAPP on the chip. CAPP on that chip supported a flexible PHB assignment scheme. However since then new chips only support a static assignment i.e a CAPP can only be attached to a specific PEC. Hence instead of using 'proc_chip.capp_phb4_attached_mask' to manage CAPP <-> PEC assignments which needs a global lock (capi_lock) to be updated, we introduce a new struct named 'capp' a pointer to which resides inside struct 'phb4'. Since updates to struct 'phb4' already happen in context of phb_lock; this eliminates the need to use mutex 'capi_lock' while updating 'capp_phb4_attached_mask'. This struct is also used to hold CAPP specific variables such as pointer to the 'struct phb' to which the CAPP is attached, 'capp_xscom_offset' which is the xscom offset to be added to CAPP registers in case there are more than 1 on the chip, 'capp_index' which is the index of the CAPP on the chip, and attached_pe' which is the process endpoint index to which CAPP is attached. Finally member 'chip_id' holds the chip-id thats used for performing xscom read/writes. Also new helpers named capp_xscom_read()/write() are introduced to make access to CAPP xscom registers easier. Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* core/pci: Introduce a new pci_slot_op named completed_sm_run()Vaibhav Jain2019-01-162-1/+6
| | | | | | | | | | | | | | | | | | | | | | | At times we need to perform some cleanup activities when the Opal PCI state machine that perform creset/freset/hreset (driven by pci_slot_ops->run_sm which) of a slot completes. One example can be to mark CAPP attached to a PHB, as deactivated when creset/freset of a CAPI card slot is completed. However the calls to pci_slot_ops->run_sm() is scattered through out the code and patching each call site to check for the return value and perform custom cleanup tacks is difficult. Hence this patch introduces a new pci_slot_ops named completed_sm_run() which should be called when pci_slot_ops->run_sm() determines that the reset state machine is complete. This provides a more centralized way to handle slot related cleanup activities. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal: Update opal_del_host_sync_notifier() to accept 'void *data'Vaibhav Jain2019-01-162-3/+6
| | | | | | | | | | | | | | | | | | | | | | Current implementation of opal_del_host_sync_notifier() will only delete the first entry of the 'notify' callback found from opal_syncers list irrespective of the 'data' of list-node. This is problematic when multiple notifiers with same callback function but different 'data' are registered. In this case when the cleanup code will call opal_del_host_sync_notifier() it cannot be sure if correct opal_syncer is removed. Hence this patch updates the function to accept a new argument named 'void *data' which is then used to iterates over the opal_syncers list and only remove the first node node having the matching value for 'notify' callback as 'data'. Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* skiboot v6.0.15 release notesVasant Hegde2018-12-171-0/+45
| | | | | | | [ Upstream commit 3bcfff5498b73bdd5697f2e4e0a8b414ad0ae680 ] Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* skiboot v6.2 release notesStewart Smith2018-12-141-0/+1375
| | | | Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* opal-ci: Drop fedora27, add fedora29Stewart Smith2018-12-134-27/+6
| | | | Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* ci: Bump Qemu versionJoel Stanley2018-12-131-1/+1
| | | | | | | | | | | | | | | This moves the qemu version to qemu-powernv-for-skiboot-7 which is based on upstream's 3.1.0, and supports a Power9 machine. It also includes a fix for the skiboot XSCOM errors: XSCOM: read error gcid=0x0 pcb_addr=0x1020013 stat=0x0 There is no modelling of the xscom behaviour but the reads/writes now succeed which is enough for skiboot to not error out. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* test: Update qemu arguments to use bmc simulatorJoel Stanley2018-12-133-3/+6
| | | | | | | | | | | | | | | | | | | | | | THe qemu skiboot platform as of 8340a9642bba ("plat/qemu: use the common OpenPOWER routines to initialize") uses the common aspeed BMC setup routines. This means a BT interface is always set up, and if the corresponding Qemu model is not present the timeout is 30 seconds. It looks like this every time an IPMI message is sent: BT: seq 0x9e netfn 0x06 cmd 0x31: Maximum queue length exceeded BT: seq 0x9d netfn 0x06 cmd 0x31: Removed from queue BT: seq 0x9f netfn 0x06 cmd 0x31: Maximum queue length exceeded BT: seq 0x9e netfn 0x06 cmd 0x31: Removed from queue BT: seq 0xa0 netfn 0x06 cmd 0x31: Maximum queue length exceeded BT: seq 0x9f netfn 0x06 cmd 0x31: Removed from queue Avoid this by adding the bmc simulator model to the Qemu powernv machine. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* ci: Add opal-utils to Debian unstableJoel Stanley2018-12-131-1/+4
| | | | | | | | This puts a 'pflash' in the users PATH, allowing more test coverage of ffspart. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* ci: Drop P8 mambo from Debian unstableJoel Stanley2018-12-131-1/+0
| | | | | | | | | | | | | | | | | Debian Unstable has removed OpenSSL 1.0.0 from the repository so mambo no longer runs: /opt/ibm/systemsim-p8/bin/systemsim-pegasus: error while loading shared libraries: libcrypto.so.1.0.0: cannot open shared object file: No such file or directory By removing it from the container these tests will be automatically skipped. Tracked in https://github.com/open-power/op-build/issues/2519 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* ci: Add dtc dependencies for rawhideJoel Stanley2018-12-131-0/+2
| | | | | | | | Both F28 and Rawhide build their own dtc version. Rawhide was missing the required build deps. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
* ci: Update Debian unstable packagesJoel Stanley2018-12-131-3/+2
| | | | | | | | | This syncs Debian unstable with Ubuntu 18.04 in order to get the clang package. It also adds qemu to the Debian install, which makes sense Debian also has 2.12. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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