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/*
* MPC8568E MDS Device Tree Source
*
* Copyright 2007, 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/include/ "fsl/mpc8568si-pre.dtsi"
/ {
model = "MPC8568EMDS";
compatible = "MPC8568EMDS", "MPC85xxMDS";
aliases {
pci0 = &pci0;
pci1 = &pci1;
rapidio0 = &rio;
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x0>;
};
lbc: localbus@e0005000 {
reg = <0x0 0xe0005000 0x0 0x1000>;
ranges = <0x0 0x0 0xfe000000 0x02000000
0x1 0x0 0xf8000000 0x00008000
0x2 0x0 0xf0000000 0x04000000
0x4 0x0 0xf8008000 0x00008000
0x5 0x0 0xf8010000 0x00008000>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x02000000>;
bank-width = <2>;
device-width = <2>;
};
bcsr@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8568mds-bcsr";
reg = <1 0 0x8000>;
ranges = <0 1 0 0x8000>;
bcsr5: gpio-controller@11 {
#gpio-cells = <2>;
compatible = "fsl,mpc8568mds-bcsr-gpio";
reg = <0x5 0x1>;
gpio-controller;
};
};
pib@4,0 {
compatible = "fsl,mpc8568mds-pib";
reg = <4 0 0x8000>;
};
pib@5,0 {
compatible = "fsl,mpc8568mds-pib";
reg = <5 0 0x8000>;
};
};
soc: soc8568@e0000000 {
ranges = <0x0 0x0 0xe0000000 0x100000>;
i2c-sleep-nexus {
i2c@3000 {
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
interrupts = <3 1 0 0>;
};
};
};
enet0: ethernet@24000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy2>;
};
mdio@24520 {
phy0: ethernet-phy@7 {
interrupts = <1 1 0 0>;
reg = <0x7>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x1>;
device_type = "ethernet-phy";
};
phy2: ethernet-phy@2 {
interrupts = <1 1 0 0>;
reg = <0x2>;
device_type = "ethernet-phy";
};
phy3: ethernet-phy@3 {
interrupts = <2 1 0 0>;
reg = <0x3>;
device_type = "ethernet-phy";
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@25000 {
tbi-handle = <&tbi1>;
phy-handle = <&phy3>;
sleep = <&pmc 0x00000040>;
};
mdio@25520 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
par_io@e0100 {
num-ports = <7>;
pio1: ucc_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
};
pio2: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
};
};
};
qe: qe@e0080000 {
ranges = <0x0 0x0 0xe0080000 0x40000>;
reg = <0x0 0xe0080000 0x0 0x480>;
spi@4c0 {
mode = "cpu";
};
spi@500 {
mode = "cpu";
};
enet2: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
pio-handle = <&pio1>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
enet3: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
pio-handle = <&pio2>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
mdio@2120 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2120 0x18>;
compatible = "fsl,ucc-mdio";
/* These are the same PHYs as on
* gianfar's MDIO bus */
qe_phy0: ethernet-phy@07 {
interrupt-parent = <&mpic>;
interrupts = <1 1 0 0>;
reg = <0x7>;
device_type = "ethernet-phy";
};
qe_phy1: ethernet-phy@01 {
interrupt-parent = <&mpic>;
interrupts = <2 1 0 0>;
reg = <0x1>;
device_type = "ethernet-phy";
};
qe_phy2: ethernet-phy@02 {
interrupt-parent = <&mpic>;
interrupts = <1 1 0 0>;
reg = <0x2>;
device_type = "ethernet-phy";
};
qe_phy3: ethernet-phy@03 {
interrupt-parent = <&mpic>;
interrupts = <2 1 0 0>;
reg = <0x3>;
device_type = "ethernet-phy";
};
};
};
pci0: pci@e0008000 {
reg = <0x0 0xe0008000 0x0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x12 AD18 */
0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
/* IDSEL 0x13 AD19 */
0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
};
/* PCI Express */
pci1: pcie@e000a000 {
ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
reg = <0x0 0xe000a000 0x0 0x1000>;
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
0x0 0x10000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x800000>;
};
};
rio: rapidio@e00c00000 {
reg = <0x0 0xe00c0000 0x0 0x20000>;
port1 {
ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
};
};
leds {
compatible = "gpio-leds";
green {
gpios = <&bcsr5 1 0>;
};
amber {
gpios = <&bcsr5 2 0>;
};
red {
gpios = <&bcsr5 3 0>;
};
};
};
/include/ "fsl/mpc8568si-post.dtsi"
|
