1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
|
// include/asm-arm/mach-omap/usb.h
#ifndef __ASM_ARCH_OMAP_USB_H
#define __ASM_ARCH_OMAP_USB_H
#include <linux/usb/musb.h>
#include <plat/board.h>
#define OMAP3_HS_USB_PORTS 3
enum ehci_hcd_omap_mode {
EHCI_HCD_OMAP_MODE_UNKNOWN,
EHCI_HCD_OMAP_MODE_PHY,
EHCI_HCD_OMAP_MODE_TLL,
};
enum ohci_omap3_port_mode {
OMAP_OHCI_PORT_MODE_UNUSED,
OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM,
};
struct ehci_hcd_omap_platform_data {
enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
unsigned phy_reset:1;
/* have to be valid if phy_reset is true and portx is in phy mode */
int reset_gpio_port[OMAP3_HS_USB_PORTS];
};
struct ohci_hcd_omap_platform_data {
enum ohci_omap3_port_mode port_mode[OMAP3_HS_USB_PORTS];
/* Set this to true for ES2.x silicon */
unsigned es2_compatibility:1;
};
/*-------------------------------------------------------------------------*/
#define OMAP1_OTG_BASE 0xfffb0400
#define OMAP1_UDC_BASE 0xfffb4000
#define OMAP1_OHCI_BASE 0xfffba000
#define OMAP2_OHCI_BASE 0x4805e000
#define OMAP2_UDC_BASE 0x4805e200
#define OMAP2_OTG_BASE 0x4805e300
#ifdef CONFIG_ARCH_OMAP1
#define OTG_BASE OMAP1_OTG_BASE
#define UDC_BASE OMAP1_UDC_BASE
#define OMAP_OHCI_BASE OMAP1_OHCI_BASE
#else
#define OTG_BASE OMAP2_OTG_BASE
#define UDC_BASE OMAP2_UDC_BASE
#define OMAP_OHCI_BASE OMAP2_OHCI_BASE
struct omap_musb_board_data {
u8 interface_type;
u8 mode;
u16 power;
unsigned extvbus:1;
};
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
extern void usb_musb_init(struct omap_musb_board_data *board_data);
extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
#endif
void omap_otg_init(struct omap_usb_config *config);
void omap_usb_init(struct omap_usb_config *pdata);
void omap2_usbfs_init(struct omap_usb_config *pdata);
#else
static inline omap2_usbfs_init(struct omap_usb_config *pdata)
{
}
#endif
/*-------------------------------------------------------------------------*/
/*
* OTG and transceiver registers, for OMAPs starting with ARM926
*/
#define OTG_REV (OTG_BASE + 0x00)
#define OTG_SYSCON_1 (OTG_BASE + 0x04)
# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
# define OTG_IDLE_EN (1 << 15)
# define HST_IDLE_EN (1 << 14)
# define DEV_IDLE_EN (1 << 13)
# define OTG_RESET_DONE (1 << 2)
# define OTG_SOFT_RESET (1 << 1)
#define OTG_SYSCON_2 (OTG_BASE + 0x08)
# define OTG_EN (1 << 31)
# define USBX_SYNCHRO (1 << 30)
# define OTG_MST16 (1 << 29)
# define SRP_GPDATA (1 << 28)
# define SRP_GPDVBUS (1 << 27)
# define SRP_GPUVBUS(w) (((w)>>24)&0x07)
# define A_WAIT_VRISE(w) (((w)>>20)&0x07)
# define B_ASE_BRST(w) (((w)>>16)&0x07)
# define SRP_DPW (1 << 14)
# define SRP_DATA (1 << 13)
# define SRP_VBUS (1 << 12)
# define OTG_PADEN (1 << 10)
# define HMC_PADEN (1 << 9)
# define UHOST_EN (1 << 8)
# define HMC_TLLSPEED (1 << 7)
# define HMC_TLLATTACH (1 << 6)
# define OTG_HMC(w) (((w)>>0)&0x3f)
#define OTG_CTRL (OTG_BASE + 0x0c)
# define OTG_USB2_EN (1 << 29)
# define OTG_USB2_DP (1 << 28)
# define OTG_USB2_DM (1 << 27)
# define OTG_USB1_EN (1 << 26)
# define OTG_USB1_DP (1 << 25)
# define OTG_USB1_DM (1 << 24)
# define OTG_USB0_EN (1 << 23)
# define OTG_USB0_DP (1 << 22)
# define OTG_USB0_DM (1 << 21)
# define OTG_ASESSVLD (1 << 20)
# define OTG_BSESSEND (1 << 19)
# define OTG_BSESSVLD (1 << 18)
# define OTG_VBUSVLD (1 << 17)
# define OTG_ID (1 << 16)
# define OTG_DRIVER_SEL (1 << 15)
# define OTG_A_SETB_HNPEN (1 << 12)
# define OTG_A_BUSREQ (1 << 11)
# define OTG_B_HNPEN (1 << 9)
# define OTG_B_BUSREQ (1 << 8)
# define OTG_BUSDROP (1 << 7)
# define OTG_PULLDOWN (1 << 5)
# define OTG_PULLUP (1 << 4)
# define OTG_DRV_VBUS (1 << 3)
# define OTG_PD_VBUS (1 << 2)
# define OTG_PU_VBUS (1 << 1)
# define OTG_PU_ID (1 << 0)
#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
# define DRIVER_SWITCH (1 << 15)
# define A_VBUS_ERR (1 << 13)
# define A_REQ_TMROUT (1 << 12)
# define A_SRP_DETECT (1 << 11)
# define B_HNP_FAIL (1 << 10)
# define B_SRP_TMROUT (1 << 9)
# define B_SRP_DONE (1 << 8)
# define B_SRP_STARTED (1 << 7)
# define OPRT_CHG (1 << 0)
#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
// same bits as in IRQ_EN
#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
# define OTGVPD (1 << 14)
# define OTGVPU (1 << 13)
# define OTGPUID (1 << 12)
# define USB2VDR (1 << 10)
# define USB2PDEN (1 << 9)
# define USB2PUEN (1 << 8)
# define USB1VDR (1 << 6)
# define USB1PDEN (1 << 5)
# define USB1PUEN (1 << 4)
# define USB0VDR (1 << 2)
# define USB0PDEN (1 << 1)
# define USB0PUEN (1 << 0)
#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
/*-------------------------------------------------------------------------*/
/* OMAP1 */
#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
# define CONF_USB2_UNI_R (1 << 8)
# define CONF_USB1_UNI_R (1 << 7)
# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
# define CONF_USB0_ISOLATE_R (1 << 3)
# define CONF_USB_PWRDN_DM_R (1 << 2)
# define CONF_USB_PWRDN_DP_R (1 << 1)
/* OMAP2 */
# define USB_UNIDIR 0x0
# define USB_UNIDIR_TLL 0x1
# define USB_BIDIR 0x2
# define USB_BIDIR_TLL 0x3
# define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
# define USBT2TLL5PI (1 << 17)
# define USB0PUENACTLOI (1 << 16)
# define USBSTANDBYCTRL (1 << 15)
#endif /* __ASM_ARCH_OMAP_USB_H */
|
