1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
|
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License terms: GNU General Public License (GPL) version 2
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>
#include <linux/string.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <asm/mach-types.h>
#include "board-mop500.h"
/* These simply sets bias for pins */
#define BIAS(a,b) static unsigned long a[] = { b }
BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
#define AB8500_MUX_HOG(group, func) \
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
#define AB8500_PIN_HOG(pin, conf) \
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
#define AB8500_MUX_STATE(group, func, dev, state) \
PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
#define AB8500_PIN_STATE(pin, conf, dev, state) \
PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
#define AB8505_MUX_HOG(group, func) \
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
#define AB8505_PIN_HOG(pin, conf) \
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
#define AB8505_MUX_STATE(group, func, dev, state) \
PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
#define AB8505_PIN_STATE(pin, conf, dev, state) \
PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
static struct pinctrl_map __initdata ab8500_pinmap[] = {
/* Sysclkreq2 */
AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
/* sysclkreq2 disable, mux in gpio configured in input pulldown */
AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
/* Sysclkreq4 */
AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
/* sysclkreq4 disable, mux in gpio configured in input pulldown */
AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/*
* pins 27,28 are muxed in DMIC12
* configured in INPUT PULL DOWN
*/
AB8500_MUX_HOG("dmic12_d_1", "dmic"),
AB8500_PIN_HOG("GPIO27_J6", in_pd),
AB8500_PIN_HOG("GPIO28_K6", in_pd),
/*
* pins 29,30 are muxed in DMIC34
* configured in INPUT PULL DOWN
*/
AB8500_MUX_HOG("dmic34_d_1", "dmic"),
AB8500_PIN_HOG("GPIO29_G6", in_pd),
AB8500_PIN_HOG("GPIO30_H6", in_pd),
/*
* pins 31,32 are muxed in DMIC56
* configured in INPUT PULL DOWN
*/
AB8500_MUX_HOG("dmic56_d_1", "dmic"),
AB8500_PIN_HOG("GPIO31_F5", in_pd),
AB8500_PIN_HOG("GPIO32_G5", in_pd),
/*
* pins 34 is muxed in EXTCPENA
* configured INPUT PULL DOWN
*/
AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
AB8500_PIN_HOG("GPIO34_R17", in_pd),
/*
* pins 40 and 41 are muxed in MODCSLSDA
* configured INPUT PULL DOWN
*/
AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
AB8500_PIN_HOG("GPIO40_T19", in_pd),
AB8500_PIN_HOG("GPIO41_U19", in_pd),
};
static struct pinctrl_map __initdata ab8505_pinmap[] = {
/* Sysclkreq2 */
AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
/* sysclkreq2 disable, mux in gpio configured in input pulldown */
AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
/* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
AB8505_MUX_HOG("gpio2_a_1", "gpio"),
AB8505_PIN_HOG("GPIO2_R5", in_pd),
/* Sysclkreq4 */
AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
/* sysclkreq4 disable, mux in gpio configured in input pulldown */
AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
AB8505_MUX_HOG("gpio10_d_1", "gpio"),
AB8505_PIN_HOG("GPIO10_B16", in_pd),
AB8505_MUX_HOG("gpio11_d_1", "gpio"),
AB8505_PIN_HOG("GPIO11_B17", in_pd),
AB8505_MUX_HOG("gpio13_d_1", "gpio"),
AB8505_PIN_HOG("GPIO13_D17", in_nopull),
AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
AB8505_PIN_HOG("GPIO14_C16", in_pd),
AB8505_MUX_HOG("adi2_d_1", "adi2"),
AB8505_PIN_HOG("GPIO17_P2", in_pd),
AB8505_PIN_HOG("GPIO18_N3", in_pd),
AB8505_PIN_HOG("GPIO19_T1", in_pd),
AB8505_PIN_HOG("GPIO20_P3", in_pd),
AB8505_MUX_HOG("gpio34_a_1", "gpio"),
AB8505_PIN_HOG("GPIO34_H14", in_pd),
AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
AB8505_PIN_HOG("GPIO40_J15", in_pd),
AB8505_PIN_HOG("GPIO41_J14", in_pd),
AB8505_MUX_HOG("gpio50_d_1", "gpio"),
AB8505_PIN_HOG("GPIO50_L4", in_nopull),
AB8505_MUX_HOG("resethw_d_1", "resethw"),
AB8505_PIN_HOG("GPIO52_D16", in_pd),
AB8505_MUX_HOG("service_d_1", "service"),
AB8505_PIN_HOG("GPIO53_D15", in_pd),
};
void __init mop500_pinmaps_init(void)
{
if (machine_is_u8520())
pinctrl_register_mappings(ab8505_pinmap,
ARRAY_SIZE(ab8505_pinmap));
else
pinctrl_register_mappings(ab8500_pinmap,
ARRAY_SIZE(ab8500_pinmap));
}
void __init snowball_pinmaps_init(void)
{
pinctrl_register_mappings(ab8500_pinmap,
ARRAY_SIZE(ab8500_pinmap));
}
void __init hrefv60_pinmaps_init(void)
{
pinctrl_register_mappings(ab8500_pinmap,
ARRAY_SIZE(ab8500_pinmap));
}
|
