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/*
* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <dt-bindings/clock/berlin2q.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
model = "Marvell Armada 1500 pro (BG2-Q) SoC";
compatible = "marvell,berlin2q", "marvell,berlin";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <1>;
};
cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <3>;
};
};
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xf7000000 0x1000000>;
interrupt-parent = <&gic>;
sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
clocks = <&chip CLKID_SDIO1XIN>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci1: sdhci@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
clocks = <&chip CLKID_SDIO1XIN>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sdhci2: sdhci@ab1000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_SDIO1XIN>;
status = "disabled";
};
l2: l2-cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-level = <2>;
arm,data-latency = <2 2 2>;
arm,tag-latency = <2 2 2>;
};
scu: snoop-control-unit@ad0000 {
compatible = "arm,cortex-a9-scu";
reg = <0xad0000 0x58>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
clocks = <&chip CLKID_TWD>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x100>;
interrupt-controller;
#interrupt-cells = <3>;
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
gpio0: gpio@0400 {
compatible = "snps,dw-apb-gpio";
reg = <0x0400 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-port@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0>;
};
};
gpio1: gpio@0800 {
compatible = "snps,dw-apb-gpio";
reg = <0x0800 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-port@1 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <1>;
};
};
gpio2: gpio@0c00 {
compatible = "snps,dw-apb-gpio";
reg = <0x0c00 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-port@2 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <2>;
};
};
gpio3: gpio@1000 {
compatible = "snps,dw-apb-gpio";
reg = <0x1000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-port@3 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <3>;
};
};
i2c0: i2c@1400 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1400 0x100>;
interrupt-parent = <&aic>;
interrupts = <4>;
clocks = <&chip CLKID_CFG>;
pinctrl-0 = <&twsi0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
i2c1: i2c@1800 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1800 0x100>;
interrupt-parent = <&aic>;
interrupts = <5>;
clocks = <&chip CLKID_CFG>;
pinctrl-0 = <&twsi1_pmux>;
pinctrl-names = "default";
status = "disabled";
};
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
interrupts = <8>;
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
clocks = <&chip CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3800 {
compatible = "snps,dw-apb-ictl";
reg = <0x3800 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
gpio4: gpio@5000 {
compatible = "snps,dw-apb-gpio";
reg = <0x5000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
porte: gpio-port@4 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
gpio5: gpio@c000 {
compatible = "snps,dw-apb-gpio";
reg = <0xc000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
portf: gpio-port@5 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
reg = <0>;
};
};
};
chip: chip-control@ea0000 {
compatible = "marvell,berlin2q-chip-ctrl";
#clock-cells = <1>;
reg = <0xea0000 0x400>, <0xdd0170 0x10>;
clocks = <&refclk>;
clock-names = "refclk";
twsi0_pmux: twsi0-pmux {
groups = "G6";
function = "twsi0";
};
twsi1_pmux: twsi1-pmux {
groups = "G7";
function = "twsi1";
};
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
i2c2: i2c@7000 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x100>;
interrupt-parent = <&sic>;
interrupts = <6>;
clocks = <&refclk>;
pinctrl-0 = <&twsi2_pmux>;
pinctrl-names = "default";
status = "disabled";
};
i2c3: i2c@8000 {
compatible = "snps,designware-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8000 0x100>;
interrupt-parent = <&sic>;
interrupts = <7>;
clocks = <&refclk>;
pinctrl-0 = <&twsi3_pmux>;
pinctrl-names = "default";
status = "disabled";
};
uart0: uart@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
interrupt-parent = <&sic>;
interrupts = <8>;
clocks = <&refclk>;
reg-shift = <2>;
pinctrl-0 = <&uart0_pmux>;
pinctrl-names = "default";
status = "disabled";
};
uart1: uart@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
interrupt-parent = <&sic>;
interrupts = <9>;
clocks = <&refclk>;
reg-shift = <2>;
pinctrl-0 = <&uart1_pmux>;
pinctrl-names = "default";
status = "disabled";
};
sysctrl: pin-controller@d000 {
compatible = "marvell,berlin2q-system-ctrl";
reg = <0xd000 0x100>;
uart0_pmux: uart0-pmux {
groups = "GSM12";
function = "uart0";
};
uart1_pmux: uart1-pmux {
groups = "GSM14";
function = "uart1";
};
twsi2_pmux: twsi2-pmux {
groups = "GSM13";
function = "twsi2";
};
twsi3_pmux: twsi3-pmux {
groups = "GSM14";
function = "twsi3";
};
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
|
