/* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * Based on "omap4.dtsi" */ #include #include #include #include / { #address-cells = <2>; #size-cells = <2>; compatible = "ti,omap5"; interrupt-parent = <&wakeupgen>; chosen { }; aliases { i2c0 = &i2c1; i2c1 = &i2c2; i2c2 = &i2c3; i2c3 = &i2c4; i2c4 = &i2c5; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; operating-points = < /* kHz uV */ 1000000 1060000 1500000 1250000 >; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; clock-latency = <300000>; /* From omap-cpufreq driver */ /* cooling options */ #cooling-cells = <2>; /* min followed by max */ }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; }; }; thermal-zones { #include "omap4-cpu-thermal.dtsi" #include "omap5-gpu-thermal.dtsi" #include "omap5-core-thermal.dtsi" }; timer { compatible = "arm,armv7-timer"; /* PPI secure/nonsecure IRQ */ interrupts = , , , ; interrupt-parent = <&gic>; }; pmu { compatible = "arm,cortex-a15-pmu"; interrupts = , ; }; gic: interrupt-controller@48211000 { compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0 0x48211000 0 0x1000>, <0 0x48212000 0 0x2000>, <0 0x48214000 0 0x2000>, <0 0x48216000 0 0x2000>; interrupt-parent = <&gic>; }; wakeupgen: interrupt-controller@48281000 { compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; reg = <0 0x48281000 0 0x1000>; interrupt-parent = <&gic>; }; /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. */ soc { compatible = "ti,omap-infra"; mpu { compatible = "ti,omap4-mpu"; ti,hwmods = "mpu"; sram = <&ocmcram>; }; }; /* * XXX: Use a flat representation of the OMAP3 interconnect. * The real OMAP interconnect network is quite complex. * Since it will not bring real advantage to represent that in DT for * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ ocp { compatible = "ti,omap5-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xc0000000>; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; reg = <0 0x44000000 0 0x2000>, <0 0x44800000 0 0x3000>, <0 0x45000000 0 0x4000>; interrupts = , ; l4_cfg: l4@4a000000 { compatible = "ti,omap5-l4-cfg", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4a000000 0x22a000>; scm_core: scm@2000 { compatible = "ti,omap5-scm-core", "simple-bus"; reg = <0x2000 0x1000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2000 0x800>; scm_conf: scm_conf@0 { compatible = "syscon"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; }; }; scm_padconf_core: scm@2800 { compatible = "ti,omap5-scm-padconf-core", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x2800 0x800>; omap5_pmx_core: pinmux@40 { compatible = "ti,omap5-padconf", "pinctrl-single"; reg = <0x40 0x01b6>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; omap5_padconf_global: omap5_padconf_global@5a0 { compatible = "syscon", "simple-bus"; reg = <0x5a0 0xec>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x5a0 0xec>; pbias_regulator: pbias_regulator@60 { compatible = "ti,pbias-omap5", "ti,pbias-omap"; reg = <0x60 0x4>; syscon = <&omap5_padconf_global>; pbias_mmc_reg: pbias_mmc_omap5 { regulator-name = "pbias_mmc_omap5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; }; }; }; cm_core_aon: cm_core_aon@4000 { compatible = "ti,omap5-cm-core-aon", "simple-bus"; reg = <0x4000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4000 0x2000>; cm_core_aon_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_core_aon_clockdomains: clockdomains { }; }; cm_core: cm_core@8000 { compatible = "ti,omap5-cm-core", "simple-bus"; reg = <0x8000 0x3000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8000 0x3000>; cm_core_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; cm_core_clockdomains: clockdomains { }; }; }; l4_wkup: l4@4ae00000 { compatible = "ti,omap5-l4-wkup", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x4ae00000 0x2b000>; counter32k: counter@4000 { compatible = "ti,omap-counter32k"; reg = <0x4000 0x40>; ti,hwmods = "counter_32k"; }; prm: prm@6000 { compatible = "ti,omap5-prm", "simple-bus"; reg = <0x6000 0x3000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x6000 0x3000>; prm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; prm_clockdomains: clockdomains { }; }; scrm: scrm@a000 { compatible = "ti,omap5-scrm"; reg = <0xa000 0x2000>; scrm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; }; scrm_clockdomains: clockdomains { }; }; omap5_pmx_wkup: pinmux@c840 { compatible = "ti,omap5-padconf", "pinctrl-single"; reg = <0xc840 0x003c>; #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; #interrupt-cells = <1>; interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; }; ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; reg = <0x40300000 0x20000>; /* 128k */ }; sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; interrupts = , , , ; #dma-cells = <1>; dma-channels = <32>; dma-requests = <127>; ti,hwmods = "dma_system"; }; gpio1: gpio@4ae10000 { compatible = "ti,omap4-gpio"; reg = <0x4ae10000 0x200>; interrupts = ; ti,hwmods = "gpio1"; ti,gpio-always-on; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio2: gpio@48055000 { compatible = "ti,omap4-gpio"; reg = <0x48055000 0x200>; interrupts = ; ti,hwmods = "gpio2"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio3: gpio@48057000 { compatible = "ti,omap4-gpio"; reg = <0x48057000 0x200>; interrupts = ; ti,hwmods = "gpio3"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio4: gpio@48059000 { compatible = "ti,omap4-gpio"; reg = <0x48059000 0x200>; interrupts = ; ti,hwmods = "gpio4"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio5: gpio@4805b000 { compatible = "ti,omap4-gpio"; reg = <0x4805b000 0x200>; interrupts = ; ti,hwmods = "gpio5"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio6: gpio@4805d000 { compatible = "ti,omap4-gpio"; reg = <0x4805d000 0x200>; interrupts = ; ti,hwmods = "gpio6"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio7: gpio@48051000 { compatible = "ti,omap4-gpio"; reg = <0x48051000 0x200>; interrupts = ; ti,hwmods = "gpio7"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpio8: gpio@48053000 { compatible = "ti,omap4-gpio"; reg = <0x48053000 0x200>; interrupts = ; ti,hwmods = "gpio8"; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; gpmc: gpmc@50000000 { compatible = "ti,omap4430-gpmc"; reg = <0x50000000 0x1000>; #address-cells = <2>; #size-cells = <1>; interrupts = ; dmas = <&sdma 4>; dma-names = "rxtx"; gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; clocks = <&l3_iclk_div>; clock-names = "fck"; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; }; i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c1"; }; i2c2: i2c@48072000 { compatible = "ti,omap4-i2c"; reg = <0x48072000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c2"; }; i2c3: i2c@48060000 { compatible = "ti,omap4-i2c"; reg = <0x48060000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c3"; }; i2c4: i2c@4807a000 { compatible = "ti,omap4-i2c"; reg = <0x4807a000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c4"; }; i2c5: i2c@4807c000 { compatible = "ti,omap4-i2c"; reg = <0x4807c000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "i2c5"; }; hwspinlock: spinlock@4a0f6000 { compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; ti,hwmods = "spinlock"; #hwlock-cells = <1>; }; mcspi1: spi@48098000 { compatible = "ti,omap4-mcspi"; reg = <0x48098000 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi1"; ti,spi-num-cs = <4>; dmas = <&sdma 35>, <&sdma 36>, <&sdma 37>, <&sdma 38>, <&sdma 39>, <&sdma 40>, <&sdma 41>, <&sdma 42>; dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3"; }; mcspi2: spi@4809a000 { compatible = "ti,omap4-mcspi"; reg = <0x4809a000 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi2"; ti,spi-num-cs = <2>; dmas = <&sdma 43>, <&sdma 44>, <&sdma 45>, <&sdma 46>; dma-names = "tx0", "rx0", "tx1", "rx1"; }; mcspi3: spi@480b8000 { compatible = "ti,omap4-mcspi"; reg = <0x480b8000 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi3"; ti,spi-num-cs = <2>; dmas = <&sdma 15>, <&sdma 16>; dma-names = "tx0", "rx0"; }; mcspi4: spi@480ba000 { compatible = "ti,omap4-mcspi"; reg = <0x480ba000 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "mcspi4"; ti,spi-num-cs = <1>; dmas = <&sdma 70>, <&sdma 71>; dma-names = "tx0", "rx0"; }; uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; interrupts = ; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; interrupts = ; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; interrupts = ; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; interrupts = ; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; interrupts = ; ti,hwmods = "uart5"; clock-frequency = <48000000>; }; uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; interrupts = ; ti,hwmods = "uart6"; clock-frequency = <48000000>; }; mmc1: mmc@4809c000 { compatible = "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; interrupts = ; ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; dmas = <&sdma 61>, <&sdma 62>; dma-names = "tx", "rx"; pbias-supply = <&pbias_mmc_reg>; }; mmc2: mmc@480b4000 { compatible = "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; interrupts = ; ti,hwmods = "mmc2"; ti,needs-special-reset; dmas = <&sdma 47>, <&sdma 48>; dma-names = "tx", "rx"; }; mmc3: mmc@480ad000 { compatible = "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; interrupts = ; ti,hwmods = "mmc3"; ti,needs-special-reset; dmas = <&sdma 77>, <&sdma 78>; dma-names = "tx", "rx"; }; mmc4: mmc@480d1000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; interrupts = ; ti,hwmods = "mmc4"; ti,needs-special-reset; dmas = <&sdma 57>, <&sdma 58>; dma-names = "tx", "rx"; }; mmc5: mmc@480d5000 { compatible = "ti,omap4-hsmmc"; reg = <0x480d5000 0x400>; interrupts = ; ti,hwmods = "mmc5"; ti,needs-special-reset; dmas = <&sdma 59>, <&sdma 60>; dma-names = "tx", "rx"; }; mmu_dsp: mmu@4a066000 { compatible = "ti,omap4-iommu"; reg = <0x4a066000 0x100>; interrupts = ; ti,hwmods = "mmu_dsp"; #iommu-cells = <0>; }; mmu_ipu: mmu@55082000 { compatible = "ti,omap4-iommu"; reg = <0x55082000 0x100>; interrupts = ; ti,hwmods = "mmu_ipu"; #iommu-cells = <0>; ti,iommu-bus-err-back; }; keypad: keypad@4ae1c000 { compatible = "ti,omap4-keypad"; reg = <0x4ae1c000 0x400>; ti,hwmods = "kbd"; }; mcpdm: mcpdm@40132000 { compatible = "ti,omap4-mcpdm"; reg = <0x40132000 0x7f>, /* MPU private access */ <0x49032000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; ti,hwmods = "mcpdm"; dmas = <&sdma 65>, <&sdma 66>; dma-names = "up_link", "dn_link"; status = "disabled"; }; dmic: dmic@4012e000 { compatible = "ti,omap4-dmic"; reg = <0x4012e000 0x7f>, /* MPU private access */ <0x4902e000 0x7f>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; ti,hwmods = "dmic"; dmas = <&sdma 67>; dma-names = "up_link"; status = "disabled"; }; mcbsp1: mcbsp@40122000 { compatible = "ti,omap4-mcbsp"; reg = <0x40122000 0xff>, /* MPU private access */ <0x49022000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp1"; dmas = <&sdma 33>, <&sdma 34>; dma-names = "tx", "rx"; status = "disabled"; }; mcbsp2: mcbsp@40124000 { compatible = "ti,omap4-mcbsp"; reg = <0x40124000 0xff>, /* MPU private access */ <0x49024000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp2"; dmas = <&sdma 17>, <&sdma 18>; dma-names = "tx", "rx"; status = "disabled"; }; mcbsp3: mcbsp@40126000 { compatible = "ti,omap4-mcbsp"; reg = <0x40126000 0xff>, /* MPU private access */ <0x49026000 0xff>; /* L3 Interconnect */ reg-names = "mpu", "dma"; interrupts = ; interrupt-names = "common"; ti,buffer-size = <128>; ti,hwmods = "mcbsp3"; dmas = <&sdma 19>, <&sdma 20>; dma-names = "tx", "rx"; status = "disabled"; }; mailbox: mailbox@4a0f4000 { compatible = "ti,omap4-mailbox"; reg = <0x4a0f4000 0x200>; interrupts = ; ti,hwmods = "mailbox"; #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; mbox_ipu: mbox_ipu { ti,mbox-tx = <0 0 0>; ti,mbox-rx = <1 0 0>; }; mbox_dsp: mbox_dsp { ti,mbox-tx = <3 0 0>; ti,mbox-rx = <2 0 0>; }; }; timer1: timer@4ae18000 { compatible = "ti,omap5430-timer"; reg = <0x4ae18000 0x80>; interrupts = ; ti,hwmods = "timer1"; ti,timer-alwon; clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; clock-names = "fck"; }; timer2: timer@48032000 { compatible = "ti,omap5430-timer"; reg = <0x48032000 0x80>; interrupts = ; ti,hwmods = "timer2"; }; timer3: timer@48034000 { compatible = "ti,omap5430-timer"; reg = <0x48034000 0x80>; interrupts = ; ti,hwmods = "timer3"; }; timer4: timer@48036000 { compatible = "ti,omap5430-timer"; reg = <0x48036000 0x80>; interrupts = ; ti,hwmods = "timer4"; }; timer5: timer@40138000 { compatible = "ti,omap5430-timer"; reg = <0x40138000 0x80>, <0x49038000 0x80>; interrupts = ; ti,hwmods = "timer5"; ti,timer-dsp; ti,timer-pwm; }; timer6: timer@4013a000 { compatible = "ti,omap5430-timer"; reg = <0x4013a000 0x80>, <0x4903a000 0x80>; interrupts = ; ti,hwmods = "timer6"; ti,timer-dsp; ti,timer-pwm; }; timer7: timer@4013c000 { compatible = "ti,omap5430-timer"; reg = <0x4013c000 0x80>, <0x4903c000 0x80>; interrupts = ; ti,hwmods = "timer7"; ti,timer-dsp; }; timer8: timer@4013e000 { compatible = "ti,omap5430-timer"; reg = <0x4013e000 0x80>, <0x4903e000 0x80>; interrupts = ; ti,hwmods = "timer8"; ti,timer-dsp; ti,timer-pwm; }; timer9: timer@4803e000 { compatible = "ti,omap5430-timer"; reg = <0x4803e000 0x80>; interrupts = ; ti,hwmods = "timer9"; ti,timer-pwm; }; timer10: timer@48086000 { compatible = "ti,omap5430-timer"; reg = <0x48086000 0x80>; interrupts = ; ti,hwmods = "timer10"; ti,timer-pwm; }; timer11: timer@48088000 { compatible = "ti,omap5430-timer"; reg = <0x48088000 0x80>; interrupts = ; ti,hwmods = "timer11"; ti,timer-pwm; }; wdt2: wdt@4ae14000 { compatible = "ti,omap5-wdt", "ti,omap3-wdt"; reg = <0x4ae14000 0x80>; interrupts = ; ti,hwmods = "wd_timer2"; }; dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; interrupts = <0 113 0x4>; ti,hwmods = "dmm"; }; emif1: emif@4c000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif1"; ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4c000000 0x400>; interrupts = ; hw-caps-read-idle-ctrl; hw-caps-ll-interface; hw-caps-temp-alert; }; emif2: emif@4d000000 { compatible = "ti,emif-4d5"; ti,hwmods = "emif2"; ti,no-idle-on-init; phy-type = <2>; /* DDR PHY type: Intelli PHY */ reg = <0x4d000000 0x400>; interrupts = ; hw-caps-read-idle-ctrl; hw-caps-ll-interface; hw-caps-temp-alert; }; usb3: omap_dwc3@4a020000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss"; reg = <0x4a020000 0x10000>; interrupts = ; #address-cells = <1>; #size-cells = <1>; utmi-mode = <2>; ranges; dwc3: dwc3@4a030000 { compatible = "snps,dwc3"; reg = <0x4a030000 0x10000>; interrupts = , , ; interrupt-names = "peripheral", "host", "otg"; phys = <&usb2_phy>, <&usb3_phy>; phy-names = "usb2-phy", "usb3-phy"; dr_mode = "peripheral"; }; }; ocp2scp@4a080000 { compatible = "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; reg = <0x4a080000 0x20>; ranges; ti,hwmods = "ocp2scp1"; usb2_phy: usb2phy@4a084000 { compatible = "ti,omap-usb2"; reg = <0x4a084000 0x7c>; syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy_cm_clk32k>, <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; }; usb3_phy: usb3phy@4a084400 { compatible = "ti,omap-usb3"; reg = <0x4a084400 0x80>, <0x4a084800 0x64>, <0x4a084c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy_cm_clk32k>, <&sys_clkin>, <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; clock-names = "wkupclk", "sysclk", "refclk"; #phy-cells = <0>; }; }; usbhstll: usbhstll@4a062000 { compatible = "ti,usbhs-tll"; reg = <0x4a062000 0x1000>; interrupts = ; ti,hwmods = "usb_tll_hs"; }; usbhshost: usbhshost@4a064000 { compatible = "ti,usbhs-host"; reg = <0x4a064000 0x800>; ti,hwmods = "usb_host_hs"; #address-cells = <1>; #size-cells = <1>; ranges; clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>, <&xclk60mhsp2_ck>; clock-names = "refclk_60m_int", "refclk_60m_ext_p1", "refclk_60m_ext_p2"; usbhsohci: ohci@4a064800 { compatible = "ti,ohci-omap3"; reg = <0x4a064800 0x400>; interrupts = ; remote-wakeup-connected; }; usbhsehci: ehci@4a064c00 { compatible = "ti,ehci-omap"; reg = <0x4a064c00 0x400>; interrupts = ; }; }; bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023C0 0x3c>; interrupts = ; compatible = "ti,omap5430-bandgap"; #thermal-sensor-cells = <1>; }; /* OCP2SCP3 */ ocp2scp@4a090000 { compatible = "ti,omap-ocp2scp"; #address-cells = <1>; #size-cells = <1>; reg = <0x4a090000 0x20>; ranges; ti,hwmods = "ocp2scp3"; sata_phy: phy@4a096000 { compatible = "ti,phy-pipe3-sata"; reg = <0x4A096000 0x80>, /* phy_rx */ <0x4A096400 0x64>, /* phy_tx */ <0x4A096800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; syscon-phy-power = <&scm_conf 0x374>; clocks = <&sys_clkin>, <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; clock-names = "sysclk", "refclk"; #phy-cells = <0>; }; }; sata: sata@4a141100 { compatible = "snps,dwc-ahci"; reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; interrupts = ; phys = <&sata_phy>; phy-names = "sata-phy"; clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; ti,hwmods = "sata"; ports-implemented = <0x1>; }; dss: dss@58000000 { compatible = "ti,omap5-dss"; reg = <0x58000000 0x80>; status = "disabled"; ti,hwmods = "dss_core"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; ranges; dispc@58001000 { compatible = "ti,omap5-dispc"; reg = <0x58001000 0x1000>; interrupts = ; ti,hwmods = "dss_dispc"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; clock-names = "fck"; }; rfbi: encoder@58002000 { compatible = "ti,omap5-rfbi"; reg = <0x58002000 0x100>; status = "disabled"; ti,hwmods = "dss_rfbi"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; clock-names = "fck", "ick"; }; dsi1: encoder@58004000 { compatible = "ti,omap5-dsi"; reg = <0x58004000 0x200>, <0x58004200 0x40>, <0x58004300 0x40>; reg-names = "proto", "phy", "pll"; interrupts = ; status = "disabled"; ti,hwmods = "dss_dsi1"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; dsi2: encoder@58005000 { compatible = "ti,omap5-dsi"; reg = <0x58009000 0x200>, <0x58009200 0x40>, <0x58009300 0x40>; reg-names = "proto", "phy", "pll"; interrupts = ; status = "disabled"; ti,hwmods = "dss_dsi2"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; }; hdmi: encoder@58060000 { compatible = "ti,omap5-hdmi"; reg = <0x58040000 0x200>, <0x58040200 0x80>, <0x58040300 0x80>, <0x58060000 0x19000>; reg-names = "wp", "pll", "phy", "core"; interrupts = ; status = "disabled"; ti,hwmods = "dss_hdmi"; clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; dmas = <&sdma 76>; dma-names = "audio_tx"; }; }; abb_mpu: regulator-abb-mpu { compatible = "ti,abb-v2"; regulator-name = "abb_mpu"; #address-cells = <0>; #size-cells = <0>; clocks = <&sys_clkin>; ti,settling-time = <50>; ti,clock-cycles = <16>; reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; reg-names = "base-address", "int-address", "efuse-address", "ldo-address"; ti,tranxdone-status-mask = <0x80>; /* LDOVBBMPU_MUX_CTRL */ ti,ldovbb-override-mask = <0x400>; /* LDOVBBMPU_VSET_OUT */ ti,ldovbb-vset-mask = <0x1F>; /* * NOTE: only FBB mode used but actual vset will * determine final biasing */ ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1060000 0 0x0 0 0x02000000 0x01F00000 1250000 0 0x4 0 0x02000000 0x01F00000 >; }; abb_mm: regulator-abb-mm { compatible = "ti,abb-v2"; regulator-name = "abb_mm"; #address-cells = <0>; #size-cells = <0>; clocks = <&sys_clkin>; ti,settling-time = <50>; ti,clock-cycles = <16>; reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; reg-names = "base-address", "int-address", "efuse-address", "ldo-address"; ti,tranxdone-status-mask = <0x80000000>; /* LDOVBBMM_MUX_CTRL */ ti,ldovbb-override-mask = <0x400>; /* LDOVBBMM_VSET_OUT */ ti,ldovbb-vset-mask = <0x1F>; /* * NOTE: only FBB mode used but actual vset will * determine final biasing */ ti,abb_info = < /*uV ABB efuse rbb_m fbb_m vset_m*/ 1025000 0 0x0 0 0x02000000 0x01F00000 1120000 0 0x4 0 0x02000000 0x01F00000 >; }; }; }; &cpu_thermal { polling-delay = <500>; /* milliseconds */ coefficients = <65 (-1791)>; }; #include "omap54xx-clocks.dtsi" &gpu_thermal { coefficients = <117 (-2992)>; }; &core_thermal { coefficients = <0 2000>; };