/* * Device Tree Include file for Marvell Armada 370 and Armada XP SoC * * Copyright (C) 2012 Marvell * * Lior Amsalem * Gregory CLEMENT * Thomas Petazzoni * Ben Dooks * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. * * This file contains the definitions that are common to the Armada * 370 and Armada XP SoC. */ /include/ "skeleton.dtsi" / { model = "Marvell Armada 370 and XP SoC"; compatible = "marvell,armada_370_xp"; cpus { cpu@0 { compatible = "marvell,sheeva-v7"; }; }; mpic: interrupt-controller@d0020000 { compatible = "marvell,mpic"; #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&mpic>; ranges; serial@d0012000 { compatible = "ns16550"; reg = <0xd0012000 0x100>; reg-shift = <2>; interrupts = <41>; status = "disabled"; }; serial@d0012100 { compatible = "ns16550"; reg = <0xd0012100 0x100>; reg-shift = <2>; interrupts = <42>; status = "disabled"; }; timer@d0020300 { compatible = "marvell,armada-370-xp-timer"; reg = <0xd0020300 0x30>; interrupts = <37>, <38>, <39>, <40>; clocks = <&coreclk 2>; }; addr-decoding@d0020000 { compatible = "marvell,armada-addr-decoding-controller"; reg = <0xd0020000 0x258>; }; sata@d00a0000 { compatible = "marvell,orion-sata"; reg = <0xd00a0000 0x2400>; interrupts = <55>; clocks = <&gateclk 15>, <&gateclk 30>; clock-names = "0", "1"; status = "disabled"; }; mdio { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0xd0072004 0x4>; }; ethernet@d0070000 { compatible = "marvell,armada-370-neta"; reg = <0xd0070000 0x2500>; interrupts = <8>; status = "disabled"; }; ethernet@d0074000 { compatible = "marvell,armada-370-neta"; reg = <0xd0074000 0x2500>; interrupts = <10>; status = "disabled"; }; }; };