From df4a4eece78b484ea3c29aa1f9e9a03fcbb56c8b Mon Sep 17 00:00:00 2001 From: Marek Belisko Date: Fri, 3 May 2013 07:37:36 +0200 Subject: ASoC: McASP: Fix receive clock polarity in DAIFMT_NB_NF mode. According documentation bit ACLKRPOL is set to 0 (receiver samples data on falling edge) and when set to 1 (receiver samples data on rising edge). I2S data are always sampled on falling edge and valid during rising edge of bit clock. So in case of capture data transmitter sample data on falling edge and macsp must read then on rising edge. Signed-off-by: Marek Belisko Signed-off-by: Mark Brown --- sound/soc/davinci/davinci-mcasp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c index 9acb72c5f65c..660d00e7f6f2 100644 --- a/sound/soc/davinci/davinci-mcasp.c +++ b/sound/soc/davinci/davinci-mcasp.c @@ -566,7 +566,7 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); - mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); + mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); break; -- cgit v1.2.1