From 591d14f00796a4250d800d316e3db1fea8a57e20 Mon Sep 17 00:00:00 2001 From: Dylan Reid Date: Mon, 17 Mar 2014 22:08:49 -0700 Subject: ASoC: tegra: Use flat regcache When using an rbtree cache, there can be allocations the first time a register is accessed. This can cause an attempt to schedule while atomic in the case that the regmap is using a spinlock. This could be fixed by either initializing all the registers or using a flat cache. The register maps for tegra30_ahub and tegra30_i2s are dense and don't save much from using a tree so convert them to flat. Tegra30 changes tested on Norrin, Tegra20 changes compile. Signed-off-by: Dylan Reid Tested-by: Stephen Warren Signed-off-by: Mark Brown --- sound/soc/tegra/tegra20_das.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound/soc/tegra/tegra20_das.c') diff --git a/sound/soc/tegra/tegra20_das.c b/sound/soc/tegra/tegra20_das.c index e72392927bd2..a634f13b3ffc 100644 --- a/sound/soc/tegra/tegra20_das.c +++ b/sound/soc/tegra/tegra20_das.c @@ -128,7 +128,7 @@ static const struct regmap_config tegra20_das_regmap_config = { .max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL), .writeable_reg = tegra20_das_wr_rd_reg, .readable_reg = tegra20_das_wr_rd_reg, - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_FLAT, }; static int tegra20_das_probe(struct platform_device *pdev) -- cgit v1.2.1