From c5607d8e7a4c30d2ff62b8eefe3f977d5c71d2fe Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 13 Aug 2010 19:05:04 +0100 Subject: ASoC: Automatically calculate clock ratio for WM8580 Implement set_sysclk() and then rather than assuming 256fs use the supplied value to calculate and configure the clock ratio for the currently used sample rate. As a side effect we also end up implementing clock selection for the ADC path. In order to avoid confusion remove the existing set_clkdiv() based configuration of the clock source for the DAC and update the SMDK64xx driver (which is the only in-tree user of the CODEC). Signed-off-by: Mark Brown Acked-by: Liam Girdwood --- sound/soc/s3c24xx/smdk64xx_wm8580.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'sound/soc/s3c24xx') diff --git a/sound/soc/s3c24xx/smdk64xx_wm8580.c b/sound/soc/s3c24xx/smdk64xx_wm8580.c index 5c21e26da075..91367f7bfec3 100644 --- a/sound/soc/s3c24xx/smdk64xx_wm8580.c +++ b/sound/soc/s3c24xx/smdk64xx_wm8580.c @@ -113,14 +113,13 @@ static int smdk64xx_hw_params(struct snd_pcm_substream *substream, if (ret < 0) return ret; - /* Explicitly set WM8580-DAC to source from MCLK */ - ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_DAC_CLKSEL, - WM8580_CLKSRC_MCLK); + ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0, + SMDK64XX_WM8580_FREQ, pll_out); if (ret < 0) return ret; - ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0, - SMDK64XX_WM8580_FREQ, pll_out); + ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_PLLA, + pll_out, SND_SOC_CLOCK_IN); if (ret < 0) return ret; -- cgit v1.2.1