From a8e43c21a8a32a3af4abc605b6ebcab039f28e00 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 16 Jul 2018 08:24:45 +0200 Subject: ASoC: pxa: remove clock divider and pll setup from zylonite and magician The SSP DAI now handles the clocking setup itself, all it needs is the master clock frequency. Remove the code from Zylonite and Magician platforms. Signed-off-by: Daniel Mack Signed-off-by: Mark Brown --- sound/soc/pxa/zylonite.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'sound/soc/pxa/zylonite.c') diff --git a/sound/soc/pxa/zylonite.c b/sound/soc/pxa/zylonite.c index ba468e560dd2..230eee450f45 100644 --- a/sound/soc/pxa/zylonite.c +++ b/sound/soc/pxa/zylonite.c @@ -83,11 +83,9 @@ static int zylonite_voice_hw_params(struct snd_pcm_substream *substream, struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - unsigned int pll_out = 0; unsigned int wm9713_div = 0; int ret = 0; int rate = params_rate(params); - int width = snd_pcm_format_physical_width(params_format(params)); /* Only support ratios that we can generate neatly from the AC97 * based master clock - in particular, this excludes 44.1kHz. @@ -109,17 +107,10 @@ static int zylonite_voice_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } - /* Add 1 to the width for the leading clock cycle */ - pll_out = rate * (width + 1) * 8; - ret = snd_soc_dai_set_sysclk(cpu_dai, PXA_SSP_CLK_AUDIO, 0, 1); if (ret < 0) return ret; - ret = snd_soc_dai_set_pll(cpu_dai, 0, 0, 0, pll_out); - if (ret < 0) - return ret; - if (clk_pout) ret = snd_soc_dai_set_clkdiv(codec_dai, WM9713_PCMCLK_PLL_DIV, WM9713_PCMDIV(wm9713_div)); -- cgit v1.2.1