From cdab0d4ecc1a890aece7102c2074bf73175b9935 Mon Sep 17 00:00:00 2001 From: Anatol Pomozov Date: Thu, 29 Oct 2015 15:31:59 -0700 Subject: ASoC: rt5677: use 'active low' logic for reset pin According to the datasheet RESET is active low pin, i.e. system goes to reset state when pin signal is low. The previous implementeation was assuming the pin is configured as 'active high' in DTS. Changle the gpio handling code and DTS configuration to 'active low'. Signed-off-by: Anatol Pomozov Signed-off-by: Mark Brown --- sound/soc/codecs/rt5677.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'sound/soc/codecs/rt5677.c') diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index b4cd7e3bf5f8..f73fd125e49c 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -4766,7 +4766,7 @@ static int rt5677_remove(struct snd_soc_codec *codec) regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); - gpiod_set_value_cansleep(rt5677->reset_pin, 0); + gpiod_set_value_cansleep(rt5677->reset_pin, 1); return 0; } @@ -4781,7 +4781,7 @@ static int rt5677_suspend(struct snd_soc_codec *codec) regcache_mark_dirty(rt5677->regmap); gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); - gpiod_set_value_cansleep(rt5677->reset_pin, 0); + gpiod_set_value_cansleep(rt5677->reset_pin, 1); } return 0; @@ -4793,7 +4793,7 @@ static int rt5677_resume(struct snd_soc_codec *codec) if (!rt5677->dsp_vad_en) { gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); - gpiod_set_value_cansleep(rt5677->reset_pin, 1); + gpiod_set_value_cansleep(rt5677->reset_pin, 0); if (rt5677->pow_ldo2 || rt5677->reset_pin) msleep(10); @@ -5138,7 +5138,7 @@ static int rt5677_i2c_probe(struct i2c_client *i2c, return ret; } rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, - "realtek,reset", GPIOD_OUT_HIGH); + "realtek,reset", GPIOD_OUT_LOW); if (IS_ERR(rt5677->reset_pin)) { ret = PTR_ERR(rt5677->reset_pin); dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); -- cgit v1.2.1 From 1aa844cd56c7a2b94824f02495ff7ae5d52a7e91 Mon Sep 17 00:00:00 2001 From: Ben Zhang Date: Tue, 15 Dec 2015 13:51:25 -0800 Subject: ASoC: rt5677: Reconfigure PLL1 after resume Sometimes PLL1 stops working if the codec loses power during suspend (when pow-ldo2 or reset gpio is used). MX-7Bh(RT5677_PLL1_CTRL2) is cleared and won't be restored by regcache since it's volatile. MX-7Bh has one status bit and M code for PLL1. rt5677_set_dai_pll doesn't reconfigure PLL1 after resume because it thinks the PLL params are not changed. This patch clears the cached PLL params at resume so that rt5677_set_dai_pll can reconfigure the PLL after resume. Signed-off-by: Ben Zhang Signed-off-by: Mark Brown --- sound/soc/codecs/rt5677.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'sound/soc/codecs/rt5677.c') diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index f73fd125e49c..c404f515376e 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -4792,6 +4792,9 @@ static int rt5677_resume(struct snd_soc_codec *codec) struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); if (!rt5677->dsp_vad_en) { + rt5677->pll_src = 0; + rt5677->pll_in = 0; + rt5677->pll_out = 0; gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); gpiod_set_value_cansleep(rt5677->reset_pin, 0); if (rt5677->pow_ldo2 || rt5677->reset_pin) -- cgit v1.2.1