From 29072b96078ffde36f03d51e6b5d0cff1ba8c7df Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 28 Sep 2006 15:38:36 +0200 Subject: [MTD] NAND: add subpage write support Many SLC NANDs support up to 4 writes at one NAND page. Add support of this feature. Signed-off-by: Artem Bityutskiy --- include/linux/mtd/nand.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/linux/mtd/nand.h') diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 6fc3e07497e0..1aeedf27a1ff 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -166,6 +166,9 @@ typedef enum { * for all large page devices, as they do not support * autoincrement.*/ #define NAND_NO_READRDY 0x00000100 +/* Chip does not allow subpage writes */ +#define NAND_NO_SUBPAGE_WRITE 0x00000200 + /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS \ @@ -193,6 +196,9 @@ typedef enum { /* Nand scan has allocated controller struct */ #define NAND_CONTROLLER_ALLOC 0x80000000 +/* Cell info constants */ +#define NAND_CI_CHIPNR_MSK 0x03 +#define NAND_CI_CELLTYPE_MSK 0x0C /* * nand_state_t - chip states @@ -341,6 +347,7 @@ struct nand_buffers { * @chipsize: [INTERN] the size of one chip for multichip arrays * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf + * @subpagesize: [INTERN] holds the subpagesize * @ecclayout: [REPLACEABLE] the default ecc placement scheme * @bbt: [INTERN] bad block table pointer * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup @@ -388,6 +395,8 @@ struct nand_chip { unsigned long chipsize; int pagemask; int pagebuf; + int subpagesize; + uint8_t cellinfo; int badblockpos; nand_state_t state; -- cgit v1.2.1