From e2fccf5c15157218f0b6488168f98183f82c1eda Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Mon, 14 Dec 2015 14:53:50 +0100 Subject: mfd: fsl-imx25-tsadc: Register touchscreen ADC driver This is the core driver for imx25 touchscreen/adc driver. The module has one shared ADC and two different conversion queues which use the ADC. The two queues are identical. Both can be used for general purpose ADC but one is meant to be used for touchscreens. This driver is the core which manages the central components and registers of the TSC/ADC unit. It manages the IRQs and forwards them to the correct components. Signed-off-by: Markus Pargmann Signed-off-by: Denis Carikli [ensure correct ADC clock depending on the IPG clock] Signed-off-by: Juergen Borleis Acked-by: Jonathan Cameron Signed-off-by: Lee Jones --- include/linux/mfd/imx25-tsadc.h | 140 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 include/linux/mfd/imx25-tsadc.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/imx25-tsadc.h b/include/linux/mfd/imx25-tsadc.h new file mode 100644 index 000000000000..7fe4b8c3baac --- /dev/null +++ b/include/linux/mfd/imx25-tsadc.h @@ -0,0 +1,140 @@ +#ifndef _LINUX_INCLUDE_MFD_IMX25_TSADC_H_ +#define _LINUX_INCLUDE_MFD_IMX25_TSADC_H_ + +struct regmap; +struct clk; + +struct mx25_tsadc { + struct regmap *regs; + struct irq_domain *domain; + struct clk *clk; +}; + +#define MX25_TSC_TGCR 0x00 +#define MX25_TSC_TGSR 0x04 +#define MX25_TSC_TICR 0x08 + +/* The same register layout for TC and GC queue */ +#define MX25_ADCQ_FIFO 0x00 +#define MX25_ADCQ_CR 0x04 +#define MX25_ADCQ_SR 0x08 +#define MX25_ADCQ_MR 0x0c +#define MX25_ADCQ_ITEM_7_0 0x20 +#define MX25_ADCQ_ITEM_15_8 0x24 +#define MX25_ADCQ_CFG(n) (0x40 + ((n) * 0x4)) + +#define MX25_ADCQ_MR_MASK 0xffffffff + +/* TGCR */ +#define MX25_TGCR_PDBTIME(x) ((x) << 25) +#define MX25_TGCR_PDBTIME_MASK GENMASK(31, 25) +#define MX25_TGCR_PDBEN BIT(24) +#define MX25_TGCR_PDEN BIT(23) +#define MX25_TGCR_ADCCLKCFG(x) ((x) << 16) +#define MX25_TGCR_GET_ADCCLK(x) (((x) >> 16) & 0x1f) +#define MX25_TGCR_INTREFEN BIT(10) +#define MX25_TGCR_POWERMODE_MASK GENMASK(9, 8) +#define MX25_TGCR_POWERMODE_SAVE (1 << 8) +#define MX25_TGCR_POWERMODE_ON (2 << 8) +#define MX25_TGCR_STLC BIT(5) +#define MX25_TGCR_SLPC BIT(4) +#define MX25_TGCR_FUNC_RST BIT(2) +#define MX25_TGCR_TSC_RST BIT(1) +#define MX25_TGCR_CLK_EN BIT(0) + +/* TGSR */ +#define MX25_TGSR_SLP_INT BIT(2) +#define MX25_TGSR_GCQ_INT BIT(1) +#define MX25_TGSR_TCQ_INT BIT(0) + +/* ADCQ_ITEM_* */ +#define _MX25_ADCQ_ITEM(item, x) ((x) << ((item) * 4)) +#define MX25_ADCQ_ITEM(item, x) ((item) >= 8 ? \ + _MX25_ADCQ_ITEM((item) - 8, (x)) : _MX25_ADCQ_ITEM((item), (x))) + +/* ADCQ_FIFO (TCQFIFO and GCQFIFO) */ +#define MX25_ADCQ_FIFO_DATA(x) (((x) >> 4) & 0xfff) +#define MX25_ADCQ_FIFO_ID(x) ((x) & 0xf) + +/* ADCQ_CR (TCQR and GCQR) */ +#define MX25_ADCQ_CR_PDCFG_LEVEL BIT(19) +#define MX25_ADCQ_CR_PDMSK BIT(18) +#define MX25_ADCQ_CR_FRST BIT(17) +#define MX25_ADCQ_CR_QRST BIT(16) +#define MX25_ADCQ_CR_RWAIT_MASK GENMASK(15, 12) +#define MX25_ADCQ_CR_RWAIT(x) ((x) << 12) +#define MX25_ADCQ_CR_WMRK_MASK GENMASK(11, 8) +#define MX25_ADCQ_CR_WMRK(x) ((x) << 8) +#define MX25_ADCQ_CR_LITEMID_MASK (0xf << 4) +#define MX25_ADCQ_CR_LITEMID(x) ((x) << 4) +#define MX25_ADCQ_CR_RPT BIT(3) +#define MX25_ADCQ_CR_FQS BIT(2) +#define MX25_ADCQ_CR_QSM_MASK GENMASK(1, 0) +#define MX25_ADCQ_CR_QSM_PD 0x1 +#define MX25_ADCQ_CR_QSM_FQS 0x2 +#define MX25_ADCQ_CR_QSM_FQS_PD 0x3 + +/* ADCQ_SR (TCQSR and GCQSR) */ +#define MX25_ADCQ_SR_FDRY BIT(15) +#define MX25_ADCQ_SR_FULL BIT(14) +#define MX25_ADCQ_SR_EMPT BIT(13) +#define MX25_ADCQ_SR_FDN(x) (((x) >> 8) & 0x1f) +#define MX25_ADCQ_SR_FRR BIT(6) +#define MX25_ADCQ_SR_FUR BIT(5) +#define MX25_ADCQ_SR_FOR BIT(4) +#define MX25_ADCQ_SR_EOQ BIT(1) +#define MX25_ADCQ_SR_PD BIT(0) + +/* ADCQ_MR (TCQMR and GCQMR) */ +#define MX25_ADCQ_MR_FDRY_DMA BIT(31) +#define MX25_ADCQ_MR_FER_DMA BIT(22) +#define MX25_ADCQ_MR_FUR_DMA BIT(21) +#define MX25_ADCQ_MR_FOR_DMA BIT(20) +#define MX25_ADCQ_MR_EOQ_DMA BIT(17) +#define MX25_ADCQ_MR_PD_DMA BIT(16) +#define MX25_ADCQ_MR_FDRY_IRQ BIT(15) +#define MX25_ADCQ_MR_FER_IRQ BIT(6) +#define MX25_ADCQ_MR_FUR_IRQ BIT(5) +#define MX25_ADCQ_MR_FOR_IRQ BIT(4) +#define MX25_ADCQ_MR_EOQ_IRQ BIT(1) +#define MX25_ADCQ_MR_PD_IRQ BIT(0) + +/* ADCQ_CFG (TICR, TCC0-7,GCC0-7) */ +#define MX25_ADCQ_CFG_SETTLING_TIME(x) ((x) << 24) +#define MX25_ADCQ_CFG_IGS (1 << 20) +#define MX25_ADCQ_CFG_NOS_MASK GENMASK(19, 16) +#define MX25_ADCQ_CFG_NOS(x) (((x) - 1) << 16) +#define MX25_ADCQ_CFG_WIPER (1 << 15) +#define MX25_ADCQ_CFG_YNLR (1 << 14) +#define MX25_ADCQ_CFG_YPLL_HIGH (0 << 12) +#define MX25_ADCQ_CFG_YPLL_OFF (1 << 12) +#define MX25_ADCQ_CFG_YPLL_LOW (3 << 12) +#define MX25_ADCQ_CFG_XNUR_HIGH (0 << 10) +#define MX25_ADCQ_CFG_XNUR_OFF (1 << 10) +#define MX25_ADCQ_CFG_XNUR_LOW (3 << 10) +#define MX25_ADCQ_CFG_XPUL_HIGH (0 << 9) +#define MX25_ADCQ_CFG_XPUL_OFF (1 << 9) +#define MX25_ADCQ_CFG_REFP(sel) ((sel) << 7) +#define MX25_ADCQ_CFG_REFP_YP MX25_ADCQ_CFG_REFP(0) +#define MX25_ADCQ_CFG_REFP_XP MX25_ADCQ_CFG_REFP(1) +#define MX25_ADCQ_CFG_REFP_EXT MX25_ADCQ_CFG_REFP(2) +#define MX25_ADCQ_CFG_REFP_INT MX25_ADCQ_CFG_REFP(3) +#define MX25_ADCQ_CFG_REFP_MASK GENMASK(8, 7) +#define MX25_ADCQ_CFG_IN(sel) ((sel) << 4) +#define MX25_ADCQ_CFG_IN_XP MX25_ADCQ_CFG_IN(0) +#define MX25_ADCQ_CFG_IN_YP MX25_ADCQ_CFG_IN(1) +#define MX25_ADCQ_CFG_IN_XN MX25_ADCQ_CFG_IN(2) +#define MX25_ADCQ_CFG_IN_YN MX25_ADCQ_CFG_IN(3) +#define MX25_ADCQ_CFG_IN_WIPER MX25_ADCQ_CFG_IN(4) +#define MX25_ADCQ_CFG_IN_AUX0 MX25_ADCQ_CFG_IN(5) +#define MX25_ADCQ_CFG_IN_AUX1 MX25_ADCQ_CFG_IN(6) +#define MX25_ADCQ_CFG_IN_AUX2 MX25_ADCQ_CFG_IN(7) +#define MX25_ADCQ_CFG_REFN(sel) ((sel) << 2) +#define MX25_ADCQ_CFG_REFN_XN MX25_ADCQ_CFG_REFN(0) +#define MX25_ADCQ_CFG_REFN_YN MX25_ADCQ_CFG_REFN(1) +#define MX25_ADCQ_CFG_REFN_NGND MX25_ADCQ_CFG_REFN(2) +#define MX25_ADCQ_CFG_REFN_NGND2 MX25_ADCQ_CFG_REFN(3) +#define MX25_ADCQ_CFG_REFN_MASK GENMASK(3, 2) +#define MX25_ADCQ_CFG_PENIACK (1 << 1) + +#endif /* _LINUX_INCLUDE_MFD_IMX25_TSADC_H_ */ -- cgit v1.2.1 From 65b6555971d0498b18a0b2fdc6dd7c822f2d69b7 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 25 Jan 2016 09:43:44 -0600 Subject: mfd: tps65912: Remove old driver in preparation for new driver The old tps65912 driver is being replaced, delete old driver. Signed-off-by: Andrew F. Davis Acked-by: Mark Brown Acked-by: Linus Walleij Signed-off-by: Lee Jones --- include/linux/mfd/tps65912.h | 328 ------------------------------------------- 1 file changed, 328 deletions(-) delete mode 100644 include/linux/mfd/tps65912.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65912.h b/include/linux/mfd/tps65912.h deleted file mode 100644 index 6d309032dc0d..000000000000 --- a/include/linux/mfd/tps65912.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * tps65912.h -- TI TPS6591x - * - * Copyright 2011 Texas Instruments Inc. - * - * Author: Margarita Olaya - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifndef __LINUX_MFD_TPS65912_H -#define __LINUX_MFD_TPS65912_H - -/* TPS regulator type list */ -#define REGULATOR_LDO 0 -#define REGULATOR_DCDC 1 - -/* - * List of registers for TPS65912 - */ - -#define TPS65912_DCDC1_CTRL 0x00 -#define TPS65912_DCDC2_CTRL 0x01 -#define TPS65912_DCDC3_CTRL 0x02 -#define TPS65912_DCDC4_CTRL 0x03 -#define TPS65912_DCDC1_OP 0x04 -#define TPS65912_DCDC1_AVS 0x05 -#define TPS65912_DCDC1_LIMIT 0x06 -#define TPS65912_DCDC2_OP 0x07 -#define TPS65912_DCDC2_AVS 0x08 -#define TPS65912_DCDC2_LIMIT 0x09 -#define TPS65912_DCDC3_OP 0x0A -#define TPS65912_DCDC3_AVS 0x0B -#define TPS65912_DCDC3_LIMIT 0x0C -#define TPS65912_DCDC4_OP 0x0D -#define TPS65912_DCDC4_AVS 0x0E -#define TPS65912_DCDC4_LIMIT 0x0F -#define TPS65912_LDO1_OP 0x10 -#define TPS65912_LDO1_AVS 0x11 -#define TPS65912_LDO1_LIMIT 0x12 -#define TPS65912_LDO2_OP 0x13 -#define TPS65912_LDO2_AVS 0x14 -#define TPS65912_LDO2_LIMIT 0x15 -#define TPS65912_LDO3_OP 0x16 -#define TPS65912_LDO3_AVS 0x17 -#define TPS65912_LDO3_LIMIT 0x18 -#define TPS65912_LDO4_OP 0x19 -#define TPS65912_LDO4_AVS 0x1A -#define TPS65912_LDO4_LIMIT 0x1B -#define TPS65912_LDO5 0x1C -#define TPS65912_LDO6 0x1D -#define TPS65912_LDO7 0x1E -#define TPS65912_LDO8 0x1F -#define TPS65912_LDO9 0x20 -#define TPS65912_LDO10 0x21 -#define TPS65912_THRM 0x22 -#define TPS65912_CLK32OUT 0x23 -#define TPS65912_DEVCTRL 0x24 -#define TPS65912_DEVCTRL2 0x25 -#define TPS65912_I2C_SPI_CFG 0x26 -#define TPS65912_KEEP_ON 0x27 -#define TPS65912_KEEP_ON2 0x28 -#define TPS65912_SET_OFF1 0x29 -#define TPS65912_SET_OFF2 0x2A -#define TPS65912_DEF_VOLT 0x2B -#define TPS65912_DEF_VOLT_MAPPING 0x2C -#define TPS65912_DISCHARGE 0x2D -#define TPS65912_DISCHARGE2 0x2E -#define TPS65912_EN1_SET1 0x2F -#define TPS65912_EN1_SET2 0x30 -#define TPS65912_EN2_SET1 0x31 -#define TPS65912_EN2_SET2 0x32 -#define TPS65912_EN3_SET1 0x33 -#define TPS65912_EN3_SET2 0x34 -#define TPS65912_EN4_SET1 0x35 -#define TPS65912_EN4_SET2 0x36 -#define TPS65912_PGOOD 0x37 -#define TPS65912_PGOOD2 0x38 -#define TPS65912_INT_STS 0x39 -#define TPS65912_INT_MSK 0x3A -#define TPS65912_INT_STS2 0x3B -#define TPS65912_INT_MSK2 0x3C -#define TPS65912_INT_STS3 0x3D -#define TPS65912_INT_MSK3 0x3E -#define TPS65912_INT_STS4 0x3F -#define TPS65912_INT_MSK4 0x40 -#define TPS65912_GPIO1 0x41 -#define TPS65912_GPIO2 0x42 -#define TPS65912_GPIO3 0x43 -#define TPS65912_GPIO4 0x44 -#define TPS65912_GPIO5 0x45 -#define TPS65912_VMON 0x46 -#define TPS65912_LEDA_CTRL1 0x47 -#define TPS65912_LEDA_CTRL2 0x48 -#define TPS65912_LEDA_CTRL3 0x49 -#define TPS65912_LEDA_CTRL4 0x4A -#define TPS65912_LEDA_CTRL5 0x4B -#define TPS65912_LEDA_CTRL6 0x4C -#define TPS65912_LEDA_CTRL7 0x4D -#define TPS65912_LEDA_CTRL8 0x4E -#define TPS65912_LEDB_CTRL1 0x4F -#define TPS65912_LEDB_CTRL2 0x50 -#define TPS65912_LEDB_CTRL3 0x51 -#define TPS65912_LEDB_CTRL4 0x52 -#define TPS65912_LEDB_CTRL5 0x53 -#define TPS65912_LEDB_CTRL6 0x54 -#define TPS65912_LEDB_CTRL7 0x55 -#define TPS65912_LEDB_CTRL8 0x56 -#define TPS65912_LEDC_CTRL1 0x57 -#define TPS65912_LEDC_CTRL2 0x58 -#define TPS65912_LEDC_CTRL3 0x59 -#define TPS65912_LEDC_CTRL4 0x5A -#define TPS65912_LEDC_CTRL5 0x5B -#define TPS65912_LEDC_CTRL6 0x5C -#define TPS65912_LEDC_CTRL7 0x5D -#define TPS65912_LEDC_CTRL8 0x5E -#define TPS65912_LED_RAMP_UP_TIME 0x5F -#define TPS65912_LED_RAMP_DOWN_TIME 0x60 -#define TPS65912_LED_SEQ_EN 0x61 -#define TPS65912_LOADSWITCH 0x62 -#define TPS65912_SPARE 0x63 -#define TPS65912_VERNUM 0x64 -#define TPS6591X_MAX_REGISTER 0x64 - -/* IRQ Definitions */ -#define TPS65912_IRQ_PWRHOLD_F 0 -#define TPS65912_IRQ_VMON 1 -#define TPS65912_IRQ_PWRON 2 -#define TPS65912_IRQ_PWRON_LP 3 -#define TPS65912_IRQ_PWRHOLD_R 4 -#define TPS65912_IRQ_HOTDIE 5 -#define TPS65912_IRQ_GPIO1_R 6 -#define TPS65912_IRQ_GPIO1_F 7 -#define TPS65912_IRQ_GPIO2_R 8 -#define TPS65912_IRQ_GPIO2_F 9 -#define TPS65912_IRQ_GPIO3_R 10 -#define TPS65912_IRQ_GPIO3_F 11 -#define TPS65912_IRQ_GPIO4_R 12 -#define TPS65912_IRQ_GPIO4_F 13 -#define TPS65912_IRQ_GPIO5_R 14 -#define TPS65912_IRQ_GPIO5_F 15 -#define TPS65912_IRQ_PGOOD_DCDC1 16 -#define TPS65912_IRQ_PGOOD_DCDC2 17 -#define TPS65912_IRQ_PGOOD_DCDC3 18 -#define TPS65912_IRQ_PGOOD_DCDC4 19 -#define TPS65912_IRQ_PGOOD_LDO1 20 -#define TPS65912_IRQ_PGOOD_LDO2 21 -#define TPS65912_IRQ_PGOOD_LDO3 22 -#define TPS65912_IRQ_PGOOD_LDO4 23 -#define TPS65912_IRQ_PGOOD_LDO5 24 -#define TPS65912_IRQ_PGOOD_LDO6 25 -#define TPS65912_IRQ_PGOOD_LDO7 26 -#define TPS65912_IRQ_PGOOD_LD08 27 -#define TPS65912_IRQ_PGOOD_LDO9 28 -#define TPS65912_IRQ_PGOOD_LDO10 29 - -#define TPS65912_NUM_IRQ 30 - -/* GPIO 1 and 2 Register Definitions */ -#define GPIO_SLEEP_MASK 0x80 -#define GPIO_SLEEP_SHIFT 7 -#define GPIO_DEB_MASK 0x10 -#define GPIO_DEB_SHIFT 4 -#define GPIO_CFG_MASK 0x04 -#define GPIO_CFG_SHIFT 2 -#define GPIO_STS_MASK 0x02 -#define GPIO_STS_SHIFT 1 -#define GPIO_SET_MASK 0x01 -#define GPIO_SET_SHIFT 0 - -/* GPIO 3 Register Definitions */ -#define GPIO3_SLEEP_MASK 0x80 -#define GPIO3_SLEEP_SHIFT 7 -#define GPIO3_SEL_MASK 0x40 -#define GPIO3_SEL_SHIFT 6 -#define GPIO3_ODEN_MASK 0x20 -#define GPIO3_ODEN_SHIFT 5 -#define GPIO3_DEB_MASK 0x10 -#define GPIO3_DEB_SHIFT 4 -#define GPIO3_PDEN_MASK 0x08 -#define GPIO3_PDEN_SHIFT 3 -#define GPIO3_CFG_MASK 0x04 -#define GPIO3_CFG_SHIFT 2 -#define GPIO3_STS_MASK 0x02 -#define GPIO3_STS_SHIFT 1 -#define GPIO3_SET_MASK 0x01 -#define GPIO3_SET_SHIFT 0 - -/* GPIO 4 Register Definitions */ -#define GPIO4_SLEEP_MASK 0x80 -#define GPIO4_SLEEP_SHIFT 7 -#define GPIO4_SEL_MASK 0x40 -#define GPIO4_SEL_SHIFT 6 -#define GPIO4_ODEN_MASK 0x20 -#define GPIO4_ODEN_SHIFT 5 -#define GPIO4_DEB_MASK 0x10 -#define GPIO4_DEB_SHIFT 4 -#define GPIO4_PDEN_MASK 0x08 -#define GPIO4_PDEN_SHIFT 3 -#define GPIO4_CFG_MASK 0x04 -#define GPIO4_CFG_SHIFT 2 -#define GPIO4_STS_MASK 0x02 -#define GPIO4_STS_SHIFT 1 -#define GPIO4_SET_MASK 0x01 -#define GPIO4_SET_SHIFT 0 - -/* Register THERM (0x80) register.RegisterDescription */ -#define THERM_THERM_HD_MASK 0x20 -#define THERM_THERM_HD_SHIFT 5 -#define THERM_THERM_TS_MASK 0x10 -#define THERM_THERM_TS_SHIFT 4 -#define THERM_THERM_HDSEL_MASK 0x0C -#define THERM_THERM_HDSEL_SHIFT 2 -#define THERM_RSVD1_MASK 0x02 -#define THERM_RSVD1_SHIFT 1 -#define THERM_THERM_STATE_MASK 0x01 -#define THERM_THERM_STATE_SHIFT 0 - -/* Register DCDCCTRL1 register.RegisterDescription */ -#define DCDCCTRL_VCON_ENABLE_MASK 0x80 -#define DCDCCTRL_VCON_ENABLE_SHIFT 7 -#define DCDCCTRL_VCON_RANGE1_MASK 0x40 -#define DCDCCTRL_VCON_RANGE1_SHIFT 6 -#define DCDCCTRL_VCON_RANGE0_MASK 0x20 -#define DCDCCTRL_VCON_RANGE0_SHIFT 5 -#define DCDCCTRL_TSTEP2_MASK 0x10 -#define DCDCCTRL_TSTEP2_SHIFT 4 -#define DCDCCTRL_TSTEP1_MASK 0x08 -#define DCDCCTRL_TSTEP1_SHIFT 3 -#define DCDCCTRL_TSTEP0_MASK 0x04 -#define DCDCCTRL_TSTEP0_SHIFT 2 -#define DCDCCTRL_DCDC1_MODE_MASK 0x02 -#define DCDCCTRL_DCDC1_MODE_SHIFT 1 - -/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */ -#define DCDCCTRL_TSTEP2_MASK 0x10 -#define DCDCCTRL_TSTEP2_SHIFT 4 -#define DCDCCTRL_TSTEP1_MASK 0x08 -#define DCDCCTRL_TSTEP1_SHIFT 3 -#define DCDCCTRL_TSTEP0_MASK 0x04 -#define DCDCCTRL_TSTEP0_SHIFT 2 -#define DCDCCTRL_DCDC_MODE_MASK 0x02 -#define DCDCCTRL_DCDC_MODE_SHIFT 1 -#define DCDCCTRL_RSVD0_MASK 0x01 -#define DCDCCTRL_RSVD0_SHIFT 0 - -/* Register DCDCCTRL4 register.RegisterDescription */ -#define DCDCCTRL_RAMP_TIME_MASK 0x01 -#define DCDCCTRL_RAMP_TIME_SHIFT 0 - -/* Register DCDCx_AVS */ -#define DCDC_AVS_ENABLE_MASK 0x80 -#define DCDC_AVS_ENABLE_SHIFT 7 -#define DCDC_AVS_ECO_MASK 0x40 -#define DCDC_AVS_ECO_SHIFT 6 - -/* Register DCDCx_LIMIT */ -#define DCDC_LIMIT_RANGE_MASK 0xC0 -#define DCDC_LIMIT_RANGE_SHIFT 6 -#define DCDC_LIMIT_MAX_SEL_MASK 0x3F -#define DCDC_LIMIT_MAX_SEL_SHIFT 0 - -/** - * struct tps65912_board - * Board platform dat may be used to initialize regulators. - */ -struct tps65912_board { - int is_dcdc1_avs; - int is_dcdc2_avs; - int is_dcdc3_avs; - int is_dcdc4_avs; - int irq; - int irq_base; - int gpio_base; - struct regulator_init_data *tps65912_pmic_init_data; -}; - -/** - * struct tps65912 - tps65912 sub-driver chip access routines - */ - -struct tps65912 { - struct device *dev; - /* for read/write acces */ - struct mutex io_mutex; - - /* For device IO interfaces: I2C or SPI */ - void *control_data; - - int (*read)(struct tps65912 *tps65912, u8 reg, int size, void *dest); - int (*write)(struct tps65912 *tps65912, u8 reg, int size, void *src); - - /* Client devices */ - struct tps65912_pmic *pmic; - - /* GPIO Handling */ - struct gpio_chip gpio; - - /* IRQ Handling */ - struct mutex irq_lock; - int chip_irq; - int irq_base; - int irq_num; - u32 irq_mask; -}; - -struct tps65912_platform_data { - int irq; - int irq_base; -}; - -unsigned int tps_chip(void); - -int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask); -int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask); -int tps65912_reg_read(struct tps65912 *tps65912, u8 reg); -int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val); -int tps65912_device_init(struct tps65912 *tps65912); -void tps65912_device_exit(struct tps65912 *tps65912); -int tps65912_irq_init(struct tps65912 *tps65912, int irq, - struct tps65912_platform_data *pdata); -int tps65912_irq_exit(struct tps65912 *tps65912); - -#endif /* __LINUX_MFD_TPS65912_H */ -- cgit v1.2.1 From 796f5692daac4ea47fa5252af742976cd1955f0b Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 25 Jan 2016 09:43:45 -0600 Subject: mfd: tps65912: Add driver for the TPS65912 PMIC This patch adds support for TPS65912 PMIC MFD core. It provides communication through the I2C and SPI interfaces. It contains the following components: - Regulators - GPIO controller Signed-off-by: Andrew F. Davis Signed-off-by: Lee Jones --- include/linux/mfd/tps65912.h | 341 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 341 insertions(+) create mode 100644 include/linux/mfd/tps65912.h (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/tps65912.h b/include/linux/mfd/tps65912.h new file mode 100644 index 000000000000..1a603701550e --- /dev/null +++ b/include/linux/mfd/tps65912.h @@ -0,0 +1,341 @@ +/* + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * Based on the TPS65218 driver and the previous TPS65912 driver by + * Margarita Olaya Cabrera + */ + +#ifndef __LINUX_MFD_TPS65912_H +#define __LINUX_MFD_TPS65912_H + +#include +#include + +/* List of registers for TPS65912 */ +#define TPS65912_DCDC1_CTRL 0x00 +#define TPS65912_DCDC2_CTRL 0x01 +#define TPS65912_DCDC3_CTRL 0x02 +#define TPS65912_DCDC4_CTRL 0x03 +#define TPS65912_DCDC1_OP 0x04 +#define TPS65912_DCDC1_AVS 0x05 +#define TPS65912_DCDC1_LIMIT 0x06 +#define TPS65912_DCDC2_OP 0x07 +#define TPS65912_DCDC2_AVS 0x08 +#define TPS65912_DCDC2_LIMIT 0x09 +#define TPS65912_DCDC3_OP 0x0A +#define TPS65912_DCDC3_AVS 0x0B +#define TPS65912_DCDC3_LIMIT 0x0C +#define TPS65912_DCDC4_OP 0x0D +#define TPS65912_DCDC4_AVS 0x0E +#define TPS65912_DCDC4_LIMIT 0x0F +#define TPS65912_LDO1_OP 0x10 +#define TPS65912_LDO1_AVS 0x11 +#define TPS65912_LDO1_LIMIT 0x12 +#define TPS65912_LDO2_OP 0x13 +#define TPS65912_LDO2_AVS 0x14 +#define TPS65912_LDO2_LIMIT 0x15 +#define TPS65912_LDO3_OP 0x16 +#define TPS65912_LDO3_AVS 0x17 +#define TPS65912_LDO3_LIMIT 0x18 +#define TPS65912_LDO4_OP 0x19 +#define TPS65912_LDO4_AVS 0x1A +#define TPS65912_LDO4_LIMIT 0x1B +#define TPS65912_LDO5 0x1C +#define TPS65912_LDO6 0x1D +#define TPS65912_LDO7 0x1E +#define TPS65912_LDO8 0x1F +#define TPS65912_LDO9 0x20 +#define TPS65912_LDO10 0x21 +#define TPS65912_THRM 0x22 +#define TPS65912_CLK32OUT 0x23 +#define TPS65912_DEVCTRL 0x24 +#define TPS65912_DEVCTRL2 0x25 +#define TPS65912_I2C_SPI_CFG 0x26 +#define TPS65912_KEEP_ON 0x27 +#define TPS65912_KEEP_ON2 0x28 +#define TPS65912_SET_OFF1 0x29 +#define TPS65912_SET_OFF2 0x2A +#define TPS65912_DEF_VOLT 0x2B +#define TPS65912_DEF_VOLT_MAPPING 0x2C +#define TPS65912_DISCHARGE 0x2D +#define TPS65912_DISCHARGE2 0x2E +#define TPS65912_EN1_SET1 0x2F +#define TPS65912_EN1_SET2 0x30 +#define TPS65912_EN2_SET1 0x31 +#define TPS65912_EN2_SET2 0x32 +#define TPS65912_EN3_SET1 0x33 +#define TPS65912_EN3_SET2 0x34 +#define TPS65912_EN4_SET1 0x35 +#define TPS65912_EN4_SET2 0x36 +#define TPS65912_PGOOD 0x37 +#define TPS65912_PGOOD2 0x38 +#define TPS65912_INT_STS 0x39 +#define TPS65912_INT_MSK 0x3A +#define TPS65912_INT_STS2 0x3B +#define TPS65912_INT_MSK2 0x3C +#define TPS65912_INT_STS3 0x3D +#define TPS65912_INT_MSK3 0x3E +#define TPS65912_INT_STS4 0x3F +#define TPS65912_INT_MSK4 0x40 +#define TPS65912_GPIO1 0x41 +#define TPS65912_GPIO2 0x42 +#define TPS65912_GPIO3 0x43 +#define TPS65912_GPIO4 0x44 +#define TPS65912_GPIO5 0x45 +#define TPS65912_VMON 0x46 +#define TPS65912_LEDA_CTRL1 0x47 +#define TPS65912_LEDA_CTRL2 0x48 +#define TPS65912_LEDA_CTRL3 0x49 +#define TPS65912_LEDA_CTRL4 0x4A +#define TPS65912_LEDA_CTRL5 0x4B +#define TPS65912_LEDA_CTRL6 0x4C +#define TPS65912_LEDA_CTRL7 0x4D +#define TPS65912_LEDA_CTRL8 0x4E +#define TPS65912_LEDB_CTRL1 0x4F +#define TPS65912_LEDB_CTRL2 0x50 +#define TPS65912_LEDB_CTRL3 0x51 +#define TPS65912_LEDB_CTRL4 0x52 +#define TPS65912_LEDB_CTRL5 0x53 +#define TPS65912_LEDB_CTRL6 0x54 +#define TPS65912_LEDB_CTRL7 0x55 +#define TPS65912_LEDB_CTRL8 0x56 +#define TPS65912_LEDC_CTRL1 0x57 +#define TPS65912_LEDC_CTRL2 0x58 +#define TPS65912_LEDC_CTRL3 0x59 +#define TPS65912_LEDC_CTRL4 0x5A +#define TPS65912_LEDC_CTRL5 0x5B +#define TPS65912_LEDC_CTRL6 0x5C +#define TPS65912_LEDC_CTRL7 0x5D +#define TPS65912_LEDC_CTRL8 0x5E +#define TPS65912_LED_RAMP_UP_TIME 0x5F +#define TPS65912_LED_RAMP_DOWN_TIME 0x60 +#define TPS65912_LED_SEQ_EN 0x61 +#define TPS65912_LOADSWITCH 0x62 +#define TPS65912_SPARE 0x63 +#define TPS65912_VERNUM 0x64 +#define TPS6591X_MAX_REGISTER 0x64 + +/* INT_STS Register field definitions */ +#define TPS65912_INT_STS_PWRHOLD_F BIT(0) +#define TPS65912_INT_STS_VMON BIT(1) +#define TPS65912_INT_STS_PWRON BIT(2) +#define TPS65912_INT_STS_PWRON_LP BIT(3) +#define TPS65912_INT_STS_PWRHOLD_R BIT(4) +#define TPS65912_INT_STS_HOTDIE BIT(5) +#define TPS65912_INT_STS_GPIO1_R BIT(6) +#define TPS65912_INT_STS_GPIO1_F BIT(7) + +/* INT_STS Register field definitions */ +#define TPS65912_INT_STS2_GPIO2_R BIT(0) +#define TPS65912_INT_STS2_GPIO2_F BIT(1) +#define TPS65912_INT_STS2_GPIO3_R BIT(2) +#define TPS65912_INT_STS2_GPIO3_F BIT(3) +#define TPS65912_INT_STS2_GPIO4_R BIT(4) +#define TPS65912_INT_STS2_GPIO4_F BIT(5) +#define TPS65912_INT_STS2_GPIO5_R BIT(6) +#define TPS65912_INT_STS2_GPIO5_F BIT(7) + +/* INT_STS Register field definitions */ +#define TPS65912_INT_STS3_PGOOD_DCDC1 BIT(0) +#define TPS65912_INT_STS3_PGOOD_DCDC2 BIT(1) +#define TPS65912_INT_STS3_PGOOD_DCDC3 BIT(2) +#define TPS65912_INT_STS3_PGOOD_DCDC4 BIT(3) +#define TPS65912_INT_STS3_PGOOD_LDO1 BIT(4) +#define TPS65912_INT_STS3_PGOOD_LDO2 BIT(5) +#define TPS65912_INT_STS3_PGOOD_LDO3 BIT(6) +#define TPS65912_INT_STS3_PGOOD_LDO4 BIT(7) + +/* INT_STS Register field definitions */ +#define TPS65912_INT_STS4_PGOOD_LDO5 BIT(0) +#define TPS65912_INT_STS4_PGOOD_LDO6 BIT(1) +#define TPS65912_INT_STS4_PGOOD_LDO7 BIT(2) +#define TPS65912_INT_STS4_PGOOD_LDO8 BIT(3) +#define TPS65912_INT_STS4_PGOOD_LDO9 BIT(4) +#define TPS65912_INT_STS4_PGOOD_LDO10 BIT(5) + +/* GPIO 1 and 2 Register field definitions */ +#define GPIO_SLEEP_MASK 0x80 +#define GPIO_SLEEP_SHIFT 7 +#define GPIO_DEB_MASK 0x10 +#define GPIO_DEB_SHIFT 4 +#define GPIO_CFG_MASK 0x04 +#define GPIO_CFG_SHIFT 2 +#define GPIO_STS_MASK 0x02 +#define GPIO_STS_SHIFT 1 +#define GPIO_SET_MASK 0x01 +#define GPIO_SET_SHIFT 0 + +/* GPIO 3 Register field definitions */ +#define GPIO3_SLEEP_MASK 0x80 +#define GPIO3_SLEEP_SHIFT 7 +#define GPIO3_SEL_MASK 0x40 +#define GPIO3_SEL_SHIFT 6 +#define GPIO3_ODEN_MASK 0x20 +#define GPIO3_ODEN_SHIFT 5 +#define GPIO3_DEB_MASK 0x10 +#define GPIO3_DEB_SHIFT 4 +#define GPIO3_PDEN_MASK 0x08 +#define GPIO3_PDEN_SHIFT 3 +#define GPIO3_CFG_MASK 0x04 +#define GPIO3_CFG_SHIFT 2 +#define GPIO3_STS_MASK 0x02 +#define GPIO3_STS_SHIFT 1 +#define GPIO3_SET_MASK 0x01 +#define GPIO3_SET_SHIFT 0 + +/* GPIO 4 Register field definitions */ +#define GPIO4_SLEEP_MASK 0x80 +#define GPIO4_SLEEP_SHIFT 7 +#define GPIO4_SEL_MASK 0x40 +#define GPIO4_SEL_SHIFT 6 +#define GPIO4_ODEN_MASK 0x20 +#define GPIO4_ODEN_SHIFT 5 +#define GPIO4_DEB_MASK 0x10 +#define GPIO4_DEB_SHIFT 4 +#define GPIO4_PDEN_MASK 0x08 +#define GPIO4_PDEN_SHIFT 3 +#define GPIO4_CFG_MASK 0x04 +#define GPIO4_CFG_SHIFT 2 +#define GPIO4_STS_MASK 0x02 +#define GPIO4_STS_SHIFT 1 +#define GPIO4_SET_MASK 0x01 +#define GPIO4_SET_SHIFT 0 + +/* Register THERM (0x80) register.RegisterDescription */ +#define THERM_THERM_HD_MASK 0x20 +#define THERM_THERM_HD_SHIFT 5 +#define THERM_THERM_TS_MASK 0x10 +#define THERM_THERM_TS_SHIFT 4 +#define THERM_THERM_HDSEL_MASK 0x0C +#define THERM_THERM_HDSEL_SHIFT 2 +#define THERM_RSVD1_MASK 0x02 +#define THERM_RSVD1_SHIFT 1 +#define THERM_THERM_STATE_MASK 0x01 +#define THERM_THERM_STATE_SHIFT 0 + +/* Register DCDCCTRL1 register.RegisterDescription */ +#define DCDCCTRL_VCON_ENABLE_MASK 0x80 +#define DCDCCTRL_VCON_ENABLE_SHIFT 7 +#define DCDCCTRL_VCON_RANGE1_MASK 0x40 +#define DCDCCTRL_VCON_RANGE1_SHIFT 6 +#define DCDCCTRL_VCON_RANGE0_MASK 0x20 +#define DCDCCTRL_VCON_RANGE0_SHIFT 5 +#define DCDCCTRL_TSTEP2_MASK 0x10 +#define DCDCCTRL_TSTEP2_SHIFT 4 +#define DCDCCTRL_TSTEP1_MASK 0x08 +#define DCDCCTRL_TSTEP1_SHIFT 3 +#define DCDCCTRL_TSTEP0_MASK 0x04 +#define DCDCCTRL_TSTEP0_SHIFT 2 +#define DCDCCTRL_DCDC1_MODE_MASK 0x02 +#define DCDCCTRL_DCDC1_MODE_SHIFT 1 + +/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */ +#define DCDCCTRL_TSTEP2_MASK 0x10 +#define DCDCCTRL_TSTEP2_SHIFT 4 +#define DCDCCTRL_TSTEP1_MASK 0x08 +#define DCDCCTRL_TSTEP1_SHIFT 3 +#define DCDCCTRL_TSTEP0_MASK 0x04 +#define DCDCCTRL_TSTEP0_SHIFT 2 +#define DCDCCTRL_DCDC_MODE_MASK 0x02 +#define DCDCCTRL_DCDC_MODE_SHIFT 1 +#define DCDCCTRL_RSVD0_MASK 0x01 +#define DCDCCTRL_RSVD0_SHIFT 0 + +/* Register DCDCCTRL4 register.RegisterDescription */ +#define DCDCCTRL_RAMP_TIME_MASK 0x01 +#define DCDCCTRL_RAMP_TIME_SHIFT 0 + +/* Register DCDCx_AVS */ +#define DCDC_AVS_ENABLE_MASK 0x80 +#define DCDC_AVS_ENABLE_SHIFT 7 +#define DCDC_AVS_ECO_MASK 0x40 +#define DCDC_AVS_ECO_SHIFT 6 + +/* Register DCDCx_LIMIT */ +#define DCDC_LIMIT_RANGE_MASK 0xC0 +#define DCDC_LIMIT_RANGE_SHIFT 6 +#define DCDC_LIMIT_MAX_SEL_MASK 0x3F +#define DCDC_LIMIT_MAX_SEL_SHIFT 0 + +/* Define the TPS65912 IRQ numbers */ +enum tps65912_irqs { + /* INT_STS registers */ + TPS65912_IRQ_PWRHOLD_F, + TPS65912_IRQ_VMON, + TPS65912_IRQ_PWRON, + TPS65912_IRQ_PWRON_LP, + TPS65912_IRQ_PWRHOLD_R, + TPS65912_IRQ_HOTDIE, + TPS65912_IRQ_GPIO1_R, + TPS65912_IRQ_GPIO1_F, + /* INT_STS2 registers */ + TPS65912_IRQ_GPIO2_R, + TPS65912_IRQ_GPIO2_F, + TPS65912_IRQ_GPIO3_R, + TPS65912_IRQ_GPIO3_F, + TPS65912_IRQ_GPIO4_R, + TPS65912_IRQ_GPIO4_F, + TPS65912_IRQ_GPIO5_R, + TPS65912_IRQ_GPIO5_F, + /* INT_STS3 registers */ + TPS65912_IRQ_PGOOD_DCDC1, + TPS65912_IRQ_PGOOD_DCDC2, + TPS65912_IRQ_PGOOD_DCDC3, + TPS65912_IRQ_PGOOD_DCDC4, + TPS65912_IRQ_PGOOD_LDO1, + TPS65912_IRQ_PGOOD_LDO2, + TPS65912_IRQ_PGOOD_LDO3, + TPS65912_IRQ_PGOOD_LDO4, + /* INT_STS4 registers */ + TPS65912_IRQ_PGOOD_LDO5, + TPS65912_IRQ_PGOOD_LDO6, + TPS65912_IRQ_PGOOD_LDO7, + TPS65912_IRQ_PGOOD_LDO8, + TPS65912_IRQ_PGOOD_LDO9, + TPS65912_IRQ_PGOOD_LDO10, +}; + +/* + * struct tps65912 - state holder for the tps65912 driver + * + * Device data may be used to access the TPS65912 chip + */ +struct tps65912 { + struct device *dev; + struct regmap *regmap; + + /* IRQ Data */ + int irq; + struct regmap_irq_chip_data *irq_data; +}; + +static const struct regmap_range tps65912_yes_ranges[] = { + regmap_reg_range(TPS65912_INT_STS, TPS65912_GPIO5), +}; + +static const struct regmap_access_table tps65912_volatile_table = { + .yes_ranges = tps65912_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(tps65912_yes_ranges), +}; + +static const struct regmap_config tps65912_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_RBTREE, + .volatile_table = &tps65912_volatile_table, +}; + +int tps65912_device_init(struct tps65912 *tps); +int tps65912_device_exit(struct tps65912 *tps); + +#endif /* __LINUX_MFD_TPS65912_H */ -- cgit v1.2.1 From 4fd411514291ae75053003e33a6a4a56f97467d0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Feb 2016 10:02:42 +0800 Subject: mfd: axp20x: Split the driver into core and i2c bits The axp20x driver assumes the device is i2c based. This is not the case with later chips, which use a proprietary 2 wire serial bus by Allwinner called "Reduced Serial Bus". This patch follows the example of mfd/wm831x and splits it into an interface independent core, and an i2c specific glue layer. MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate symbols, allowing the driver to be built as modules. Whitespace and other style errors in the moved i2c specific code have been fixed. Included but unused header files are removed as well. Signed-off-by: Chen-Yu Tsai Signed-off-by: Lee Jones --- include/linux/mfd/axp20x.h | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index b24c771cebd5..00697c6ad8b0 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -396,7 +396,7 @@ enum axp288_irqs { struct axp20x_dev { struct device *dev; - struct i2c_client *i2c_client; + int irq; struct regmap *regmap; struct regmap_irq_chip_data *regmap_irqc; long variant; @@ -462,4 +462,35 @@ static inline int axp20x_read_variable_width(struct regmap *regmap, return result; } +/** + * axp20x_match_device(): Setup axp20x variant related fields + * + * @axp20x: axp20x device to setup (.dev field must be set) + * @dev: device associated with this axp20x device + * + * This lets the axp20x core configure the mfd cells and register maps + * for later use. + */ +int axp20x_match_device(struct axp20x_dev *axp20x); + +/** + * axp20x_device_probe(): Probe a configured axp20x device + * + * @axp20x: axp20x device to probe (must be configured) + * + * This function lets the axp20x core register the axp20x mfd devices + * and irqchip. The axp20x device passed in must be fully configured + * with axp20x_match_device, its irq set, and regmap created. + */ +int axp20x_device_probe(struct axp20x_dev *axp20x); + +/** + * axp20x_device_probe(): Remove a axp20x device + * + * @axp20x: axp20x device to remove + * + * This tells the axp20x core to remove the associated mfd devices + */ +int axp20x_device_remove(struct axp20x_dev *axp20x); + #endif /* __LINUX_MFD_AXP20X_H */ -- cgit v1.2.1 From 02071f0f797c989b342f46fbdf472ddb1c2cdee9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Feb 2016 10:02:44 +0800 Subject: mfd: axp20x: Add support for RSB based AXP223 PMIC The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs. It is functionally identical to AXP221; only the regulator default voltage/status and the external host interface are different. Signed-off-by: Chen-Yu Tsai Signed-off-by: Lee Jones --- include/linux/mfd/axp20x.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/mfd') diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 00697c6ad8b0..d82e7d51372b 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -18,6 +18,7 @@ enum { AXP202_ID, AXP209_ID, AXP221_ID, + AXP223_ID, AXP288_ID, NR_AXP20X_VARIANTS, }; -- cgit v1.2.1