From 7043ad4f4c81914ca9e2cd2208c8f4801ed63735 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 22 Dec 2005 13:41:29 +0100 Subject: MIPS: R2: Try to bulletproof instruction_hazard against miss-compilation. Gcc has a tradition of misscompiling the previous construct using the address of a label as argument to inline assembler. Gas otoh has the annoying difference between la and dla which are only usable for 32-bit rsp. 64-bit code, so can't be used without conditional compilation. The alterantive is switching the assembler to 64-bit code which happens to work right even for 32-bit code ... Signed-off-by: Ralf Baechle --- include/asm-mips/hazards.h | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) (limited to 'include/asm-mips') diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 7517189e469f..2fc90632f88c 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -233,15 +233,25 @@ __asm__( #endif #ifdef CONFIG_CPU_MIPSR2 +/* + * gcc has a tradition of misscompiling the previous construct using the + * address of a label as argument to inline assembler. Gas otoh has the + * annoying difference between la and dla which are only usable for 32-bit + * rsp. 64-bit code, so can't be used without conditional compilation. + * The alterantive is switching the assembler to 64-bit code which happens + * to work right even for 32-bit code ... + */ #define instruction_hazard() \ do { \ -__label__ __next; \ + unsigned long tmp; \ + \ __asm__ __volatile__( \ + " .set mips64r2 \n" \ + " dla %0, 1f \n" \ " jr.hb %0 \n" \ - : \ - : "r" (&&__next)); \ -__next: \ - ; \ + " .set mips0 \n" \ + "1: \n" \ + : "=r" (tmp)); \ } while (0) #else -- cgit v1.2.1