From 641e97f318870921d048154af6807e46e43c307a Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:05 +0100 Subject: [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle --- include/asm-mips/linkage.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/asm-mips/linkage.h') diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h index b6185d3cfe68..e9a940d1b0c6 100644 --- a/include/asm-mips/linkage.h +++ b/include/asm-mips/linkage.h @@ -5,4 +5,6 @@ #include #endif +#define __weak __attribute__((weak)) + #endif -- cgit v1.2.1