From 5cedae9ca752a43cfb1074907d12c9f01fbebd45 Mon Sep 17 00:00:00 2001 From: Deepak Saxena Date: Wed, 31 May 2006 16:14:05 -0700 Subject: [PATCH] ARM: Fix XScale PMD setting The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation defined" and it must be set to zero on Intel XScale CPUs or the cache does not behave properly. Found by Mike Rapoport while debugging a flash issue on the PXA255: http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1 Signed-off-by: Deepak Saxena Signed-off-by: Linus Torvalds --- include/asm-arm/system.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/asm-arm/system.h') diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 95b3abf4851b..7c9568d30307 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -127,6 +127,12 @@ static inline int cpu_is_xsc3(void) } #endif +#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) +#define cpu_is_xscale() 0 +#else +#define cpu_is_xscale() 1 +#endif + #define set_cr(x) \ __asm__ __volatile__( \ "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ -- cgit v1.2.1