From 2f85f97e460a4bcfad678151fcc13dbf0b8181b3 Mon Sep 17 00:00:00 2001 From: Ajay Kumar Date: Mon, 5 Nov 2012 16:47:00 +0900 Subject: video: exynos_dp: Fix incorrect setting for INT_CTL INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL. This patch fixes the wrong register setting for INT_CTL. Signed-off-by: Ajay Kumar Signed-off-by: Jingoo Han --- drivers/video/exynos/exynos_dp_reg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/video/exynos/exynos_dp_reg.h') diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h index 1f2f014cfe88..2e9bd0e0b9f2 100644 --- a/drivers/video/exynos/exynos_dp_reg.h +++ b/drivers/video/exynos/exynos_dp_reg.h @@ -242,7 +242,8 @@ /* EXYNOS_DP_INT_CTL */ #define SOFT_INT_CTRL (0x1 << 2) -#define INT_POL (0x1 << 0) +#define INT_POL1 (0x1 << 1) +#define INT_POL0 (0x1 << 0) /* EXYNOS_DP_SYS_CTL_1 */ #define DET_STA (0x1 << 2) -- cgit v1.2.1