From d6fe89b0630080e2bd6ece20ff7b1b5c2647ed62 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Mon, 11 Jun 2007 17:34:17 +0800 Subject: Blackfin SPI driver: fix bug SPI DMA incomplete transmission SPI writes intermittently drop bytes at end of DMA transfer http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3205 http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=2892 Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- drivers/spi/spi_bfin5xx.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c index a2d4884752ef..48587c27050d 100644 --- a/drivers/spi/spi_bfin5xx.c +++ b/drivers/spi/spi_bfin5xx.c @@ -582,14 +582,19 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); clear_dma_irqstat(CH_SPI); + /* Wait for DMA to complete */ + while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN) + continue; + /* - * wait for the last transaction shifted out. yes, these two - * while loops are supposed to be the same (see the HRM). + * wait for the last transaction shifted out. HRM states: + * at this point there may still be data in the SPI DMA FIFO waiting + * to be transmitted ... software needs to poll TXS in the SPI_STAT + * register until it goes low for 2 successive reads */ if (drv_data->tx != NULL) { - while (bfin_read_SPI_STAT() & TXS) - continue; - while (bfin_read_SPI_STAT() & TXS) + while ((bfin_read_SPI_STAT() & TXS) || + (bfin_read_SPI_STAT() & TXS)) continue; } -- cgit v1.2.1