From 69b78b8de65b28f65f2e31029462521855c7c351 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 9 Jul 2014 13:55:12 +0200 Subject: pinctrl: msm: move all qualcomm drivers to subdir We have four Qualcomm-related pin control drivers, and now there are drivers coming in for the PMICs on these systems, so let's create a qcom subdirectory to hold all the Qualcomm stuff. Acked-by: Ivan T. Ivanov Acked-by: Bjorn Andersson Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 40 +- drivers/pinctrl/Makefile | 6 +- drivers/pinctrl/pinctrl-apq8064.c | 613 ---------------- drivers/pinctrl/pinctrl-ipq8064.c | 653 ----------------- drivers/pinctrl/pinctrl-msm.c | 922 ----------------------- drivers/pinctrl/pinctrl-msm.h | 121 --- drivers/pinctrl/pinctrl-msm8960.c | 1254 -------------------------------- drivers/pinctrl/pinctrl-msm8x74.c | 1040 -------------------------- drivers/pinctrl/qcom/Kconfig | 42 ++ drivers/pinctrl/qcom/Makefile | 6 + drivers/pinctrl/qcom/pinctrl-apq8064.c | 613 ++++++++++++++++ drivers/pinctrl/qcom/pinctrl-ipq8064.c | 653 +++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.c | 922 +++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 121 +++ drivers/pinctrl/qcom/pinctrl-msm8960.c | 1254 ++++++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm8x74.c | 1040 ++++++++++++++++++++++++++ 16 files changed, 4653 insertions(+), 4647 deletions(-) delete mode 100644 drivers/pinctrl/pinctrl-apq8064.c delete mode 100644 drivers/pinctrl/pinctrl-ipq8064.c delete mode 100644 drivers/pinctrl/pinctrl-msm.c delete mode 100644 drivers/pinctrl/pinctrl-msm.h delete mode 100644 drivers/pinctrl/pinctrl-msm8960.c delete mode 100644 drivers/pinctrl/pinctrl-msm8x74.c create mode 100644 drivers/pinctrl/qcom/Kconfig create mode 100644 drivers/pinctrl/qcom/Makefile create mode 100644 drivers/pinctrl/qcom/pinctrl-apq8064.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8064.c create mode 100644 drivers/pinctrl/qcom/pinctrl-msm.c create mode 100644 drivers/pinctrl/qcom/pinctrl-msm.h create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8960.c create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8x74.c (limited to 'drivers/pinctrl') diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c0f49fb3276c..e2c7e09783fa 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -233,45 +233,6 @@ config PINCTRL_IMX28 bool select PINCTRL_MXS -config PINCTRL_MSM - bool - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB_IRQCHIP - -config PINCTRL_APQ8064 - tristate "Qualcomm APQ8064 pin controller driver" - depends on GPIOLIB && OF - select PINCTRL_MSM - help - This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm APQ8064 platform. - -config PINCTRL_IPQ8064 - tristate "Qualcomm IPQ8064 pin controller driver" - depends on GPIOLIB && OF - select PINCTRL_MSM - help - This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. - -config PINCTRL_MSM8960 - tristate "Qualcomm 8960 pin controller driver" - depends on GPIOLIB && OF - select PINCTRL_MSM - help - This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm 8960 platform. - -config PINCTRL_MSM8X74 - tristate "Qualcomm 8x74 pin controller driver" - depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST) - select PINCTRL_MSM - help - This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm 8974 platform. - config PINCTRL_NOMADIK bool "Nomadik pin controller driver" depends on ARCH_U8500 || ARCH_NOMADIK @@ -410,6 +371,7 @@ config PINCTRL_S3C64XX source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/mvebu/Kconfig" +source "drivers/pinctrl/qcom/Kconfig" source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 80bced77446a..abe17724036c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -39,11 +39,6 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o -obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o -obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o -obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o -obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o -obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o @@ -74,6 +69,7 @@ obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_PLAT_ORION) += mvebu/ +obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ obj-$(CONFIG_SUPERH) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ diff --git a/drivers/pinctrl/pinctrl-apq8064.c b/drivers/pinctrl/pinctrl-apq8064.c deleted file mode 100644 index 519f7886b0f1..000000000000 --- a/drivers/pinctrl/pinctrl-apq8064.c +++ /dev/null @@ -1,613 +0,0 @@ -/* - * Copyright (c) 2014, Sony Mobile Communications AB. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -static const struct pinctrl_pin_desc apq8064_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - PINCTRL_PIN(69, "GPIO_69"), - PINCTRL_PIN(70, "GPIO_70"), - PINCTRL_PIN(71, "GPIO_71"), - PINCTRL_PIN(72, "GPIO_72"), - PINCTRL_PIN(73, "GPIO_73"), - PINCTRL_PIN(74, "GPIO_74"), - PINCTRL_PIN(75, "GPIO_75"), - PINCTRL_PIN(76, "GPIO_76"), - PINCTRL_PIN(77, "GPIO_77"), - PINCTRL_PIN(78, "GPIO_78"), - PINCTRL_PIN(79, "GPIO_79"), - PINCTRL_PIN(80, "GPIO_80"), - PINCTRL_PIN(81, "GPIO_81"), - PINCTRL_PIN(82, "GPIO_82"), - PINCTRL_PIN(83, "GPIO_83"), - PINCTRL_PIN(84, "GPIO_84"), - PINCTRL_PIN(85, "GPIO_85"), - PINCTRL_PIN(86, "GPIO_86"), - PINCTRL_PIN(87, "GPIO_87"), - PINCTRL_PIN(88, "GPIO_88"), - PINCTRL_PIN(89, "GPIO_89"), - - PINCTRL_PIN(90, "SDC1_CLK"), - PINCTRL_PIN(91, "SDC1_CMD"), - PINCTRL_PIN(92, "SDC1_DATA"), - PINCTRL_PIN(93, "SDC3_CLK"), - PINCTRL_PIN(94, "SDC3_CMD"), - PINCTRL_PIN(95, "SDC3_DATA"), -}; - -#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_APQ_GPIO_PINS(0); -DECLARE_APQ_GPIO_PINS(1); -DECLARE_APQ_GPIO_PINS(2); -DECLARE_APQ_GPIO_PINS(3); -DECLARE_APQ_GPIO_PINS(4); -DECLARE_APQ_GPIO_PINS(5); -DECLARE_APQ_GPIO_PINS(6); -DECLARE_APQ_GPIO_PINS(7); -DECLARE_APQ_GPIO_PINS(8); -DECLARE_APQ_GPIO_PINS(9); -DECLARE_APQ_GPIO_PINS(10); -DECLARE_APQ_GPIO_PINS(11); -DECLARE_APQ_GPIO_PINS(12); -DECLARE_APQ_GPIO_PINS(13); -DECLARE_APQ_GPIO_PINS(14); -DECLARE_APQ_GPIO_PINS(15); -DECLARE_APQ_GPIO_PINS(16); -DECLARE_APQ_GPIO_PINS(17); -DECLARE_APQ_GPIO_PINS(18); -DECLARE_APQ_GPIO_PINS(19); -DECLARE_APQ_GPIO_PINS(20); -DECLARE_APQ_GPIO_PINS(21); -DECLARE_APQ_GPIO_PINS(22); -DECLARE_APQ_GPIO_PINS(23); -DECLARE_APQ_GPIO_PINS(24); -DECLARE_APQ_GPIO_PINS(25); -DECLARE_APQ_GPIO_PINS(26); -DECLARE_APQ_GPIO_PINS(27); -DECLARE_APQ_GPIO_PINS(28); -DECLARE_APQ_GPIO_PINS(29); -DECLARE_APQ_GPIO_PINS(30); -DECLARE_APQ_GPIO_PINS(31); -DECLARE_APQ_GPIO_PINS(32); -DECLARE_APQ_GPIO_PINS(33); -DECLARE_APQ_GPIO_PINS(34); -DECLARE_APQ_GPIO_PINS(35); -DECLARE_APQ_GPIO_PINS(36); -DECLARE_APQ_GPIO_PINS(37); -DECLARE_APQ_GPIO_PINS(38); -DECLARE_APQ_GPIO_PINS(39); -DECLARE_APQ_GPIO_PINS(40); -DECLARE_APQ_GPIO_PINS(41); -DECLARE_APQ_GPIO_PINS(42); -DECLARE_APQ_GPIO_PINS(43); -DECLARE_APQ_GPIO_PINS(44); -DECLARE_APQ_GPIO_PINS(45); -DECLARE_APQ_GPIO_PINS(46); -DECLARE_APQ_GPIO_PINS(47); -DECLARE_APQ_GPIO_PINS(48); -DECLARE_APQ_GPIO_PINS(49); -DECLARE_APQ_GPIO_PINS(50); -DECLARE_APQ_GPIO_PINS(51); -DECLARE_APQ_GPIO_PINS(52); -DECLARE_APQ_GPIO_PINS(53); -DECLARE_APQ_GPIO_PINS(54); -DECLARE_APQ_GPIO_PINS(55); -DECLARE_APQ_GPIO_PINS(56); -DECLARE_APQ_GPIO_PINS(57); -DECLARE_APQ_GPIO_PINS(58); -DECLARE_APQ_GPIO_PINS(59); -DECLARE_APQ_GPIO_PINS(60); -DECLARE_APQ_GPIO_PINS(61); -DECLARE_APQ_GPIO_PINS(62); -DECLARE_APQ_GPIO_PINS(63); -DECLARE_APQ_GPIO_PINS(64); -DECLARE_APQ_GPIO_PINS(65); -DECLARE_APQ_GPIO_PINS(66); -DECLARE_APQ_GPIO_PINS(67); -DECLARE_APQ_GPIO_PINS(68); -DECLARE_APQ_GPIO_PINS(69); -DECLARE_APQ_GPIO_PINS(70); -DECLARE_APQ_GPIO_PINS(71); -DECLARE_APQ_GPIO_PINS(72); -DECLARE_APQ_GPIO_PINS(73); -DECLARE_APQ_GPIO_PINS(74); -DECLARE_APQ_GPIO_PINS(75); -DECLARE_APQ_GPIO_PINS(76); -DECLARE_APQ_GPIO_PINS(77); -DECLARE_APQ_GPIO_PINS(78); -DECLARE_APQ_GPIO_PINS(79); -DECLARE_APQ_GPIO_PINS(80); -DECLARE_APQ_GPIO_PINS(81); -DECLARE_APQ_GPIO_PINS(82); -DECLARE_APQ_GPIO_PINS(83); -DECLARE_APQ_GPIO_PINS(84); -DECLARE_APQ_GPIO_PINS(85); -DECLARE_APQ_GPIO_PINS(86); -DECLARE_APQ_GPIO_PINS(87); -DECLARE_APQ_GPIO_PINS(88); -DECLARE_APQ_GPIO_PINS(89); - -static const unsigned int sdc1_clk_pins[] = { 90 }; -static const unsigned int sdc1_cmd_pins[] = { 91 }; -static const unsigned int sdc1_data_pins[] = { 92 }; -static const unsigned int sdc3_clk_pins[] = { 93 }; -static const unsigned int sdc3_cmd_pins[] = { 94 }; -static const unsigned int sdc3_data_pins[] = { 95 }; - -#define FUNCTION(fname) \ - [APQ_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - APQ_MUX_NA, /* gpio mode */ \ - APQ_MUX_##f1, \ - APQ_MUX_##f2, \ - APQ_MUX_##f3, \ - APQ_MUX_##f4, \ - APQ_MUX_##f5, \ - APQ_MUX_##f6, \ - APQ_MUX_##f7, \ - APQ_MUX_##f8, \ - APQ_MUX_##f9, \ - APQ_MUX_##f10, \ - }, \ - .nfuncs = 11, \ - .ctl_reg = 0x1000 + 0x10 * id, \ - .io_reg = 0x1004 + 0x10 * id, \ - .intr_cfg_reg = 0x1008 + 0x10 * id, \ - .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x400 + 0x4 * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_ack_high = 1, \ - .intr_target_bit = 0, \ - .intr_raw_status_bit = 3, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 1, \ - } - -#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -enum apq8064_functions { - APQ_MUX_cam_mclk, - APQ_MUX_codec_mic_i2s, - APQ_MUX_codec_spkr_i2s, - APQ_MUX_gsbi1, - APQ_MUX_gsbi2, - APQ_MUX_gsbi3, - APQ_MUX_gsbi4, - APQ_MUX_gsbi4_cam_i2c, - APQ_MUX_gsbi5, - APQ_MUX_gsbi5_spi_cs1, - APQ_MUX_gsbi5_spi_cs2, - APQ_MUX_gsbi5_spi_cs3, - APQ_MUX_gsbi6, - APQ_MUX_gsbi6_spi_cs1, - APQ_MUX_gsbi6_spi_cs2, - APQ_MUX_gsbi6_spi_cs3, - APQ_MUX_gsbi7, - APQ_MUX_gsbi7_spi_cs1, - APQ_MUX_gsbi7_spi_cs2, - APQ_MUX_gsbi7_spi_cs3, - APQ_MUX_gsbi_cam_i2c, - APQ_MUX_hdmi, - APQ_MUX_mi2s, - APQ_MUX_riva_bt, - APQ_MUX_riva_fm, - APQ_MUX_riva_wlan, - APQ_MUX_sdc2, - APQ_MUX_sdc4, - APQ_MUX_slimbus, - APQ_MUX_spkr_i2s, - APQ_MUX_tsif1, - APQ_MUX_tsif2, - APQ_MUX_usb2_hsic, - APQ_MUX_NA, -}; - -static const char * const cam_mclk_groups[] = { - "gpio4" "gpio5" -}; -static const char * const codec_mic_i2s_groups[] = { - "gpio34", "gpio35", "gpio36", "gpio37", "gpio38" -}; -static const char * const codec_spkr_i2s_groups[] = { - "gpio39", "gpio40", "gpio41", "gpio42" -}; -static const char * const gsbi1_groups[] = { - "gpio18", "gpio19", "gpio20", "gpio21" -}; -static const char * const gsbi2_groups[] = { - "gpio22", "gpio23", "gpio24", "gpio25" -}; -static const char * const gsbi3_groups[] = { - "gpio6", "gpio7", "gpio8", "gpio9" -}; -static const char * const gsbi4_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13" -}; -static const char * const gsbi4_cam_i2c_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13" -}; -static const char * const gsbi5_groups[] = { - "gpio51", "gpio52", "gpio53", "gpio54" -}; -static const char * const gsbi5_spi_cs1_groups[] = { - "gpio47" -}; -static const char * const gsbi5_spi_cs2_groups[] = { - "gpio31" -}; -static const char * const gsbi5_spi_cs3_groups[] = { - "gpio32" -}; -static const char * const gsbi6_groups[] = { - "gpio14", "gpio15", "gpio16", "gpio17" -}; -static const char * const gsbi6_spi_cs1_groups[] = { - "gpio47" -}; -static const char * const gsbi6_spi_cs2_groups[] = { - "gpio31" -}; -static const char * const gsbi6_spi_cs3_groups[] = { - "gpio32" -}; -static const char * const gsbi7_groups[] = { - "gpio82", "gpio83", "gpio84", "gpio85" -}; -static const char * const gsbi7_spi_cs1_groups[] = { - "gpio47" -}; -static const char * const gsbi7_spi_cs2_groups[] = { - "gpio31" -}; -static const char * const gsbi7_spi_cs3_groups[] = { - "gpio32" -}; -static const char * const gsbi_cam_i2c_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13" -}; -static const char * const hdmi_groups[] = { - "gpio69", "gpio70", "gpio71", "gpio72" -}; -static const char * const mi2s_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33" -}; -static const char * const riva_bt_groups[] = { - "gpio16", "gpio17" -}; -static const char * const riva_fm_groups[] = { - "gpio14", "gpio15" -}; -static const char * const riva_wlan_groups[] = { - "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" -}; -static const char * const sdc2_groups[] = { - "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62" -}; -static const char * const sdc4_groups[] = { - "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" -}; -static const char * const slimbus_groups[] = { - "gpio40", "gpio41" -}; -static const char * const spkr_i2s_groups[] = { - "gpio47", "gpio48", "gpio49", "gpio50" -}; -static const char * const tsif1_groups[] = { - "gpio55", "gpio56", "gpio57" -}; -static const char * const tsif2_groups[] = { - "gpio58", "gpio59", "gpio60" -}; -static const char * const usb2_hsic_groups[] = { - "gpio88", "gpio89" -}; - -static const struct msm_function apq8064_functions[] = { - FUNCTION(cam_mclk), - FUNCTION(codec_mic_i2s), - FUNCTION(codec_spkr_i2s), - FUNCTION(gsbi1), - FUNCTION(gsbi2), - FUNCTION(gsbi3), - FUNCTION(gsbi4), - FUNCTION(gsbi4_cam_i2c), - FUNCTION(gsbi5), - FUNCTION(gsbi5_spi_cs1), - FUNCTION(gsbi5_spi_cs2), - FUNCTION(gsbi5_spi_cs3), - FUNCTION(gsbi6), - FUNCTION(gsbi6_spi_cs1), - FUNCTION(gsbi6_spi_cs2), - FUNCTION(gsbi6_spi_cs3), - FUNCTION(gsbi7), - FUNCTION(gsbi7_spi_cs1), - FUNCTION(gsbi7_spi_cs2), - FUNCTION(gsbi7_spi_cs3), - FUNCTION(gsbi_cam_i2c), - FUNCTION(hdmi), - FUNCTION(mi2s), - FUNCTION(riva_bt), - FUNCTION(riva_fm), - FUNCTION(riva_wlan), - FUNCTION(sdc2), - FUNCTION(sdc4), - FUNCTION(slimbus), - FUNCTION(spkr_i2s), - FUNCTION(tsif1), - FUNCTION(tsif2), - FUNCTION(usb2_hsic), -}; - -static const struct msm_pingroup apq8064_groups[] = { - PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(10, gsbi4, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c, NA), - PINGROUP(11, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c), - PINGROUP(12, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), - PINGROUP(13, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), - PINGROUP(14, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(16, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(17, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(18, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(19, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(20, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(21, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA), - PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA), - PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA), - PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(54, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(55, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(56, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(57, tsif1, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(58, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(59, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(60, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(61, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(62, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, NA, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(69, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(70, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(71, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(72, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(82, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(83, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(84, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(85, NA, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - - SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), - SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), - SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), - - SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), - SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), - SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), -}; - -#define NUM_GPIO_PINGROUPS 90 - -static const struct msm_pinctrl_soc_data apq8064_pinctrl = { - .pins = apq8064_pins, - .npins = ARRAY_SIZE(apq8064_pins), - .functions = apq8064_functions, - .nfunctions = ARRAY_SIZE(apq8064_functions), - .groups = apq8064_groups, - .ngroups = ARRAY_SIZE(apq8064_groups), - .ngpios = NUM_GPIO_PINGROUPS, -}; - -static int apq8064_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &apq8064_pinctrl); -} - -static const struct of_device_id apq8064_pinctrl_of_match[] = { - { .compatible = "qcom,apq8064-pinctrl", }, - { }, -}; - -static struct platform_driver apq8064_pinctrl_driver = { - .driver = { - .name = "apq8064-pinctrl", - .owner = THIS_MODULE, - .of_match_table = apq8064_pinctrl_of_match, - }, - .probe = apq8064_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init apq8064_pinctrl_init(void) -{ - return platform_driver_register(&apq8064_pinctrl_driver); -} -arch_initcall(apq8064_pinctrl_init); - -static void __exit apq8064_pinctrl_exit(void) -{ - platform_driver_unregister(&apq8064_pinctrl_driver); -} -module_exit(apq8064_pinctrl_exit); - -MODULE_AUTHOR("Bjorn Andersson "); -MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-ipq8064.c b/drivers/pinctrl/pinctrl-ipq8064.c deleted file mode 100644 index acafea4c3a33..000000000000 --- a/drivers/pinctrl/pinctrl-ipq8064.c +++ /dev/null @@ -1,653 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -static const struct pinctrl_pin_desc ipq8064_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - - PINCTRL_PIN(69, "SDC3_CLK"), - PINCTRL_PIN(70, "SDC3_CMD"), - PINCTRL_PIN(71, "SDC3_DATA"), -}; - -#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_IPQ_GPIO_PINS(0); -DECLARE_IPQ_GPIO_PINS(1); -DECLARE_IPQ_GPIO_PINS(2); -DECLARE_IPQ_GPIO_PINS(3); -DECLARE_IPQ_GPIO_PINS(4); -DECLARE_IPQ_GPIO_PINS(5); -DECLARE_IPQ_GPIO_PINS(6); -DECLARE_IPQ_GPIO_PINS(7); -DECLARE_IPQ_GPIO_PINS(8); -DECLARE_IPQ_GPIO_PINS(9); -DECLARE_IPQ_GPIO_PINS(10); -DECLARE_IPQ_GPIO_PINS(11); -DECLARE_IPQ_GPIO_PINS(12); -DECLARE_IPQ_GPIO_PINS(13); -DECLARE_IPQ_GPIO_PINS(14); -DECLARE_IPQ_GPIO_PINS(15); -DECLARE_IPQ_GPIO_PINS(16); -DECLARE_IPQ_GPIO_PINS(17); -DECLARE_IPQ_GPIO_PINS(18); -DECLARE_IPQ_GPIO_PINS(19); -DECLARE_IPQ_GPIO_PINS(20); -DECLARE_IPQ_GPIO_PINS(21); -DECLARE_IPQ_GPIO_PINS(22); -DECLARE_IPQ_GPIO_PINS(23); -DECLARE_IPQ_GPIO_PINS(24); -DECLARE_IPQ_GPIO_PINS(25); -DECLARE_IPQ_GPIO_PINS(26); -DECLARE_IPQ_GPIO_PINS(27); -DECLARE_IPQ_GPIO_PINS(28); -DECLARE_IPQ_GPIO_PINS(29); -DECLARE_IPQ_GPIO_PINS(30); -DECLARE_IPQ_GPIO_PINS(31); -DECLARE_IPQ_GPIO_PINS(32); -DECLARE_IPQ_GPIO_PINS(33); -DECLARE_IPQ_GPIO_PINS(34); -DECLARE_IPQ_GPIO_PINS(35); -DECLARE_IPQ_GPIO_PINS(36); -DECLARE_IPQ_GPIO_PINS(37); -DECLARE_IPQ_GPIO_PINS(38); -DECLARE_IPQ_GPIO_PINS(39); -DECLARE_IPQ_GPIO_PINS(40); -DECLARE_IPQ_GPIO_PINS(41); -DECLARE_IPQ_GPIO_PINS(42); -DECLARE_IPQ_GPIO_PINS(43); -DECLARE_IPQ_GPIO_PINS(44); -DECLARE_IPQ_GPIO_PINS(45); -DECLARE_IPQ_GPIO_PINS(46); -DECLARE_IPQ_GPIO_PINS(47); -DECLARE_IPQ_GPIO_PINS(48); -DECLARE_IPQ_GPIO_PINS(49); -DECLARE_IPQ_GPIO_PINS(50); -DECLARE_IPQ_GPIO_PINS(51); -DECLARE_IPQ_GPIO_PINS(52); -DECLARE_IPQ_GPIO_PINS(53); -DECLARE_IPQ_GPIO_PINS(54); -DECLARE_IPQ_GPIO_PINS(55); -DECLARE_IPQ_GPIO_PINS(56); -DECLARE_IPQ_GPIO_PINS(57); -DECLARE_IPQ_GPIO_PINS(58); -DECLARE_IPQ_GPIO_PINS(59); -DECLARE_IPQ_GPIO_PINS(60); -DECLARE_IPQ_GPIO_PINS(61); -DECLARE_IPQ_GPIO_PINS(62); -DECLARE_IPQ_GPIO_PINS(63); -DECLARE_IPQ_GPIO_PINS(64); -DECLARE_IPQ_GPIO_PINS(65); -DECLARE_IPQ_GPIO_PINS(66); -DECLARE_IPQ_GPIO_PINS(67); -DECLARE_IPQ_GPIO_PINS(68); - -static const unsigned int sdc3_clk_pins[] = { 69 }; -static const unsigned int sdc3_cmd_pins[] = { 70 }; -static const unsigned int sdc3_data_pins[] = { 71 }; - -#define FUNCTION(fname) \ - [IPQ_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - IPQ_MUX_NA, /* gpio mode */ \ - IPQ_MUX_##f1, \ - IPQ_MUX_##f2, \ - IPQ_MUX_##f3, \ - IPQ_MUX_##f4, \ - IPQ_MUX_##f5, \ - IPQ_MUX_##f6, \ - IPQ_MUX_##f7, \ - IPQ_MUX_##f8, \ - IPQ_MUX_##f9, \ - IPQ_MUX_##f10, \ - }, \ - .nfuncs = 11, \ - .ctl_reg = 0x1000 + 0x10 * id, \ - .io_reg = 0x1004 + 0x10 * id, \ - .intr_cfg_reg = 0x1008 + 0x10 * id, \ - .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x400 + 0x4 * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_ack_high = 1, \ - .intr_target_bit = 0, \ - .intr_raw_status_bit = 3, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 1, \ - } - -#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -enum ipq8064_functions { - IPQ_MUX_mdio, - IPQ_MUX_mi2s, - IPQ_MUX_pdm, - IPQ_MUX_ssbi, - IPQ_MUX_spmi, - IPQ_MUX_audio_pcm, - IPQ_MUX_gsbi1, - IPQ_MUX_gsbi2, - IPQ_MUX_gsbi4, - IPQ_MUX_gsbi5, - IPQ_MUX_gsbi5_spi_cs1, - IPQ_MUX_gsbi5_spi_cs2, - IPQ_MUX_gsbi5_spi_cs3, - IPQ_MUX_gsbi6, - IPQ_MUX_gsbi7, - IPQ_MUX_nss_spi, - IPQ_MUX_sdc1, - IPQ_MUX_spdif, - IPQ_MUX_nand, - IPQ_MUX_tsif1, - IPQ_MUX_tsif2, - IPQ_MUX_usb_fs_n, - IPQ_MUX_usb_fs, - IPQ_MUX_usb2_hsic, - IPQ_MUX_rgmii2, - IPQ_MUX_sata, - IPQ_MUX_pcie1_rst, - IPQ_MUX_pcie1_prsnt, - IPQ_MUX_pcie1_pwrflt, - IPQ_MUX_pcie1_pwren_n, - IPQ_MUX_pcie1_pwren, - IPQ_MUX_pcie1_clk_req, - IPQ_MUX_pcie2_rst, - IPQ_MUX_pcie2_prsnt, - IPQ_MUX_pcie2_pwrflt, - IPQ_MUX_pcie2_pwren_n, - IPQ_MUX_pcie2_pwren, - IPQ_MUX_pcie2_clk_req, - IPQ_MUX_pcie3_rst, - IPQ_MUX_pcie3_prsnt, - IPQ_MUX_pcie3_pwrflt, - IPQ_MUX_pcie3_pwren_n, - IPQ_MUX_pcie3_pwren, - IPQ_MUX_pcie3_clk_req, - IPQ_MUX_ps_hold, - IPQ_MUX_NA, -}; - -static const char * const mdio_groups[] = { - "gpio0", "gpio1", "gpio10", "gpio11", -}; - -static const char * const mi2s_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio33", "gpio55", "gpio56", "gpio57", "gpio58", -}; - -static const char * const pdm_groups[] = { - "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31", - "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58", - "gpio59", -}; - -static const char * const ssbi_groups[] = { - "gpio10", "gpio11", -}; - -static const char * const spmi_groups[] = { - "gpio10", "gpio11", -}; - -static const char * const audio_pcm_groups[] = { - "gpio14", "gpio15", "gpio16", "gpio17", -}; - -static const char * const gsbi1_groups[] = { - "gpio51", "gpio52", "gpio53", "gpio54", -}; - -static const char * const gsbi2_groups[] = { - "gpio22", "gpio23", "gpio24", "gpio25", -}; - -static const char * const gsbi4_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13", -}; - -static const char * const gsbi5_groups[] = { - "gpio18", "gpio19", "gpio20", "gpio21", -}; - -static const char * const gsbi5_spi_cs1_groups[] = { - "gpio6", "gpio61", -}; - -static const char * const gsbi5_spi_cs2_groups[] = { - "gpio7", "gpio62", -}; - -static const char * const gsbi5_spi_cs3_groups[] = { - "gpio2", -}; - -static const char * const gsbi6_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56", - "gpio57", "gpio58", -}; - -static const char * const gsbi7_groups[] = { - "gpio6", "gpio7", "gpio8", "gpio9", -}; - -static const char * const nss_spi_groups[] = { - "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56", - "gpio57", "gpio58", -}; - -static const char * const sdc1_groups[] = { - "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", - "gpio44", "gpio45", "gpio46", "gpio47", -}; - -static const char * const spdif_groups[] = { - "gpio10", "gpio48", -}; - -static const char * const nand_groups[] = { - "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", - "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", - "gpio46", "gpio47", -}; - -static const char * const tsif1_groups[] = { - "gpio55", "gpio56", "gpio57", "gpio58", -}; - -static const char * const tsif2_groups[] = { - "gpio59", "gpio60", "gpio61", "gpio62", -}; - -static const char * const usb_fs_n_groups[] = { - "gpio6", -}; - -static const char * const usb_fs_groups[] = { - "gpio6", "gpio7", "gpio8", -}; - -static const char * const usb2_hsic_groups[] = { - "gpio67", "gpio68", -}; - -static const char * const rgmii2_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", -}; - -static const char * const sata_groups[] = { - "gpio10", -}; - -static const char * const pcie1_rst_groups[] = { - "gpio3", -}; - -static const char * const pcie1_prsnt_groups[] = { - "gpio3", "gpio11", -}; - -static const char * const pcie1_pwren_n_groups[] = { - "gpio4", "gpio12", -}; - -static const char * const pcie1_pwren_groups[] = { - "gpio4", "gpio12", -}; - -static const char * const pcie1_pwrflt_groups[] = { - "gpio5", "gpio13", -}; - -static const char * const pcie1_clk_req_groups[] = { - "gpio5", -}; - -static const char * const pcie2_rst_groups[] = { - "gpio48", -}; - -static const char * const pcie2_prsnt_groups[] = { - "gpio11", "gpio48", -}; - -static const char * const pcie2_pwren_n_groups[] = { - "gpio12", "gpio49", -}; - -static const char * const pcie2_pwren_groups[] = { - "gpio12", "gpio49", -}; - -static const char * const pcie2_pwrflt_groups[] = { - "gpio13", "gpio50", -}; - -static const char * const pcie2_clk_req_groups[] = { - "gpio50", -}; - -static const char * const pcie3_rst_groups[] = { - "gpio63", -}; - -static const char * const pcie3_prsnt_groups[] = { - "gpio11", -}; - -static const char * const pcie3_pwren_n_groups[] = { - "gpio12", -}; - -static const char * const pcie3_pwren_groups[] = { - "gpio12", -}; - -static const char * const pcie3_pwrflt_groups[] = { - "gpio13", -}; - -static const char * const pcie3_clk_req_groups[] = { - "gpio65", -}; - -static const char * const ps_hold_groups[] = { - "gpio26", -}; - -static const struct msm_function ipq8064_functions[] = { - FUNCTION(mdio), - FUNCTION(ssbi), - FUNCTION(spmi), - FUNCTION(mi2s), - FUNCTION(pdm), - FUNCTION(audio_pcm), - FUNCTION(gsbi1), - FUNCTION(gsbi2), - FUNCTION(gsbi4), - FUNCTION(gsbi5), - FUNCTION(gsbi5_spi_cs1), - FUNCTION(gsbi5_spi_cs2), - FUNCTION(gsbi5_spi_cs3), - FUNCTION(gsbi6), - FUNCTION(gsbi7), - FUNCTION(nss_spi), - FUNCTION(sdc1), - FUNCTION(spdif), - FUNCTION(nand), - FUNCTION(tsif1), - FUNCTION(tsif2), - FUNCTION(usb_fs_n), - FUNCTION(usb_fs), - FUNCTION(usb2_hsic), - FUNCTION(rgmii2), - FUNCTION(sata), - FUNCTION(pcie1_rst), - FUNCTION(pcie1_prsnt), - FUNCTION(pcie1_pwren_n), - FUNCTION(pcie1_pwren), - FUNCTION(pcie1_pwrflt), - FUNCTION(pcie1_clk_req), - FUNCTION(pcie2_rst), - FUNCTION(pcie2_prsnt), - FUNCTION(pcie2_pwren_n), - FUNCTION(pcie2_pwren), - FUNCTION(pcie2_pwrflt), - FUNCTION(pcie2_clk_req), - FUNCTION(pcie3_rst), - FUNCTION(pcie3_prsnt), - FUNCTION(pcie3_pwren_n), - FUNCTION(pcie3_pwren), - FUNCTION(pcie3_pwrflt), - FUNCTION(pcie3_clk_req), - FUNCTION(ps_hold), -}; - -static const struct msm_pingroup ipq8064_groups[] = { - PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA), - PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA), - PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA), - PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA), - PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA), - PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA), - PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), - PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), - PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA), - PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), - PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), - SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), - SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3), - SDC_PINGROUP(sdc3_data, 0x204a, 9, 0), -}; - -#define NUM_GPIO_PINGROUPS 69 - -static const struct msm_pinctrl_soc_data ipq8064_pinctrl = { - .pins = ipq8064_pins, - .npins = ARRAY_SIZE(ipq8064_pins), - .functions = ipq8064_functions, - .nfunctions = ARRAY_SIZE(ipq8064_functions), - .groups = ipq8064_groups, - .ngroups = ARRAY_SIZE(ipq8064_groups), - .ngpios = NUM_GPIO_PINGROUPS, -}; - -static int ipq8064_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &ipq8064_pinctrl); -} - -static const struct of_device_id ipq8064_pinctrl_of_match[] = { - { .compatible = "qcom,ipq8064-pinctrl", }, - { }, -}; - -static struct platform_driver ipq8064_pinctrl_driver = { - .driver = { - .name = "ipq8064-pinctrl", - .owner = THIS_MODULE, - .of_match_table = ipq8064_pinctrl_of_match, - }, - .probe = ipq8064_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init ipq8064_pinctrl_init(void) -{ - return platform_driver_register(&ipq8064_pinctrl_driver); -} -arch_initcall(ipq8064_pinctrl_init); - -static void __exit ipq8064_pinctrl_exit(void) -{ - platform_driver_unregister(&ipq8064_pinctrl_driver); -} -module_exit(ipq8064_pinctrl_exit); - -MODULE_AUTHOR("Andy Gross "); -MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c deleted file mode 100644 index 43d47b7cff92..000000000000 --- a/drivers/pinctrl/pinctrl-msm.c +++ /dev/null @@ -1,922 +0,0 @@ -/* - * Copyright (c) 2013, Sony Mobile Communications AB. - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" -#include "pinconf.h" -#include "pinctrl-msm.h" -#include "pinctrl-utils.h" - -#define MAX_NR_GPIO 300 - -/** - * struct msm_pinctrl - state for a pinctrl-msm device - * @dev: device handle. - * @pctrl: pinctrl handle. - * @chip: gpiochip handle. - * @irq: parent irq for the TLMM irq_chip. - * @lock: Spinlock to protect register resources as well - * as msm_pinctrl data structures. - * @enabled_irqs: Bitmap of currently enabled irqs. - * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge - * detection. - * @soc; Reference to soc_data of platform specific data. - * @regs: Base address for the TLMM register map. - */ -struct msm_pinctrl { - struct device *dev; - struct pinctrl_dev *pctrl; - struct gpio_chip chip; - int irq; - - spinlock_t lock; - - DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); - DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); - - const struct msm_pinctrl_soc_data *soc; - void __iomem *regs; -}; - -static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) -{ - return container_of(gc, struct msm_pinctrl, chip); -} - -static int msm_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->ngroups; -} - -static const char *msm_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->groups[group].name; -} - -static int msm_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, - const unsigned **pins, - unsigned *num_pins) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *pins = pctrl->soc->groups[group].pins; - *num_pins = pctrl->soc->groups[group].npins; - return 0; -} - -static const struct pinctrl_ops msm_pinctrl_ops = { - .get_groups_count = msm_get_groups_count, - .get_group_name = msm_get_group_name, - .get_group_pins = msm_get_group_pins, - .dt_node_to_map = pinconf_generic_dt_node_to_map_group, - .dt_free_map = pinctrl_utils_dt_free_map, -}; - -static int msm_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->nfunctions; -} - -static const char *msm_get_function_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->functions[function].name; -} - -static int msm_get_function_groups(struct pinctrl_dev *pctldev, - unsigned function, - const char * const **groups, - unsigned * const num_groups) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctrl->soc->functions[function].groups; - *num_groups = pctrl->soc->functions[function].ngroups; - return 0; -} - -static int msm_pinmux_enable(struct pinctrl_dev *pctldev, - unsigned function, - unsigned group) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - int i; - - g = &pctrl->soc->groups[group]; - - if (WARN_ON(g->mux_bit < 0)) - return -EINVAL; - - for (i = 0; i < g->nfuncs; i++) { - if (g->funcs[i] == function) - break; - } - - if (WARN_ON(i == g->nfuncs)) - return -EINVAL; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->ctl_reg); - val &= ~(0x7 << g->mux_bit); - val |= i << g->mux_bit; - writel(val, pctrl->regs + g->ctl_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - -static const struct pinmux_ops msm_pinmux_ops = { - .get_functions_count = msm_get_functions_count, - .get_function_name = msm_get_function_name, - .get_function_groups = msm_get_function_groups, - .enable = msm_pinmux_enable, -}; - -static int msm_config_reg(struct msm_pinctrl *pctrl, - const struct msm_pingroup *g, - unsigned param, - unsigned *mask, - unsigned *bit) -{ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_PULL_DOWN: - case PIN_CONFIG_BIAS_BUS_HOLD: - case PIN_CONFIG_BIAS_PULL_UP: - *bit = g->pull_bit; - *mask = 3; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - *bit = g->drv_bit; - *mask = 7; - break; - case PIN_CONFIG_OUTPUT: - *bit = g->oe_bit; - *mask = 1; - break; - default: - dev_err(pctrl->dev, "Invalid config param %04x\n", param); - return -ENOTSUPP; - } - - return 0; -} - -static int msm_config_get(struct pinctrl_dev *pctldev, - unsigned int pin, - unsigned long *config) -{ - dev_err(pctldev->dev, "pin_config_set op not supported\n"); - return -ENOTSUPP; -} - -static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned num_configs) -{ - dev_err(pctldev->dev, "pin_config_set op not supported\n"); - return -ENOTSUPP; -} - -#define MSM_NO_PULL 0 -#define MSM_PULL_DOWN 1 -#define MSM_KEEPER 2 -#define MSM_PULL_UP 3 - -static unsigned msm_regval_to_drive(u32 val) -{ - return (val + 1) * 2; -} - -static int msm_config_group_get(struct pinctrl_dev *pctldev, - unsigned int group, - unsigned long *config) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned param = pinconf_to_config_param(*config); - unsigned mask; - unsigned arg; - unsigned bit; - int ret; - u32 val; - - g = &pctrl->soc->groups[group]; - - ret = msm_config_reg(pctrl, g, param, &mask, &bit); - if (ret < 0) - return ret; - - val = readl(pctrl->regs + g->ctl_reg); - arg = (val >> bit) & mask; - - /* Convert register value to pinconf value */ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - arg = arg == MSM_NO_PULL; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - arg = arg == MSM_PULL_DOWN; - break; - case PIN_CONFIG_BIAS_BUS_HOLD: - arg = arg == MSM_KEEPER; - break; - case PIN_CONFIG_BIAS_PULL_UP: - arg = arg == MSM_PULL_UP; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - arg = msm_regval_to_drive(arg); - break; - case PIN_CONFIG_OUTPUT: - /* Pin is not output */ - if (!arg) - return -EINVAL; - - val = readl(pctrl->regs + g->io_reg); - arg = !!(val & BIT(g->in_bit)); - break; - default: - dev_err(pctrl->dev, "Unsupported config parameter: %x\n", - param); - return -EINVAL; - } - - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int msm_config_group_set(struct pinctrl_dev *pctldev, - unsigned group, - unsigned long *configs, - unsigned num_configs) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned long flags; - unsigned param; - unsigned mask; - unsigned arg; - unsigned bit; - int ret; - u32 val; - int i; - - g = &pctrl->soc->groups[group]; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - ret = msm_config_reg(pctrl, g, param, &mask, &bit); - if (ret < 0) - return ret; - - /* Convert pinconf values to register values */ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - arg = MSM_NO_PULL; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - arg = MSM_PULL_DOWN; - break; - case PIN_CONFIG_BIAS_BUS_HOLD: - arg = MSM_KEEPER; - break; - case PIN_CONFIG_BIAS_PULL_UP: - arg = MSM_PULL_UP; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - /* Check for invalid values */ - if (arg > 16 || arg < 2 || (arg % 2) != 0) - arg = -1; - else - arg = (arg / 2) - 1; - break; - case PIN_CONFIG_OUTPUT: - /* set output value */ - spin_lock_irqsave(&pctrl->lock, flags); - val = readl(pctrl->regs + g->io_reg); - if (arg) - val |= BIT(g->out_bit); - else - val &= ~BIT(g->out_bit); - writel(val, pctrl->regs + g->io_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); - - /* enable output */ - arg = 1; - break; - default: - dev_err(pctrl->dev, "Unsupported config parameter: %x\n", - param); - return -EINVAL; - } - - /* Range-check user-supplied value */ - if (arg & ~mask) { - dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); - return -EINVAL; - } - - spin_lock_irqsave(&pctrl->lock, flags); - val = readl(pctrl->regs + g->ctl_reg); - val &= ~(mask << bit); - val |= arg << bit; - writel(val, pctrl->regs + g->ctl_reg); - spin_unlock_irqrestore(&pctrl->lock, flags); - } - - return 0; -} - -static const struct pinconf_ops msm_pinconf_ops = { - .pin_config_get = msm_config_get, - .pin_config_set = msm_config_set, - .pin_config_group_get = msm_config_group_get, - .pin_config_group_set = msm_config_group_set, -}; - -static struct pinctrl_desc msm_pinctrl_desc = { - .pctlops = &msm_pinctrl_ops, - .pmxops = &msm_pinmux_ops, - .confops = &msm_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[offset]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->ctl_reg); - val &= ~BIT(g->oe_bit); - writel(val, pctrl->regs + g->ctl_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - -static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[offset]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->io_reg); - if (value) - val |= BIT(g->out_bit); - else - val &= ~BIT(g->out_bit); - writel(val, pctrl->regs + g->io_reg); - - val = readl(pctrl->regs + g->ctl_reg); - val |= BIT(g->oe_bit); - writel(val, pctrl->regs + g->ctl_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - -static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - u32 val; - - g = &pctrl->soc->groups[offset]; - - val = readl(pctrl->regs + g->io_reg); - return !!(val & BIT(g->in_bit)); -} - -static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[offset]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->io_reg); - if (value) - val |= BIT(g->out_bit); - else - val &= ~BIT(g->out_bit); - writel(val, pctrl->regs + g->io_reg); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - -static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - return pinctrl_request_gpio(gpio); -} - -static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - return pinctrl_free_gpio(gpio); -} - -#ifdef CONFIG_DEBUG_FS -#include - -static void msm_gpio_dbg_show_one(struct seq_file *s, - struct pinctrl_dev *pctldev, - struct gpio_chip *chip, - unsigned offset, - unsigned gpio) -{ - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); - unsigned func; - int is_out; - int drive; - int pull; - u32 ctl_reg; - - static const char * const pulls[] = { - "no pull", - "pull down", - "keeper", - "pull up" - }; - - g = &pctrl->soc->groups[offset]; - ctl_reg = readl(pctrl->regs + g->ctl_reg); - - is_out = !!(ctl_reg & BIT(g->oe_bit)); - func = (ctl_reg >> g->mux_bit) & 7; - drive = (ctl_reg >> g->drv_bit) & 7; - pull = (ctl_reg >> g->pull_bit) & 3; - - seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); - seq_printf(s, " %dmA", msm_regval_to_drive(drive)); - seq_printf(s, " %s", pulls[pull]); -} - -static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - unsigned gpio = chip->base; - unsigned i; - - for (i = 0; i < chip->ngpio; i++, gpio++) { - msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); - seq_puts(s, "\n"); - } -} - -#else -#define msm_gpio_dbg_show NULL -#endif - -static struct gpio_chip msm_gpio_template = { - .direction_input = msm_gpio_direction_input, - .direction_output = msm_gpio_direction_output, - .get = msm_gpio_get, - .set = msm_gpio_set, - .request = msm_gpio_request, - .free = msm_gpio_free, - .dbg_show = msm_gpio_dbg_show, -}; - -/* For dual-edge interrupts in software, since some hardware has no - * such support: - * - * At appropriate moments, this function may be called to flip the polarity - * settings of both-edge irq lines to try and catch the next edge. - * - * The attempt is considered successful if: - * - the status bit goes high, indicating that an edge was caught, or - * - the input value of the gpio doesn't change during the attempt. - * If the value changes twice during the process, that would cause the first - * test to fail but would force the second, as two opposite - * transitions would cause a detection no matter the polarity setting. - * - * The do-loop tries to sledge-hammer closed the timing hole between - * the initial value-read and the polarity-write - if the line value changes - * during that window, an interrupt is lost, the new polarity setting is - * incorrect, and the first success test will fail, causing a retry. - * - * Algorithm comes from Google's msmgpio driver. - */ -static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, - const struct msm_pingroup *g, - struct irq_data *d) -{ - int loop_limit = 100; - unsigned val, val2, intstat; - unsigned pol; - - do { - val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); - - pol = readl(pctrl->regs + g->intr_cfg_reg); - pol ^= BIT(g->intr_polarity_bit); - writel(pol, pctrl->regs + g->intr_cfg_reg); - - val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); - intstat = readl(pctrl->regs + g->intr_status_reg); - if (intstat || (val == val2)) - return; - } while (loop_limit-- > 0); - dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", - val, val2); -} - -static void msm_gpio_irq_mask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[d->hwirq]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->intr_cfg_reg); - val &= ~BIT(g->intr_enable_bit); - writel(val, pctrl->regs + g->intr_cfg_reg); - - clear_bit(d->hwirq, pctrl->enabled_irqs); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - -static void msm_gpio_irq_unmask(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[d->hwirq]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->intr_status_reg); - val &= ~BIT(g->intr_status_bit); - writel(val, pctrl->regs + g->intr_status_reg); - - val = readl(pctrl->regs + g->intr_cfg_reg); - val |= BIT(g->intr_enable_bit); - writel(val, pctrl->regs + g->intr_cfg_reg); - - set_bit(d->hwirq, pctrl->enabled_irqs); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - -static void msm_gpio_irq_ack(struct irq_data *d) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[d->hwirq]; - - spin_lock_irqsave(&pctrl->lock, flags); - - val = readl(pctrl->regs + g->intr_status_reg); - if (g->intr_ack_high) - val |= BIT(g->intr_status_bit); - else - val &= ~BIT(g->intr_status_bit); - writel(val, pctrl->regs + g->intr_status_reg); - - if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) - msm_gpio_update_dual_edge_pos(pctrl, g, d); - - spin_unlock_irqrestore(&pctrl->lock, flags); -} - -#define INTR_TARGET_PROC_APPS 4 - -static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - const struct msm_pingroup *g; - unsigned long flags; - u32 val; - - g = &pctrl->soc->groups[d->hwirq]; - - spin_lock_irqsave(&pctrl->lock, flags); - - /* - * For hw without possibility of detecting both edges - */ - if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) - set_bit(d->hwirq, pctrl->dual_edge_irqs); - else - clear_bit(d->hwirq, pctrl->dual_edge_irqs); - - /* Route interrupts to application cpu */ - val = readl(pctrl->regs + g->intr_target_reg); - val &= ~(7 << g->intr_target_bit); - val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; - writel(val, pctrl->regs + g->intr_target_reg); - - /* Update configuration for gpio. - * RAW_STATUS_EN is left on for all gpio irqs. Due to the - * internal circuitry of TLMM, toggling the RAW_STATUS - * could cause the INTR_STATUS to be set for EDGE interrupts. - */ - val = readl(pctrl->regs + g->intr_cfg_reg); - val |= BIT(g->intr_raw_status_bit); - if (g->intr_detection_width == 2) { - val &= ~(3 << g->intr_detection_bit); - val &= ~(1 << g->intr_polarity_bit); - switch (type) { - case IRQ_TYPE_EDGE_RISING: - val |= 1 << g->intr_detection_bit; - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_EDGE_FALLING: - val |= 2 << g->intr_detection_bit; - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_EDGE_BOTH: - val |= 3 << g->intr_detection_bit; - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_LEVEL_LOW: - break; - case IRQ_TYPE_LEVEL_HIGH: - val |= BIT(g->intr_polarity_bit); - break; - } - } else if (g->intr_detection_width == 1) { - val &= ~(1 << g->intr_detection_bit); - val &= ~(1 << g->intr_polarity_bit); - switch (type) { - case IRQ_TYPE_EDGE_RISING: - val |= BIT(g->intr_detection_bit); - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_EDGE_FALLING: - val |= BIT(g->intr_detection_bit); - break; - case IRQ_TYPE_EDGE_BOTH: - val |= BIT(g->intr_detection_bit); - val |= BIT(g->intr_polarity_bit); - break; - case IRQ_TYPE_LEVEL_LOW: - break; - case IRQ_TYPE_LEVEL_HIGH: - val |= BIT(g->intr_polarity_bit); - break; - } - } else { - BUG(); - } - writel(val, pctrl->regs + g->intr_cfg_reg); - - if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) - msm_gpio_update_dual_edge_pos(pctrl, g, d); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - __irq_set_handler_locked(d->irq, handle_level_irq); - else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) - __irq_set_handler_locked(d->irq, handle_edge_irq); - - return 0; -} - -static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) -{ - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - unsigned long flags; - - spin_lock_irqsave(&pctrl->lock, flags); - - irq_set_irq_wake(pctrl->irq, on); - - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - -static struct irq_chip msm_gpio_irq_chip = { - .name = "msmgpio", - .irq_mask = msm_gpio_irq_mask, - .irq_unmask = msm_gpio_irq_unmask, - .irq_ack = msm_gpio_irq_ack, - .irq_set_type = msm_gpio_irq_set_type, - .irq_set_wake = msm_gpio_irq_set_wake, -}; - -static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -{ - struct gpio_chip *gc = irq_desc_get_handler_data(desc); - const struct msm_pingroup *g; - struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); - struct irq_chip *chip = irq_get_chip(irq); - int irq_pin; - int handled = 0; - u32 val; - int i; - - chained_irq_enter(chip, desc); - - /* - * Each pin has it's own IRQ status register, so use - * enabled_irq bitmap to limit the number of reads. - */ - for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { - g = &pctrl->soc->groups[i]; - val = readl(pctrl->regs + g->intr_status_reg); - if (val & BIT(g->intr_status_bit)) { - irq_pin = irq_find_mapping(gc->irqdomain, i); - generic_handle_irq(irq_pin); - handled++; - } - } - - /* No interrupts were flagged */ - if (handled == 0) - handle_bad_irq(irq, desc); - - chained_irq_exit(chip, desc); -} - -static int msm_gpio_init(struct msm_pinctrl *pctrl) -{ - struct gpio_chip *chip; - int ret; - unsigned ngpio = pctrl->soc->ngpios; - - if (WARN_ON(ngpio > MAX_NR_GPIO)) - return -EINVAL; - - chip = &pctrl->chip; - chip->base = 0; - chip->ngpio = ngpio; - chip->label = dev_name(pctrl->dev); - chip->dev = pctrl->dev; - chip->owner = THIS_MODULE; - chip->of_node = pctrl->dev->of_node; - - ret = gpiochip_add(&pctrl->chip); - if (ret) { - dev_err(pctrl->dev, "Failed register gpiochip\n"); - return ret; - } - - ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); - if (ret) { - dev_err(pctrl->dev, "Failed to add pin range\n"); - return ret; - } - - ret = gpiochip_irqchip_add(chip, - &msm_gpio_irq_chip, - 0, - handle_edge_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); - return -ENOSYS; - } - - gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, - msm_gpio_irq_handler); - - return 0; -} - -int msm_pinctrl_probe(struct platform_device *pdev, - const struct msm_pinctrl_soc_data *soc_data) -{ - struct msm_pinctrl *pctrl; - struct resource *res; - int ret; - - pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); - if (!pctrl) { - dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); - return -ENOMEM; - } - pctrl->dev = &pdev->dev; - pctrl->soc = soc_data; - pctrl->chip = msm_gpio_template; - - spin_lock_init(&pctrl->lock); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pctrl->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pctrl->regs)) - return PTR_ERR(pctrl->regs); - - pctrl->irq = platform_get_irq(pdev, 0); - if (pctrl->irq < 0) { - dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); - return pctrl->irq; - } - - msm_pinctrl_desc.name = dev_name(&pdev->dev); - msm_pinctrl_desc.pins = pctrl->soc->pins; - msm_pinctrl_desc.npins = pctrl->soc->npins; - pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); - if (!pctrl->pctrl) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return -ENODEV; - } - - ret = msm_gpio_init(pctrl); - if (ret) { - pinctrl_unregister(pctrl->pctrl); - return ret; - } - - platform_set_drvdata(pdev, pctrl); - - dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); - - return 0; -} -EXPORT_SYMBOL(msm_pinctrl_probe); - -int msm_pinctrl_remove(struct platform_device *pdev) -{ - struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); - int ret; - - ret = gpiochip_remove(&pctrl->chip); - if (ret) { - dev_err(&pdev->dev, "Failed to remove gpiochip\n"); - return ret; - } - - pinctrl_unregister(pctrl->pctrl); - - return 0; -} -EXPORT_SYMBOL(msm_pinctrl_remove); - diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/pinctrl-msm.h deleted file mode 100644 index 7b2a227a590a..000000000000 --- a/drivers/pinctrl/pinctrl-msm.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2013, Sony Mobile Communications AB. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __PINCTRL_MSM_H__ -#define __PINCTRL_MSM_H__ - -struct pinctrl_pin_desc; - -/** - * struct msm_function - a pinmux function - * @name: Name of the pinmux function. - * @groups: List of pingroups for this function. - * @ngroups: Number of entries in @groups. - */ -struct msm_function { - const char *name; - const char * const *groups; - unsigned ngroups; -}; - -/** - * struct msm_pingroup - Qualcomm pingroup definition - * @name: Name of the pingroup. - * @pins: A list of pins assigned to this pingroup. - * @npins: Number of entries in @pins. - * @funcs: A list of pinmux functions that can be selected for - * this group. The index of the selected function is used - * for programming the function selector. - * Entries should be indices into the groups list of the - * struct msm_pinctrl_soc_data. - * @ctl_reg: Offset of the register holding control bits for this group. - * @io_reg: Offset of the register holding input/output bits for this group. - * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. - * @intr_status_reg: Offset of the register holding the status bits for this group. - * @intr_target_reg: Offset of the register specifying routing of the interrupts - * from this group. - * @mux_bit: Offset in @ctl_reg for the pinmux function selection. - * @pull_bit: Offset in @ctl_reg for the bias configuration. - * @drv_bit: Offset in @ctl_reg for the drive strength configuration. - * @oe_bit: Offset in @ctl_reg for controlling output enable. - * @in_bit: Offset in @io_reg for the input bit value. - * @out_bit: Offset in @io_reg for the output bit value. - * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. - * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt - * status. - * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. - * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. - * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. - * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. - * @intr_detection_width: Number of bits used for specifying interrupt type, - * Should be 2 for SoCs that can detect both edges in hardware, - * otherwise 1. - */ -struct msm_pingroup { - const char *name; - const unsigned *pins; - unsigned npins; - - unsigned *funcs; - unsigned nfuncs; - - s16 ctl_reg; - s16 io_reg; - s16 intr_cfg_reg; - s16 intr_status_reg; - s16 intr_target_reg; - - unsigned mux_bit:5; - - unsigned pull_bit:5; - unsigned drv_bit:5; - - unsigned oe_bit:5; - unsigned in_bit:5; - unsigned out_bit:5; - - unsigned intr_enable_bit:5; - unsigned intr_status_bit:5; - unsigned intr_ack_high:1; - - unsigned intr_target_bit:5; - unsigned intr_raw_status_bit:5; - unsigned intr_polarity_bit:5; - unsigned intr_detection_bit:5; - unsigned intr_detection_width:5; -}; - -/** - * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration - * @pins: An array describing all pins the pin controller affects. - * @npins: The number of entries in @pins. - * @functions: An array describing all mux functions the SoC supports. - * @nfunctions: The number of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The numbmer of entries in @groups. - * @ngpio: The number of pingroups the driver should expose as GPIOs. - */ -struct msm_pinctrl_soc_data { - const struct pinctrl_pin_desc *pins; - unsigned npins; - const struct msm_function *functions; - unsigned nfunctions; - const struct msm_pingroup *groups; - unsigned ngroups; - unsigned ngpios; -}; - -int msm_pinctrl_probe(struct platform_device *pdev, - const struct msm_pinctrl_soc_data *soc_data); -int msm_pinctrl_remove(struct platform_device *pdev); - -#endif diff --git a/drivers/pinctrl/pinctrl-msm8960.c b/drivers/pinctrl/pinctrl-msm8960.c deleted file mode 100644 index 564543bb2c1c..000000000000 --- a/drivers/pinctrl/pinctrl-msm8960.c +++ /dev/null @@ -1,1254 +0,0 @@ -/* - * Copyright (c) 2014, Sony Mobile Communications AB. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -static const struct pinctrl_pin_desc msm8960_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - PINCTRL_PIN(69, "GPIO_69"), - PINCTRL_PIN(70, "GPIO_70"), - PINCTRL_PIN(71, "GPIO_71"), - PINCTRL_PIN(72, "GPIO_72"), - PINCTRL_PIN(73, "GPIO_73"), - PINCTRL_PIN(74, "GPIO_74"), - PINCTRL_PIN(75, "GPIO_75"), - PINCTRL_PIN(76, "GPIO_76"), - PINCTRL_PIN(77, "GPIO_77"), - PINCTRL_PIN(78, "GPIO_78"), - PINCTRL_PIN(79, "GPIO_79"), - PINCTRL_PIN(80, "GPIO_80"), - PINCTRL_PIN(81, "GPIO_81"), - PINCTRL_PIN(82, "GPIO_82"), - PINCTRL_PIN(83, "GPIO_83"), - PINCTRL_PIN(84, "GPIO_84"), - PINCTRL_PIN(85, "GPIO_85"), - PINCTRL_PIN(86, "GPIO_86"), - PINCTRL_PIN(87, "GPIO_87"), - PINCTRL_PIN(88, "GPIO_88"), - PINCTRL_PIN(89, "GPIO_89"), - PINCTRL_PIN(90, "GPIO_90"), - PINCTRL_PIN(91, "GPIO_91"), - PINCTRL_PIN(92, "GPIO_92"), - PINCTRL_PIN(93, "GPIO_93"), - PINCTRL_PIN(94, "GPIO_94"), - PINCTRL_PIN(95, "GPIO_95"), - PINCTRL_PIN(96, "GPIO_96"), - PINCTRL_PIN(97, "GPIO_97"), - PINCTRL_PIN(98, "GPIO_98"), - PINCTRL_PIN(99, "GPIO_99"), - PINCTRL_PIN(100, "GPIO_100"), - PINCTRL_PIN(101, "GPIO_101"), - PINCTRL_PIN(102, "GPIO_102"), - PINCTRL_PIN(103, "GPIO_103"), - PINCTRL_PIN(104, "GPIO_104"), - PINCTRL_PIN(105, "GPIO_105"), - PINCTRL_PIN(106, "GPIO_106"), - PINCTRL_PIN(107, "GPIO_107"), - PINCTRL_PIN(108, "GPIO_108"), - PINCTRL_PIN(109, "GPIO_109"), - PINCTRL_PIN(110, "GPIO_110"), - PINCTRL_PIN(111, "GPIO_111"), - PINCTRL_PIN(112, "GPIO_112"), - PINCTRL_PIN(113, "GPIO_113"), - PINCTRL_PIN(114, "GPIO_114"), - PINCTRL_PIN(115, "GPIO_115"), - PINCTRL_PIN(116, "GPIO_116"), - PINCTRL_PIN(117, "GPIO_117"), - PINCTRL_PIN(118, "GPIO_118"), - PINCTRL_PIN(119, "GPIO_119"), - PINCTRL_PIN(120, "GPIO_120"), - PINCTRL_PIN(121, "GPIO_121"), - PINCTRL_PIN(122, "GPIO_122"), - PINCTRL_PIN(123, "GPIO_123"), - PINCTRL_PIN(124, "GPIO_124"), - PINCTRL_PIN(125, "GPIO_125"), - PINCTRL_PIN(126, "GPIO_126"), - PINCTRL_PIN(127, "GPIO_127"), - PINCTRL_PIN(128, "GPIO_128"), - PINCTRL_PIN(129, "GPIO_129"), - PINCTRL_PIN(130, "GPIO_130"), - PINCTRL_PIN(131, "GPIO_131"), - PINCTRL_PIN(132, "GPIO_132"), - PINCTRL_PIN(133, "GPIO_133"), - PINCTRL_PIN(134, "GPIO_134"), - PINCTRL_PIN(135, "GPIO_135"), - PINCTRL_PIN(136, "GPIO_136"), - PINCTRL_PIN(137, "GPIO_137"), - PINCTRL_PIN(138, "GPIO_138"), - PINCTRL_PIN(139, "GPIO_139"), - PINCTRL_PIN(140, "GPIO_140"), - PINCTRL_PIN(141, "GPIO_141"), - PINCTRL_PIN(142, "GPIO_142"), - PINCTRL_PIN(143, "GPIO_143"), - PINCTRL_PIN(144, "GPIO_144"), - PINCTRL_PIN(145, "GPIO_145"), - PINCTRL_PIN(146, "GPIO_146"), - PINCTRL_PIN(147, "GPIO_147"), - PINCTRL_PIN(148, "GPIO_148"), - PINCTRL_PIN(149, "GPIO_149"), - PINCTRL_PIN(150, "GPIO_150"), - PINCTRL_PIN(151, "GPIO_151"), - - PINCTRL_PIN(152, "SDC1_CLK"), - PINCTRL_PIN(153, "SDC1_CMD"), - PINCTRL_PIN(154, "SDC1_DATA"), - PINCTRL_PIN(155, "SDC3_CLK"), - PINCTRL_PIN(156, "SDC3_CMD"), - PINCTRL_PIN(157, "SDC3_DATA"), -}; - -#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_MSM_GPIO_PINS(0); -DECLARE_MSM_GPIO_PINS(1); -DECLARE_MSM_GPIO_PINS(2); -DECLARE_MSM_GPIO_PINS(3); -DECLARE_MSM_GPIO_PINS(4); -DECLARE_MSM_GPIO_PINS(5); -DECLARE_MSM_GPIO_PINS(6); -DECLARE_MSM_GPIO_PINS(7); -DECLARE_MSM_GPIO_PINS(8); -DECLARE_MSM_GPIO_PINS(9); -DECLARE_MSM_GPIO_PINS(10); -DECLARE_MSM_GPIO_PINS(11); -DECLARE_MSM_GPIO_PINS(12); -DECLARE_MSM_GPIO_PINS(13); -DECLARE_MSM_GPIO_PINS(14); -DECLARE_MSM_GPIO_PINS(15); -DECLARE_MSM_GPIO_PINS(16); -DECLARE_MSM_GPIO_PINS(17); -DECLARE_MSM_GPIO_PINS(18); -DECLARE_MSM_GPIO_PINS(19); -DECLARE_MSM_GPIO_PINS(20); -DECLARE_MSM_GPIO_PINS(21); -DECLARE_MSM_GPIO_PINS(22); -DECLARE_MSM_GPIO_PINS(23); -DECLARE_MSM_GPIO_PINS(24); -DECLARE_MSM_GPIO_PINS(25); -DECLARE_MSM_GPIO_PINS(26); -DECLARE_MSM_GPIO_PINS(27); -DECLARE_MSM_GPIO_PINS(28); -DECLARE_MSM_GPIO_PINS(29); -DECLARE_MSM_GPIO_PINS(30); -DECLARE_MSM_GPIO_PINS(31); -DECLARE_MSM_GPIO_PINS(32); -DECLARE_MSM_GPIO_PINS(33); -DECLARE_MSM_GPIO_PINS(34); -DECLARE_MSM_GPIO_PINS(35); -DECLARE_MSM_GPIO_PINS(36); -DECLARE_MSM_GPIO_PINS(37); -DECLARE_MSM_GPIO_PINS(38); -DECLARE_MSM_GPIO_PINS(39); -DECLARE_MSM_GPIO_PINS(40); -DECLARE_MSM_GPIO_PINS(41); -DECLARE_MSM_GPIO_PINS(42); -DECLARE_MSM_GPIO_PINS(43); -DECLARE_MSM_GPIO_PINS(44); -DECLARE_MSM_GPIO_PINS(45); -DECLARE_MSM_GPIO_PINS(46); -DECLARE_MSM_GPIO_PINS(47); -DECLARE_MSM_GPIO_PINS(48); -DECLARE_MSM_GPIO_PINS(49); -DECLARE_MSM_GPIO_PINS(50); -DECLARE_MSM_GPIO_PINS(51); -DECLARE_MSM_GPIO_PINS(52); -DECLARE_MSM_GPIO_PINS(53); -DECLARE_MSM_GPIO_PINS(54); -DECLARE_MSM_GPIO_PINS(55); -DECLARE_MSM_GPIO_PINS(56); -DECLARE_MSM_GPIO_PINS(57); -DECLARE_MSM_GPIO_PINS(58); -DECLARE_MSM_GPIO_PINS(59); -DECLARE_MSM_GPIO_PINS(60); -DECLARE_MSM_GPIO_PINS(61); -DECLARE_MSM_GPIO_PINS(62); -DECLARE_MSM_GPIO_PINS(63); -DECLARE_MSM_GPIO_PINS(64); -DECLARE_MSM_GPIO_PINS(65); -DECLARE_MSM_GPIO_PINS(66); -DECLARE_MSM_GPIO_PINS(67); -DECLARE_MSM_GPIO_PINS(68); -DECLARE_MSM_GPIO_PINS(69); -DECLARE_MSM_GPIO_PINS(70); -DECLARE_MSM_GPIO_PINS(71); -DECLARE_MSM_GPIO_PINS(72); -DECLARE_MSM_GPIO_PINS(73); -DECLARE_MSM_GPIO_PINS(74); -DECLARE_MSM_GPIO_PINS(75); -DECLARE_MSM_GPIO_PINS(76); -DECLARE_MSM_GPIO_PINS(77); -DECLARE_MSM_GPIO_PINS(78); -DECLARE_MSM_GPIO_PINS(79); -DECLARE_MSM_GPIO_PINS(80); -DECLARE_MSM_GPIO_PINS(81); -DECLARE_MSM_GPIO_PINS(82); -DECLARE_MSM_GPIO_PINS(83); -DECLARE_MSM_GPIO_PINS(84); -DECLARE_MSM_GPIO_PINS(85); -DECLARE_MSM_GPIO_PINS(86); -DECLARE_MSM_GPIO_PINS(87); -DECLARE_MSM_GPIO_PINS(88); -DECLARE_MSM_GPIO_PINS(89); -DECLARE_MSM_GPIO_PINS(90); -DECLARE_MSM_GPIO_PINS(91); -DECLARE_MSM_GPIO_PINS(92); -DECLARE_MSM_GPIO_PINS(93); -DECLARE_MSM_GPIO_PINS(94); -DECLARE_MSM_GPIO_PINS(95); -DECLARE_MSM_GPIO_PINS(96); -DECLARE_MSM_GPIO_PINS(97); -DECLARE_MSM_GPIO_PINS(98); -DECLARE_MSM_GPIO_PINS(99); -DECLARE_MSM_GPIO_PINS(100); -DECLARE_MSM_GPIO_PINS(101); -DECLARE_MSM_GPIO_PINS(102); -DECLARE_MSM_GPIO_PINS(103); -DECLARE_MSM_GPIO_PINS(104); -DECLARE_MSM_GPIO_PINS(105); -DECLARE_MSM_GPIO_PINS(106); -DECLARE_MSM_GPIO_PINS(107); -DECLARE_MSM_GPIO_PINS(108); -DECLARE_MSM_GPIO_PINS(109); -DECLARE_MSM_GPIO_PINS(110); -DECLARE_MSM_GPIO_PINS(111); -DECLARE_MSM_GPIO_PINS(112); -DECLARE_MSM_GPIO_PINS(113); -DECLARE_MSM_GPIO_PINS(114); -DECLARE_MSM_GPIO_PINS(115); -DECLARE_MSM_GPIO_PINS(116); -DECLARE_MSM_GPIO_PINS(117); -DECLARE_MSM_GPIO_PINS(118); -DECLARE_MSM_GPIO_PINS(119); -DECLARE_MSM_GPIO_PINS(120); -DECLARE_MSM_GPIO_PINS(121); -DECLARE_MSM_GPIO_PINS(122); -DECLARE_MSM_GPIO_PINS(123); -DECLARE_MSM_GPIO_PINS(124); -DECLARE_MSM_GPIO_PINS(125); -DECLARE_MSM_GPIO_PINS(126); -DECLARE_MSM_GPIO_PINS(127); -DECLARE_MSM_GPIO_PINS(128); -DECLARE_MSM_GPIO_PINS(129); -DECLARE_MSM_GPIO_PINS(130); -DECLARE_MSM_GPIO_PINS(131); -DECLARE_MSM_GPIO_PINS(132); -DECLARE_MSM_GPIO_PINS(133); -DECLARE_MSM_GPIO_PINS(134); -DECLARE_MSM_GPIO_PINS(135); -DECLARE_MSM_GPIO_PINS(136); -DECLARE_MSM_GPIO_PINS(137); -DECLARE_MSM_GPIO_PINS(138); -DECLARE_MSM_GPIO_PINS(139); -DECLARE_MSM_GPIO_PINS(140); -DECLARE_MSM_GPIO_PINS(141); -DECLARE_MSM_GPIO_PINS(142); -DECLARE_MSM_GPIO_PINS(143); -DECLARE_MSM_GPIO_PINS(144); -DECLARE_MSM_GPIO_PINS(145); -DECLARE_MSM_GPIO_PINS(146); -DECLARE_MSM_GPIO_PINS(147); -DECLARE_MSM_GPIO_PINS(148); -DECLARE_MSM_GPIO_PINS(149); -DECLARE_MSM_GPIO_PINS(150); -DECLARE_MSM_GPIO_PINS(151); - -static const unsigned int sdc1_clk_pins[] = { 152 }; -static const unsigned int sdc1_cmd_pins[] = { 153 }; -static const unsigned int sdc1_data_pins[] = { 154 }; -static const unsigned int sdc3_clk_pins[] = { 155 }; -static const unsigned int sdc3_cmd_pins[] = { 156 }; -static const unsigned int sdc3_data_pins[] = { 157 }; - -#define FUNCTION(fname) \ - [MSM_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - MSM_MUX_NA, /* gpio mode */ \ - MSM_MUX_##f1, \ - MSM_MUX_##f2, \ - MSM_MUX_##f3, \ - MSM_MUX_##f4, \ - MSM_MUX_##f5, \ - MSM_MUX_##f6, \ - MSM_MUX_##f7, \ - MSM_MUX_##f8, \ - MSM_MUX_##f9, \ - MSM_MUX_##f10, \ - MSM_MUX_##f11 \ - }, \ - .nfuncs = 12, \ - .ctl_reg = 0x1000 + 0x10 * id, \ - .io_reg = 0x1004 + 0x10 * id, \ - .intr_cfg_reg = 0x1008 + 0x10 * id, \ - .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x400 + 0x4 * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_ack_high = 1, \ - .intr_target_bit = 0, \ - .intr_raw_status_bit = 3, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 1, \ - } - -#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -enum msm8960_functions { - MSM_MUX_audio_pcm, - MSM_MUX_bt, - MSM_MUX_cam_mclk0, - MSM_MUX_cam_mclk1, - MSM_MUX_cam_mclk2, - MSM_MUX_codec_mic_i2s, - MSM_MUX_codec_spkr_i2s, - MSM_MUX_ext_gps, - MSM_MUX_fm, - MSM_MUX_gps_blanking, - MSM_MUX_gps_pps_in, - MSM_MUX_gps_pps_out, - MSM_MUX_gp_clk_0a, - MSM_MUX_gp_clk_0b, - MSM_MUX_gp_clk_1a, - MSM_MUX_gp_clk_1b, - MSM_MUX_gp_clk_2a, - MSM_MUX_gp_clk_2b, - MSM_MUX_gp_mn, - MSM_MUX_gp_pdm_0a, - MSM_MUX_gp_pdm_0b, - MSM_MUX_gp_pdm_1a, - MSM_MUX_gp_pdm_1b, - MSM_MUX_gp_pdm_2a, - MSM_MUX_gp_pdm_2b, - MSM_MUX_gsbi1, - MSM_MUX_gsbi1_spi_cs1_n, - MSM_MUX_gsbi1_spi_cs2a_n, - MSM_MUX_gsbi1_spi_cs2b_n, - MSM_MUX_gsbi1_spi_cs3_n, - MSM_MUX_gsbi2, - MSM_MUX_gsbi2_spi_cs1_n, - MSM_MUX_gsbi2_spi_cs2_n, - MSM_MUX_gsbi2_spi_cs3_n, - MSM_MUX_gsbi3, - MSM_MUX_gsbi4, - MSM_MUX_gsbi4_3d_cam_i2c_l, - MSM_MUX_gsbi4_3d_cam_i2c_r, - MSM_MUX_gsbi5, - MSM_MUX_gsbi5_3d_cam_i2c_l, - MSM_MUX_gsbi5_3d_cam_i2c_r, - MSM_MUX_gsbi6, - MSM_MUX_gsbi7, - MSM_MUX_gsbi8, - MSM_MUX_gsbi9, - MSM_MUX_gsbi10, - MSM_MUX_gsbi11, - MSM_MUX_gsbi11_spi_cs1a_n, - MSM_MUX_gsbi11_spi_cs1b_n, - MSM_MUX_gsbi11_spi_cs2a_n, - MSM_MUX_gsbi11_spi_cs2b_n, - MSM_MUX_gsbi11_spi_cs3_n, - MSM_MUX_gsbi12, - MSM_MUX_hdmi_cec, - MSM_MUX_hdmi_ddc_clock, - MSM_MUX_hdmi_ddc_data, - MSM_MUX_hdmi_hot_plug_detect, - MSM_MUX_hsic, - MSM_MUX_mdp_vsync, - MSM_MUX_mi2s, - MSM_MUX_mic_i2s, - MSM_MUX_pmb_clk, - MSM_MUX_pmb_ext_ctrl, - MSM_MUX_ps_hold, - MSM_MUX_rpm_wdog, - MSM_MUX_sdc2, - MSM_MUX_sdc4, - MSM_MUX_sdc5, - MSM_MUX_slimbus1, - MSM_MUX_slimbus2, - MSM_MUX_spkr_i2s, - MSM_MUX_ssbi1, - MSM_MUX_ssbi2, - MSM_MUX_ssbi_ext_gps, - MSM_MUX_ssbi_pmic2, - MSM_MUX_ssbi_qpa1, - MSM_MUX_ssbi_ts, - MSM_MUX_tsif1, - MSM_MUX_tsif2, - MSM_MUX_ts_eoc, - MSM_MUX_usb_fs1, - MSM_MUX_usb_fs1_oe, - MSM_MUX_usb_fs1_oe_n, - MSM_MUX_usb_fs2, - MSM_MUX_usb_fs2_oe, - MSM_MUX_usb_fs2_oe_n, - MSM_MUX_vfe_camif_timer1_a, - MSM_MUX_vfe_camif_timer1_b, - MSM_MUX_vfe_camif_timer2, - MSM_MUX_vfe_camif_timer3_a, - MSM_MUX_vfe_camif_timer3_b, - MSM_MUX_vfe_camif_timer4_a, - MSM_MUX_vfe_camif_timer4_b, - MSM_MUX_vfe_camif_timer4_c, - MSM_MUX_vfe_camif_timer5_a, - MSM_MUX_vfe_camif_timer5_b, - MSM_MUX_vfe_camif_timer6_a, - MSM_MUX_vfe_camif_timer6_b, - MSM_MUX_vfe_camif_timer6_c, - MSM_MUX_vfe_camif_timer7_a, - MSM_MUX_vfe_camif_timer7_b, - MSM_MUX_vfe_camif_timer7_c, - MSM_MUX_wlan, - MSM_MUX_NA, -}; - -static const char * const audio_pcm_groups[] = { - "gpio63", "gpio64", "gpio65", "gpio66" -}; - -static const char * const bt_groups[] = { - "gpio28", "gpio29", "gpio83" -}; - -static const char * const cam_mclk0_groups[] = { - "gpio5" -}; - -static const char * const cam_mclk1_groups[] = { - "gpio4" -}; - -static const char * const cam_mclk2_groups[] = { - "gpio2" -}; - -static const char * const codec_mic_i2s_groups[] = { - "gpio54", "gpio55", "gpio56", "gpio57", "gpio58" -}; - -static const char * const codec_spkr_i2s_groups[] = { - "gpio59", "gpio60", "gpio61", "gpio62" -}; - -static const char * const ext_gps_groups[] = { - "gpio22", "gpio23", "gpio24", "gpio25" -}; - -static const char * const fm_groups[] = { - "gpio26", "gpio27" -}; - -static const char * const gps_blanking_groups[] = { - "gpio137" -}; - -static const char * const gps_pps_in_groups[] = { - "gpio37" -}; - -static const char * const gps_pps_out_groups[] = { - "gpio37" -}; - -static const char * const gp_clk_0a_groups[] = { - "gpio3" -}; - -static const char * const gp_clk_0b_groups[] = { - "gpio54" -}; - -static const char * const gp_clk_1a_groups[] = { - "gpio4" -}; - -static const char * const gp_clk_1b_groups[] = { - "gpio70" -}; - -static const char * const gp_clk_2a_groups[] = { - "gpio52" -}; - -static const char * const gp_clk_2b_groups[] = { - "gpio37" -}; - -static const char * const gp_mn_groups[] = { - "gpio2" -}; - -static const char * const gp_pdm_0a_groups[] = { - "gpio58" -}; - -static const char * const gp_pdm_0b_groups[] = { - "gpio39" -}; - -static const char * const gp_pdm_1a_groups[] = { - "gpio94" -}; - -static const char * const gp_pdm_1b_groups[] = { - "gpio64" -}; - -static const char * const gp_pdm_2a_groups[] = { - "gpio69" -}; - -static const char * const gp_pdm_2b_groups[] = { - "gpio53" -}; - -static const char * const gsbi1_groups[] = { - "gpio6", "gpio7", "gpio8", "gpio9" -}; - -static const char * const gsbi1_spi_cs1_n_groups[] = { - "gpio14" -}; - -static const char * const gsbi1_spi_cs2a_n_groups[] = { - "gpio15" -}; - -static const char * const gsbi1_spi_cs2b_n_groups[] = { - "gpio17" -}; - -static const char * const gsbi1_spi_cs3_n_groups[] = { - "gpio16" -}; - -static const char * const gsbi2_groups[] = { - "gpio10", "gpio11", "gpio12", "gpio13" -}; - -static const char * const gsbi2_spi_cs1_n_groups[] = { - "gpio52" -}; - -static const char * const gsbi2_spi_cs2_n_groups[] = { - "gpio68" -}; - -static const char * const gsbi2_spi_cs3_n_groups[] = { - "gpio56" -}; - -static const char * const gsbi3_groups[] = { - "gpio14", "gpio15", "gpio16", "gpio17" -}; - -static const char * const gsbi4_groups[] = { - "gpio18", "gpio19", "gpio20", "gpio21" -}; - -static const char * const gsbi4_3d_cam_i2c_l_groups[] = { - "gpio18", "gpio19" -}; - -static const char * const gsbi4_3d_cam_i2c_r_groups[] = { - "gpio20", "gpio21" -}; - -static const char * const gsbi5_groups[] = { - "gpio22", "gpio23", "gpio24", "gpio25" -}; - -static const char * const gsbi5_3d_cam_i2c_l_groups[] = { - "gpio22", "gpio23" -}; - -static const char * const gsbi5_3d_cam_i2c_r_groups[] = { - "gpio24", "gpio25" -}; - -static const char * const gsbi6_groups[] = { - "gpio26", "gpio27", "gpio28", "gpio29" -}; - -static const char * const gsbi7_groups[] = { - "gpio30", "gpio31", "gpio32", "gpio33" -}; - -static const char * const gsbi8_groups[] = { - "gpio34", "gpio35", "gpio36", "gpio37" -}; - -static const char * const gsbi9_groups[] = { - "gpio93", "gpio94", "gpio95", "gpio96" -}; - -static const char * const gsbi10_groups[] = { - "gpio71", "gpio72", "gpio73", "gpio74" -}; - -static const char * const gsbi11_groups[] = { - "gpio38", "gpio39", "gpio40", "gpio41" -}; - -static const char * const gsbi11_spi_cs1a_n_groups[] = { - "gpio36" -}; - -static const char * const gsbi11_spi_cs1b_n_groups[] = { - "gpio18" -}; - -static const char * const gsbi11_spi_cs2a_n_groups[] = { - "gpio37" -}; - -static const char * const gsbi11_spi_cs2b_n_groups[] = { - "gpio19" -}; - -static const char * const gsbi11_spi_cs3_n_groups[] = { - "gpio76" -}; - -static const char * const gsbi12_groups[] = { - "gpio42", "gpio43", "gpio44", "gpio45" -}; - -static const char * const hdmi_cec_groups[] = { - "gpio99" -}; - -static const char * const hdmi_ddc_clock_groups[] = { - "gpio100" -}; - -static const char * const hdmi_ddc_data_groups[] = { - "gpio101" -}; - -static const char * const hdmi_hot_plug_detect_groups[] = { - "gpio102" -}; - -static const char * const hsic_groups[] = { - "gpio150", "gpio151" -}; - -static const char * const mdp_vsync_groups[] = { - "gpio0", "gpio1", "gpio19" -}; - -static const char * const mi2s_groups[] = { - "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53" -}; - -static const char * const mic_i2s_groups[] = { - "gpio71", "gpio72", "gpio73", "gpio74" -}; - -static const char * const pmb_clk_groups[] = { - "gpio21", "gpio86", "gpio112" -}; - -static const char * const pmb_ext_ctrl_groups[] = { - "gpio4", "gpio5" -}; - -static const char * const ps_hold_groups[] = { - "gpio108" -}; - -static const char * const rpm_wdog_groups[] = { - "gpio12" -}; - -static const char * const sdc2_groups[] = { - "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", - "gpio96", "gpio97", "gpio98" -}; - -static const char * const sdc4_groups[] = { - "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" -}; - -static const char * const sdc5_groups[] = { - "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" -}; - -static const char * const slimbus1_groups[] = { - "gpio50", "gpio51", "gpio60", "gpio61" -}; - -static const char * const slimbus2_groups[] = { - "gpio42", "gpio43" -}; - -static const char * const spkr_i2s_groups[] = { - "gpio67", "gpio68", "gpio69", "gpio70" -}; - -static const char * const ssbi1_groups[] = { - "gpio141", "gpio143" -}; - -static const char * const ssbi2_groups[] = { - "gpio140", "gpio142" -}; - -static const char * const ssbi_ext_gps_groups[] = { - "gpio23" -}; - -static const char * const ssbi_pmic2_groups[] = { - "gpio149" -}; - -static const char * const ssbi_qpa1_groups[] = { - "gpio131" -}; - -static const char * const ssbi_ts_groups[] = { - "gpio10" -}; - -static const char * const tsif1_groups[] = { - "gpio75", "gpio76", "gpio77", "gpio82" -}; - -static const char * const tsif2_groups[] = { - "gpio78", "gpio79", "gpio80", "gpio81" -}; - -static const char * const ts_eoc_groups[] = { - "gpio11" -}; - -static const char * const usb_fs1_groups[] = { - "gpio32", "gpio33" -}; - -static const char * const usb_fs1_oe_groups[] = { - "gpio31" -}; - -static const char * const usb_fs1_oe_n_groups[] = { - "gpio31" -}; - -static const char * const usb_fs2_groups[] = { - "gpio34", "gpio35" -}; - -static const char * const usb_fs2_oe_groups[] = { - "gpio36" -}; - -static const char * const usb_fs2_oe_n_groups[] = { - "gpio36" -}; - -static const char * const vfe_camif_timer1_a_groups[] = { - "gpio2" -}; - -static const char * const vfe_camif_timer1_b_groups[] = { - "gpio38" -}; - -static const char * const vfe_camif_timer2_groups[] = { - "gpio3" -}; - -static const char * const vfe_camif_timer3_a_groups[] = { - "gpio4" -}; - -static const char * const vfe_camif_timer3_b_groups[] = { - "gpio151" -}; - -static const char * const vfe_camif_timer4_a_groups[] = { - "gpio65" -}; - -static const char * const vfe_camif_timer4_b_groups[] = { - "gpio150" -}; - -static const char * const vfe_camif_timer4_c_groups[] = { - "gpio10" -}; - -static const char * const vfe_camif_timer5_a_groups[] = { - "gpio66" -}; - -static const char * const vfe_camif_timer5_b_groups[] = { - "gpio39" -}; - -static const char * const vfe_camif_timer6_a_groups[] = { - "gpio71" -}; - -static const char * const vfe_camif_timer6_b_groups[] = { - "gpio0" -}; - -static const char * const vfe_camif_timer6_c_groups[] = { - "gpio18" -}; - -static const char * const vfe_camif_timer7_a_groups[] = { - "gpio67" -}; - -static const char * const vfe_camif_timer7_b_groups[] = { - "gpio1" -}; - -static const char * const vfe_camif_timer7_c_groups[] = { - "gpio19" -}; - -static const char * const wlan_groups[] = { - "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" -}; - -static const struct msm_function msm8960_functions[] = { - FUNCTION(audio_pcm), - FUNCTION(bt), - FUNCTION(cam_mclk0), - FUNCTION(cam_mclk1), - FUNCTION(cam_mclk2), - FUNCTION(codec_mic_i2s), - FUNCTION(codec_spkr_i2s), - FUNCTION(ext_gps), - FUNCTION(fm), - FUNCTION(gps_blanking), - FUNCTION(gps_pps_in), - FUNCTION(gps_pps_out), - FUNCTION(gp_clk_0a), - FUNCTION(gp_clk_0b), - FUNCTION(gp_clk_1a), - FUNCTION(gp_clk_1b), - FUNCTION(gp_clk_2a), - FUNCTION(gp_clk_2b), - FUNCTION(gp_mn), - FUNCTION(gp_pdm_0a), - FUNCTION(gp_pdm_0b), - FUNCTION(gp_pdm_1a), - FUNCTION(gp_pdm_1b), - FUNCTION(gp_pdm_2a), - FUNCTION(gp_pdm_2b), - FUNCTION(gsbi1), - FUNCTION(gsbi1_spi_cs1_n), - FUNCTION(gsbi1_spi_cs2a_n), - FUNCTION(gsbi1_spi_cs2b_n), - FUNCTION(gsbi1_spi_cs3_n), - FUNCTION(gsbi2), - FUNCTION(gsbi2_spi_cs1_n), - FUNCTION(gsbi2_spi_cs2_n), - FUNCTION(gsbi2_spi_cs3_n), - FUNCTION(gsbi3), - FUNCTION(gsbi4), - FUNCTION(gsbi4_3d_cam_i2c_l), - FUNCTION(gsbi4_3d_cam_i2c_r), - FUNCTION(gsbi5), - FUNCTION(gsbi5_3d_cam_i2c_l), - FUNCTION(gsbi5_3d_cam_i2c_r), - FUNCTION(gsbi6), - FUNCTION(gsbi7), - FUNCTION(gsbi8), - FUNCTION(gsbi9), - FUNCTION(gsbi10), - FUNCTION(gsbi11), - FUNCTION(gsbi11_spi_cs1a_n), - FUNCTION(gsbi11_spi_cs1b_n), - FUNCTION(gsbi11_spi_cs2a_n), - FUNCTION(gsbi11_spi_cs2b_n), - FUNCTION(gsbi11_spi_cs3_n), - FUNCTION(gsbi12), - FUNCTION(hdmi_cec), - FUNCTION(hdmi_ddc_clock), - FUNCTION(hdmi_ddc_data), - FUNCTION(hdmi_hot_plug_detect), - FUNCTION(hsic), - FUNCTION(mdp_vsync), - FUNCTION(mi2s), - FUNCTION(mic_i2s), - FUNCTION(pmb_clk), - FUNCTION(pmb_ext_ctrl), - FUNCTION(ps_hold), - FUNCTION(rpm_wdog), - FUNCTION(sdc2), - FUNCTION(sdc4), - FUNCTION(sdc5), - FUNCTION(slimbus1), - FUNCTION(slimbus2), - FUNCTION(spkr_i2s), - FUNCTION(ssbi1), - FUNCTION(ssbi2), - FUNCTION(ssbi_ext_gps), - FUNCTION(ssbi_pmic2), - FUNCTION(ssbi_qpa1), - FUNCTION(ssbi_ts), - FUNCTION(tsif1), - FUNCTION(tsif2), - FUNCTION(ts_eoc), - FUNCTION(usb_fs1), - FUNCTION(usb_fs1_oe), - FUNCTION(usb_fs1_oe_n), - FUNCTION(usb_fs2), - FUNCTION(usb_fs2_oe), - FUNCTION(usb_fs2_oe_n), - FUNCTION(vfe_camif_timer1_a), - FUNCTION(vfe_camif_timer1_b), - FUNCTION(vfe_camif_timer2), - FUNCTION(vfe_camif_timer3_a), - FUNCTION(vfe_camif_timer3_b), - FUNCTION(vfe_camif_timer4_a), - FUNCTION(vfe_camif_timer4_b), - FUNCTION(vfe_camif_timer4_c), - FUNCTION(vfe_camif_timer5_a), - FUNCTION(vfe_camif_timer5_b), - FUNCTION(vfe_camif_timer6_a), - FUNCTION(vfe_camif_timer6_b), - FUNCTION(vfe_camif_timer6_c), - FUNCTION(vfe_camif_timer7_a), - FUNCTION(vfe_camif_timer7_b), - FUNCTION(vfe_camif_timer7_c), - FUNCTION(wlan), -}; - -static const struct msm_pingroup msm8960_groups[] = { - PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA), - PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA), - PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), - PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), - PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), - PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), - PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA), - PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA), - PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b), - PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA), - - SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), - SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), - SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), - - SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), - SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), - SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), -}; - -#define NUM_GPIO_PINGROUPS 152 - -static const struct msm_pinctrl_soc_data msm8960_pinctrl = { - .pins = msm8960_pins, - .npins = ARRAY_SIZE(msm8960_pins), - .functions = msm8960_functions, - .nfunctions = ARRAY_SIZE(msm8960_functions), - .groups = msm8960_groups, - .ngroups = ARRAY_SIZE(msm8960_groups), - .ngpios = NUM_GPIO_PINGROUPS, -}; - -static int msm8960_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &msm8960_pinctrl); -} - -static const struct of_device_id msm8960_pinctrl_of_match[] = { - { .compatible = "qcom,msm8960-pinctrl", }, - { }, -}; - -static struct platform_driver msm8960_pinctrl_driver = { - .driver = { - .name = "msm8960-pinctrl", - .owner = THIS_MODULE, - .of_match_table = msm8960_pinctrl_of_match, - }, - .probe = msm8960_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init msm8960_pinctrl_init(void) -{ - return platform_driver_register(&msm8960_pinctrl_driver); -} -arch_initcall(msm8960_pinctrl_init); - -static void __exit msm8960_pinctrl_exit(void) -{ - platform_driver_unregister(&msm8960_pinctrl_driver); -} -module_exit(msm8960_pinctrl_exit); - -MODULE_AUTHOR("Bjorn Andersson "); -MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c deleted file mode 100644 index 418306911a6f..000000000000 --- a/drivers/pinctrl/pinctrl-msm8x74.c +++ /dev/null @@ -1,1040 +0,0 @@ -/* - * Copyright (c) 2013, Sony Mobile Communications AB. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -static const struct pinctrl_pin_desc msm8x74_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - PINCTRL_PIN(69, "GPIO_69"), - PINCTRL_PIN(70, "GPIO_70"), - PINCTRL_PIN(71, "GPIO_71"), - PINCTRL_PIN(72, "GPIO_72"), - PINCTRL_PIN(73, "GPIO_73"), - PINCTRL_PIN(74, "GPIO_74"), - PINCTRL_PIN(75, "GPIO_75"), - PINCTRL_PIN(76, "GPIO_76"), - PINCTRL_PIN(77, "GPIO_77"), - PINCTRL_PIN(78, "GPIO_78"), - PINCTRL_PIN(79, "GPIO_79"), - PINCTRL_PIN(80, "GPIO_80"), - PINCTRL_PIN(81, "GPIO_81"), - PINCTRL_PIN(82, "GPIO_82"), - PINCTRL_PIN(83, "GPIO_83"), - PINCTRL_PIN(84, "GPIO_84"), - PINCTRL_PIN(85, "GPIO_85"), - PINCTRL_PIN(86, "GPIO_86"), - PINCTRL_PIN(87, "GPIO_87"), - PINCTRL_PIN(88, "GPIO_88"), - PINCTRL_PIN(89, "GPIO_89"), - PINCTRL_PIN(90, "GPIO_90"), - PINCTRL_PIN(91, "GPIO_91"), - PINCTRL_PIN(92, "GPIO_92"), - PINCTRL_PIN(93, "GPIO_93"), - PINCTRL_PIN(94, "GPIO_94"), - PINCTRL_PIN(95, "GPIO_95"), - PINCTRL_PIN(96, "GPIO_96"), - PINCTRL_PIN(97, "GPIO_97"), - PINCTRL_PIN(98, "GPIO_98"), - PINCTRL_PIN(99, "GPIO_99"), - PINCTRL_PIN(100, "GPIO_100"), - PINCTRL_PIN(101, "GPIO_101"), - PINCTRL_PIN(102, "GPIO_102"), - PINCTRL_PIN(103, "GPIO_103"), - PINCTRL_PIN(104, "GPIO_104"), - PINCTRL_PIN(105, "GPIO_105"), - PINCTRL_PIN(106, "GPIO_106"), - PINCTRL_PIN(107, "GPIO_107"), - PINCTRL_PIN(108, "GPIO_108"), - PINCTRL_PIN(109, "GPIO_109"), - PINCTRL_PIN(110, "GPIO_110"), - PINCTRL_PIN(111, "GPIO_111"), - PINCTRL_PIN(112, "GPIO_112"), - PINCTRL_PIN(113, "GPIO_113"), - PINCTRL_PIN(114, "GPIO_114"), - PINCTRL_PIN(115, "GPIO_115"), - PINCTRL_PIN(116, "GPIO_116"), - PINCTRL_PIN(117, "GPIO_117"), - PINCTRL_PIN(118, "GPIO_118"), - PINCTRL_PIN(119, "GPIO_119"), - PINCTRL_PIN(120, "GPIO_120"), - PINCTRL_PIN(121, "GPIO_121"), - PINCTRL_PIN(122, "GPIO_122"), - PINCTRL_PIN(123, "GPIO_123"), - PINCTRL_PIN(124, "GPIO_124"), - PINCTRL_PIN(125, "GPIO_125"), - PINCTRL_PIN(126, "GPIO_126"), - PINCTRL_PIN(127, "GPIO_127"), - PINCTRL_PIN(128, "GPIO_128"), - PINCTRL_PIN(129, "GPIO_129"), - PINCTRL_PIN(130, "GPIO_130"), - PINCTRL_PIN(131, "GPIO_131"), - PINCTRL_PIN(132, "GPIO_132"), - PINCTRL_PIN(133, "GPIO_133"), - PINCTRL_PIN(134, "GPIO_134"), - PINCTRL_PIN(135, "GPIO_135"), - PINCTRL_PIN(136, "GPIO_136"), - PINCTRL_PIN(137, "GPIO_137"), - PINCTRL_PIN(138, "GPIO_138"), - PINCTRL_PIN(139, "GPIO_139"), - PINCTRL_PIN(140, "GPIO_140"), - PINCTRL_PIN(141, "GPIO_141"), - PINCTRL_PIN(142, "GPIO_142"), - PINCTRL_PIN(143, "GPIO_143"), - PINCTRL_PIN(144, "GPIO_144"), - PINCTRL_PIN(145, "GPIO_145"), - - PINCTRL_PIN(146, "SDC1_CLK"), - PINCTRL_PIN(147, "SDC1_CMD"), - PINCTRL_PIN(148, "SDC1_DATA"), - PINCTRL_PIN(149, "SDC2_CLK"), - PINCTRL_PIN(150, "SDC2_CMD"), - PINCTRL_PIN(151, "SDC2_DATA"), -}; - -#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_MSM_GPIO_PINS(0); -DECLARE_MSM_GPIO_PINS(1); -DECLARE_MSM_GPIO_PINS(2); -DECLARE_MSM_GPIO_PINS(3); -DECLARE_MSM_GPIO_PINS(4); -DECLARE_MSM_GPIO_PINS(5); -DECLARE_MSM_GPIO_PINS(6); -DECLARE_MSM_GPIO_PINS(7); -DECLARE_MSM_GPIO_PINS(8); -DECLARE_MSM_GPIO_PINS(9); -DECLARE_MSM_GPIO_PINS(10); -DECLARE_MSM_GPIO_PINS(11); -DECLARE_MSM_GPIO_PINS(12); -DECLARE_MSM_GPIO_PINS(13); -DECLARE_MSM_GPIO_PINS(14); -DECLARE_MSM_GPIO_PINS(15); -DECLARE_MSM_GPIO_PINS(16); -DECLARE_MSM_GPIO_PINS(17); -DECLARE_MSM_GPIO_PINS(18); -DECLARE_MSM_GPIO_PINS(19); -DECLARE_MSM_GPIO_PINS(20); -DECLARE_MSM_GPIO_PINS(21); -DECLARE_MSM_GPIO_PINS(22); -DECLARE_MSM_GPIO_PINS(23); -DECLARE_MSM_GPIO_PINS(24); -DECLARE_MSM_GPIO_PINS(25); -DECLARE_MSM_GPIO_PINS(26); -DECLARE_MSM_GPIO_PINS(27); -DECLARE_MSM_GPIO_PINS(28); -DECLARE_MSM_GPIO_PINS(29); -DECLARE_MSM_GPIO_PINS(30); -DECLARE_MSM_GPIO_PINS(31); -DECLARE_MSM_GPIO_PINS(32); -DECLARE_MSM_GPIO_PINS(33); -DECLARE_MSM_GPIO_PINS(34); -DECLARE_MSM_GPIO_PINS(35); -DECLARE_MSM_GPIO_PINS(36); -DECLARE_MSM_GPIO_PINS(37); -DECLARE_MSM_GPIO_PINS(38); -DECLARE_MSM_GPIO_PINS(39); -DECLARE_MSM_GPIO_PINS(40); -DECLARE_MSM_GPIO_PINS(41); -DECLARE_MSM_GPIO_PINS(42); -DECLARE_MSM_GPIO_PINS(43); -DECLARE_MSM_GPIO_PINS(44); -DECLARE_MSM_GPIO_PINS(45); -DECLARE_MSM_GPIO_PINS(46); -DECLARE_MSM_GPIO_PINS(47); -DECLARE_MSM_GPIO_PINS(48); -DECLARE_MSM_GPIO_PINS(49); -DECLARE_MSM_GPIO_PINS(50); -DECLARE_MSM_GPIO_PINS(51); -DECLARE_MSM_GPIO_PINS(52); -DECLARE_MSM_GPIO_PINS(53); -DECLARE_MSM_GPIO_PINS(54); -DECLARE_MSM_GPIO_PINS(55); -DECLARE_MSM_GPIO_PINS(56); -DECLARE_MSM_GPIO_PINS(57); -DECLARE_MSM_GPIO_PINS(58); -DECLARE_MSM_GPIO_PINS(59); -DECLARE_MSM_GPIO_PINS(60); -DECLARE_MSM_GPIO_PINS(61); -DECLARE_MSM_GPIO_PINS(62); -DECLARE_MSM_GPIO_PINS(63); -DECLARE_MSM_GPIO_PINS(64); -DECLARE_MSM_GPIO_PINS(65); -DECLARE_MSM_GPIO_PINS(66); -DECLARE_MSM_GPIO_PINS(67); -DECLARE_MSM_GPIO_PINS(68); -DECLARE_MSM_GPIO_PINS(69); -DECLARE_MSM_GPIO_PINS(70); -DECLARE_MSM_GPIO_PINS(71); -DECLARE_MSM_GPIO_PINS(72); -DECLARE_MSM_GPIO_PINS(73); -DECLARE_MSM_GPIO_PINS(74); -DECLARE_MSM_GPIO_PINS(75); -DECLARE_MSM_GPIO_PINS(76); -DECLARE_MSM_GPIO_PINS(77); -DECLARE_MSM_GPIO_PINS(78); -DECLARE_MSM_GPIO_PINS(79); -DECLARE_MSM_GPIO_PINS(80); -DECLARE_MSM_GPIO_PINS(81); -DECLARE_MSM_GPIO_PINS(82); -DECLARE_MSM_GPIO_PINS(83); -DECLARE_MSM_GPIO_PINS(84); -DECLARE_MSM_GPIO_PINS(85); -DECLARE_MSM_GPIO_PINS(86); -DECLARE_MSM_GPIO_PINS(87); -DECLARE_MSM_GPIO_PINS(88); -DECLARE_MSM_GPIO_PINS(89); -DECLARE_MSM_GPIO_PINS(90); -DECLARE_MSM_GPIO_PINS(91); -DECLARE_MSM_GPIO_PINS(92); -DECLARE_MSM_GPIO_PINS(93); -DECLARE_MSM_GPIO_PINS(94); -DECLARE_MSM_GPIO_PINS(95); -DECLARE_MSM_GPIO_PINS(96); -DECLARE_MSM_GPIO_PINS(97); -DECLARE_MSM_GPIO_PINS(98); -DECLARE_MSM_GPIO_PINS(99); -DECLARE_MSM_GPIO_PINS(100); -DECLARE_MSM_GPIO_PINS(101); -DECLARE_MSM_GPIO_PINS(102); -DECLARE_MSM_GPIO_PINS(103); -DECLARE_MSM_GPIO_PINS(104); -DECLARE_MSM_GPIO_PINS(105); -DECLARE_MSM_GPIO_PINS(106); -DECLARE_MSM_GPIO_PINS(107); -DECLARE_MSM_GPIO_PINS(108); -DECLARE_MSM_GPIO_PINS(109); -DECLARE_MSM_GPIO_PINS(110); -DECLARE_MSM_GPIO_PINS(111); -DECLARE_MSM_GPIO_PINS(112); -DECLARE_MSM_GPIO_PINS(113); -DECLARE_MSM_GPIO_PINS(114); -DECLARE_MSM_GPIO_PINS(115); -DECLARE_MSM_GPIO_PINS(116); -DECLARE_MSM_GPIO_PINS(117); -DECLARE_MSM_GPIO_PINS(118); -DECLARE_MSM_GPIO_PINS(119); -DECLARE_MSM_GPIO_PINS(120); -DECLARE_MSM_GPIO_PINS(121); -DECLARE_MSM_GPIO_PINS(122); -DECLARE_MSM_GPIO_PINS(123); -DECLARE_MSM_GPIO_PINS(124); -DECLARE_MSM_GPIO_PINS(125); -DECLARE_MSM_GPIO_PINS(126); -DECLARE_MSM_GPIO_PINS(127); -DECLARE_MSM_GPIO_PINS(128); -DECLARE_MSM_GPIO_PINS(129); -DECLARE_MSM_GPIO_PINS(130); -DECLARE_MSM_GPIO_PINS(131); -DECLARE_MSM_GPIO_PINS(132); -DECLARE_MSM_GPIO_PINS(133); -DECLARE_MSM_GPIO_PINS(134); -DECLARE_MSM_GPIO_PINS(135); -DECLARE_MSM_GPIO_PINS(136); -DECLARE_MSM_GPIO_PINS(137); -DECLARE_MSM_GPIO_PINS(138); -DECLARE_MSM_GPIO_PINS(139); -DECLARE_MSM_GPIO_PINS(140); -DECLARE_MSM_GPIO_PINS(141); -DECLARE_MSM_GPIO_PINS(142); -DECLARE_MSM_GPIO_PINS(143); -DECLARE_MSM_GPIO_PINS(144); -DECLARE_MSM_GPIO_PINS(145); - -static const unsigned int sdc1_clk_pins[] = { 146 }; -static const unsigned int sdc1_cmd_pins[] = { 147 }; -static const unsigned int sdc1_data_pins[] = { 148 }; -static const unsigned int sdc2_clk_pins[] = { 149 }; -static const unsigned int sdc2_cmd_pins[] = { 150 }; -static const unsigned int sdc2_data_pins[] = { 151 }; - -#define FUNCTION(fname) \ - [MSM_MUX_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - MSM_MUX_NA, /* gpio mode */ \ - MSM_MUX_##f1, \ - MSM_MUX_##f2, \ - MSM_MUX_##f3, \ - MSM_MUX_##f4, \ - MSM_MUX_##f5, \ - MSM_MUX_##f6, \ - MSM_MUX_##f7 \ - }, \ - .nfuncs = 8, \ - .ctl_reg = 0x1000 + 0x10 * id, \ - .io_reg = 0x1004 + 0x10 * id, \ - .intr_cfg_reg = 0x1008 + 0x10 * id, \ - .intr_status_reg = 0x100c + 0x10 * id, \ - .intr_target_reg = 0x1008 + 0x10 * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_target_bit = 5, \ - .intr_raw_status_bit = 4, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 2, \ - } - -#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } - -/* - * TODO: Add the rest of the possible functions and fill out - * the pingroup table below. - */ -enum msm8x74_functions { - MSM_MUX_cci_i2c0, - MSM_MUX_cci_i2c1, - MSM_MUX_blsp_i2c1, - MSM_MUX_blsp_i2c2, - MSM_MUX_blsp_i2c3, - MSM_MUX_blsp_i2c4, - MSM_MUX_blsp_i2c5, - MSM_MUX_blsp_i2c6, - MSM_MUX_blsp_i2c7, - MSM_MUX_blsp_i2c8, - MSM_MUX_blsp_i2c9, - MSM_MUX_blsp_i2c10, - MSM_MUX_blsp_i2c11, - MSM_MUX_blsp_i2c12, - MSM_MUX_blsp_spi1, - MSM_MUX_blsp_spi1_cs1, - MSM_MUX_blsp_spi1_cs2, - MSM_MUX_blsp_spi1_cs3, - MSM_MUX_blsp_spi2, - MSM_MUX_blsp_spi2_cs1, - MSM_MUX_blsp_spi2_cs2, - MSM_MUX_blsp_spi2_cs3, - MSM_MUX_blsp_spi3, - MSM_MUX_blsp_spi4, - MSM_MUX_blsp_spi5, - MSM_MUX_blsp_spi6, - MSM_MUX_blsp_spi7, - MSM_MUX_blsp_spi8, - MSM_MUX_blsp_spi9, - MSM_MUX_blsp_spi10, - MSM_MUX_blsp_spi10_cs1, - MSM_MUX_blsp_spi10_cs2, - MSM_MUX_blsp_spi10_cs3, - MSM_MUX_blsp_spi11, - MSM_MUX_blsp_spi12, - MSM_MUX_blsp_uart1, - MSM_MUX_blsp_uart2, - MSM_MUX_blsp_uart3, - MSM_MUX_blsp_uart4, - MSM_MUX_blsp_uart5, - MSM_MUX_blsp_uart6, - MSM_MUX_blsp_uart7, - MSM_MUX_blsp_uart8, - MSM_MUX_blsp_uart9, - MSM_MUX_blsp_uart10, - MSM_MUX_blsp_uart11, - MSM_MUX_blsp_uart12, - MSM_MUX_blsp_uim1, - MSM_MUX_blsp_uim2, - MSM_MUX_blsp_uim3, - MSM_MUX_blsp_uim4, - MSM_MUX_blsp_uim5, - MSM_MUX_blsp_uim6, - MSM_MUX_blsp_uim7, - MSM_MUX_blsp_uim8, - MSM_MUX_blsp_uim9, - MSM_MUX_blsp_uim10, - MSM_MUX_blsp_uim11, - MSM_MUX_blsp_uim12, - MSM_MUX_uim1, - MSM_MUX_uim2, - MSM_MUX_uim_batt_alarm, - MSM_MUX_sdc3, - MSM_MUX_sdc4, - MSM_MUX_gcc_gp_clk1, - MSM_MUX_gcc_gp_clk2, - MSM_MUX_gcc_gp_clk3, - MSM_MUX_qua_mi2s, - MSM_MUX_pri_mi2s, - MSM_MUX_spkr_mi2s, - MSM_MUX_ter_mi2s, - MSM_MUX_sec_mi2s, - MSM_MUX_hdmi_cec, - MSM_MUX_hdmi_ddc, - MSM_MUX_hdmi_hpd, - MSM_MUX_edp_hpd, - MSM_MUX_mdp_vsync, - MSM_MUX_cam_mclk0, - MSM_MUX_cam_mclk1, - MSM_MUX_cam_mclk2, - MSM_MUX_cam_mclk3, - MSM_MUX_cci_timer0, - MSM_MUX_cci_timer1, - MSM_MUX_cci_timer2, - MSM_MUX_cci_timer3, - MSM_MUX_cci_timer4, - MSM_MUX_cci_async_in0, - MSM_MUX_cci_async_in1, - MSM_MUX_cci_async_in2, - MSM_MUX_gp_pdm0, - MSM_MUX_gp_pdm1, - MSM_MUX_gp_pdm2, - MSM_MUX_gp0_clk, - MSM_MUX_gp1_clk, - MSM_MUX_gp_mn, - MSM_MUX_tsif1, - MSM_MUX_tsif2, - MSM_MUX_hsic, - MSM_MUX_grfc, - MSM_MUX_audio_ref_clk, - MSM_MUX_bt, - MSM_MUX_fm, - MSM_MUX_wlan, - MSM_MUX_slimbus, - MSM_MUX_NA, -}; - -static const char * const blsp_uart1_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3" -}; -static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; -static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; -static const char * const blsp_spi1_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3" -}; -static const char * const blsp_spi1_cs1_groups[] = { "gpio8" }; -static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" }; -static const char * const blsp_spi1_cs3_groups[] = { "gpio10" }; - -static const char * const blsp_uart2_groups[] = { - "gpio4", "gpio5", "gpio6", "gpio7" -}; -static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; -static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; -static const char * const blsp_spi2_groups[] = { - "gpio4", "gpio5", "gpio6", "gpio7" -}; -static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" }; -static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" }; -static const char * const blsp_spi2_cs3_groups[] = { "gpio66" }; - -static const char * const blsp_uart3_groups[] = { - "gpio8", "gpio9", "gpio10", "gpio11" -}; -static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; -static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; -static const char * const blsp_spi3_groups[] = { - "gpio8", "gpio9", "gpio10", "gpio11" -}; - -static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" }; -static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" }; - -static const char * const blsp_uart4_groups[] = { - "gpio19", "gpio20", "gpio21", "gpio22" -}; -static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" }; -static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" }; -static const char * const blsp_spi4_groups[] = { - "gpio19", "gpio20", "gpio21", "gpio22" -}; - -static const char * const blsp_uart5_groups[] = { - "gpio23", "gpio24", "gpio25", "gpio26" -}; -static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" }; -static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" }; -static const char * const blsp_spi5_groups[] = { - "gpio23", "gpio24", "gpio25", "gpio26" -}; - -static const char * const blsp_uart6_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30" -}; -static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" }; -static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; -static const char * const blsp_spi6_groups[] = { - "gpio27", "gpio28", "gpio29", "gpio30" -}; - -static const char * const blsp_uart7_groups[] = { - "gpio41", "gpio42", "gpio43", "gpio44" -}; -static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" }; -static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" }; -static const char * const blsp_spi7_groups[] = { - "gpio41", "gpio42", "gpio43", "gpio44" -}; - -static const char * const blsp_uart8_groups[] = { - "gpio45", "gpio46", "gpio47", "gpio48" -}; -static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" }; -static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" }; -static const char * const blsp_spi8_groups[] = { - "gpio45", "gpio46", "gpio47", "gpio48" -}; - -static const char * const blsp_uart9_groups[] = { - "gpio49", "gpio50", "gpio51", "gpio52" -}; -static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" }; -static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" }; -static const char * const blsp_spi9_groups[] = { - "gpio49", "gpio50", "gpio51", "gpio52" -}; - -static const char * const blsp_uart10_groups[] = { - "gpio53", "gpio54", "gpio55", "gpio56" -}; -static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" }; -static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" }; -static const char * const blsp_spi10_groups[] = { - "gpio53", "gpio54", "gpio55", "gpio56" -}; -static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" }; -static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" }; -static const char * const blsp_spi10_cs3_groups[] = { "gpio90" }; - -static const char * const blsp_uart11_groups[] = { - "gpio81", "gpio82", "gpio83", "gpio84" -}; -static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" }; -static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; -static const char * const blsp_spi11_groups[] = { - "gpio81", "gpio82", "gpio83", "gpio84" -}; - -static const char * const blsp_uart12_groups[] = { - "gpio85", "gpio86", "gpio87", "gpio88" -}; -static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" }; -static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" }; -static const char * const blsp_spi12_groups[] = { - "gpio85", "gpio86", "gpio87", "gpio88" -}; - -static const char * const uim1_groups[] = { - "gpio97", "gpio98", "gpio99", "gpio100" -}; - -static const char * const uim2_groups[] = { - "gpio49", "gpio50", "gpio51", "gpio52" -}; - -static const char * const uim_batt_alarm_groups[] = { "gpio101" }; - -static const char * const sdc3_groups[] = { - "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" -}; - -static const char * const sdc4_groups[] = { - "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" -}; - -static const char * const gp0_clk_groups[] = { "gpio26" }; -static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" }; -static const char * const gp_mn_groups[] = { "gpio29" }; -static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" }; -static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" }; -static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" }; - -static const char * const qua_mi2s_groups[] = { - "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", -}; - -static const char * const pri_mi2s_groups[] = { - "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" -}; - -static const char * const spkr_mi2s_groups[] = { - "gpio69", "gpio70", "gpio71", "gpio72" -}; - -static const char * const ter_mi2s_groups[] = { - "gpio73", "gpio74", "gpio75", "gpio76", "gpio77" -}; - -static const char * const sec_mi2s_groups[] = { - "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" -}; - -static const char * const hdmi_cec_groups[] = { "gpio31" }; -static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" }; -static const char * const hdmi_hpd_groups[] = { "gpio34" }; -static const char * const edp_hpd_groups[] = { "gpio102" }; - -static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" }; -static const char * const cam_mclk0_groups[] = { "gpio15" }; -static const char * const cam_mclk1_groups[] = { "gpio16" }; -static const char * const cam_mclk2_groups[] = { "gpio17" }; -static const char * const cam_mclk3_groups[] = { "gpio18" }; - -static const char * const cci_timer0_groups[] = { "gpio23" }; -static const char * const cci_timer1_groups[] = { "gpio24" }; -static const char * const cci_timer2_groups[] = { "gpio25" }; -static const char * const cci_timer3_groups[] = { "gpio26" }; -static const char * const cci_timer4_groups[] = { "gpio27" }; -static const char * const cci_async_in0_groups[] = { "gpio28" }; -static const char * const cci_async_in1_groups[] = { "gpio26" }; -static const char * const cci_async_in2_groups[] = { "gpio27" }; - -static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" }; -static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" }; -static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" }; - -static const char * const tsif1_groups[] = { - "gpio89", "gpio90", "gpio91", "gpio92" -}; - -static const char * const tsif2_groups[] = { - "gpio93", "gpio94", "gpio95", "gpio96" -}; - -static const char * const hsic_groups[] = { "gpio144", "gpio145" }; -static const char * const grfc_groups[] = { - "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", - "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", - "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", - "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", - "gpio128", "gpio136", "gpio137", "gpio141", "gpio143" -}; - -static const char * const audio_ref_clk_groups[] = { "gpio69" }; - -static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" }; - -static const char * const fm_groups[] = { "gpio41", "gpio42" }; - -static const char * const wlan_groups[] = { - "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" -}; - -static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; - -static const struct msm_function msm8x74_functions[] = { - FUNCTION(cci_i2c0), - FUNCTION(cci_i2c1), - FUNCTION(uim1), - FUNCTION(uim2), - FUNCTION(uim_batt_alarm), - FUNCTION(blsp_uim1), - FUNCTION(blsp_uim2), - FUNCTION(blsp_uim3), - FUNCTION(blsp_uim4), - FUNCTION(blsp_uim5), - FUNCTION(blsp_uim6), - FUNCTION(blsp_uim7), - FUNCTION(blsp_uim8), - FUNCTION(blsp_uim9), - FUNCTION(blsp_uim10), - FUNCTION(blsp_uim11), - FUNCTION(blsp_uim12), - FUNCTION(blsp_i2c1), - FUNCTION(blsp_i2c2), - FUNCTION(blsp_i2c3), - FUNCTION(blsp_i2c4), - FUNCTION(blsp_i2c5), - FUNCTION(blsp_i2c6), - FUNCTION(blsp_i2c7), - FUNCTION(blsp_i2c8), - FUNCTION(blsp_i2c9), - FUNCTION(blsp_i2c10), - FUNCTION(blsp_i2c11), - FUNCTION(blsp_i2c12), - FUNCTION(blsp_spi1), - FUNCTION(blsp_spi1_cs1), - FUNCTION(blsp_spi1_cs2), - FUNCTION(blsp_spi1_cs3), - FUNCTION(blsp_spi2), - FUNCTION(blsp_spi2_cs1), - FUNCTION(blsp_spi2_cs2), - FUNCTION(blsp_spi2_cs3), - FUNCTION(blsp_spi3), - FUNCTION(blsp_spi4), - FUNCTION(blsp_spi5), - FUNCTION(blsp_spi6), - FUNCTION(blsp_spi7), - FUNCTION(blsp_spi8), - FUNCTION(blsp_spi9), - FUNCTION(blsp_spi10), - FUNCTION(blsp_spi10_cs1), - FUNCTION(blsp_spi10_cs2), - FUNCTION(blsp_spi10_cs3), - FUNCTION(blsp_spi11), - FUNCTION(blsp_spi12), - FUNCTION(blsp_uart1), - FUNCTION(blsp_uart2), - FUNCTION(blsp_uart3), - FUNCTION(blsp_uart4), - FUNCTION(blsp_uart5), - FUNCTION(blsp_uart6), - FUNCTION(blsp_uart7), - FUNCTION(blsp_uart8), - FUNCTION(blsp_uart9), - FUNCTION(blsp_uart10), - FUNCTION(blsp_uart11), - FUNCTION(blsp_uart12), - FUNCTION(sdc3), - FUNCTION(sdc4), - FUNCTION(gcc_gp_clk1), - FUNCTION(gcc_gp_clk2), - FUNCTION(gcc_gp_clk3), - FUNCTION(qua_mi2s), - FUNCTION(pri_mi2s), - FUNCTION(spkr_mi2s), - FUNCTION(ter_mi2s), - FUNCTION(sec_mi2s), - FUNCTION(mdp_vsync), - FUNCTION(cam_mclk0), - FUNCTION(cam_mclk1), - FUNCTION(cam_mclk2), - FUNCTION(cam_mclk3), - FUNCTION(cci_timer0), - FUNCTION(cci_timer1), - FUNCTION(cci_timer2), - FUNCTION(cci_timer3), - FUNCTION(cci_timer4), - FUNCTION(cci_async_in0), - FUNCTION(cci_async_in1), - FUNCTION(cci_async_in2), - FUNCTION(hdmi_cec), - FUNCTION(hdmi_ddc), - FUNCTION(hdmi_hpd), - FUNCTION(edp_hpd), - FUNCTION(gp_pdm0), - FUNCTION(gp_pdm1), - FUNCTION(gp_pdm2), - FUNCTION(gp0_clk), - FUNCTION(gp1_clk), - FUNCTION(gp_mn), - FUNCTION(tsif1), - FUNCTION(tsif2), - FUNCTION(hsic), - FUNCTION(grfc), - FUNCTION(audio_ref_clk), - FUNCTION(bt), - FUNCTION(fm), - FUNCTION(wlan), - FUNCTION(slimbus), -}; - -static const struct msm_pingroup msm8x74_groups[] = { - PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), - PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), - PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), - PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), - PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), - PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), - PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), - PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), - PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA), - PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA), - PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA), - PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA), - PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), - PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), - PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), - PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), - PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), - PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), - PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), - PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), - PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), - PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), - PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), - PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), - PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), - PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA), - PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA), - PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA), - PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA), - PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA), - PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), - PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), - PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), - PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), - PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA), - PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA), - PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), - PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), - PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), - PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), - PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), - PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), - PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), - PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA), - PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA), - PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), - PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), - PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), - PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), - PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA), - PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA), - PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), - PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), - PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), - PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA), - PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA), - PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA), - PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA), - PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA), - PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA), - PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA), - PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA), - PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), - PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), - PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA), - PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), - PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA), - PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA), - PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA), - PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA), - PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), - PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), - PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), - PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA), - PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), - PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), - PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA), - PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA), - PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA), - PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA), - PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA), - PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA), - PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA), - PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA), - PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA), - PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA), - PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA), - PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA), - PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA), - PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA), - PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA), - PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(129, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(130, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(131, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(132, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(133, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(134, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(135, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(140, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(142, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA), - PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA), - PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA), - SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), - SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), - SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), - SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), - SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), - SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), -}; - -#define NUM_GPIO_PINGROUPS 146 - -static const struct msm_pinctrl_soc_data msm8x74_pinctrl = { - .pins = msm8x74_pins, - .npins = ARRAY_SIZE(msm8x74_pins), - .functions = msm8x74_functions, - .nfunctions = ARRAY_SIZE(msm8x74_functions), - .groups = msm8x74_groups, - .ngroups = ARRAY_SIZE(msm8x74_groups), - .ngpios = NUM_GPIO_PINGROUPS, -}; - -static int msm8x74_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &msm8x74_pinctrl); -} - -static const struct of_device_id msm8x74_pinctrl_of_match[] = { - { .compatible = "qcom,msm8974-pinctrl", }, - { }, -}; - -static struct platform_driver msm8x74_pinctrl_driver = { - .driver = { - .name = "msm8x74-pinctrl", - .owner = THIS_MODULE, - .of_match_table = msm8x74_pinctrl_of_match, - }, - .probe = msm8x74_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init msm8x74_pinctrl_init(void) -{ - return platform_driver_register(&msm8x74_pinctrl_driver); -} -arch_initcall(msm8x74_pinctrl_init); - -static void __exit msm8x74_pinctrl_exit(void) -{ - platform_driver_unregister(&msm8x74_pinctrl_driver); -} -module_exit(msm8x74_pinctrl_exit); - -MODULE_AUTHOR("Bjorn Andersson "); -MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); - diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig new file mode 100644 index 000000000000..d160a710d704 --- /dev/null +++ b/drivers/pinctrl/qcom/Kconfig @@ -0,0 +1,42 @@ +if (ARCH_QCOM || COMPILE_TEST) + +config PINCTRL_MSM + bool + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB_IRQCHIP + +config PINCTRL_APQ8064 + tristate "Qualcomm APQ8064 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm APQ8064 platform. + +config PINCTRL_IPQ8064 + tristate "Qualcomm IPQ8064 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. + +config PINCTRL_MSM8960 + tristate "Qualcomm 8960 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8960 platform. + +config PINCTRL_MSM8X74 + tristate "Qualcomm 8x74 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm 8974 platform. + +endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile new file mode 100644 index 000000000000..2a02602d715c --- /dev/null +++ b/drivers/pinctrl/qcom/Makefile @@ -0,0 +1,6 @@ +# Qualcomm pin control drivers +obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o +obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o +obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o +obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c new file mode 100644 index 000000000000..519f7886b0f1 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c @@ -0,0 +1,613 @@ +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc apq8064_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + + PINCTRL_PIN(90, "SDC1_CLK"), + PINCTRL_PIN(91, "SDC1_CMD"), + PINCTRL_PIN(92, "SDC1_DATA"), + PINCTRL_PIN(93, "SDC3_CLK"), + PINCTRL_PIN(94, "SDC3_CMD"), + PINCTRL_PIN(95, "SDC3_DATA"), +}; + +#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_APQ_GPIO_PINS(0); +DECLARE_APQ_GPIO_PINS(1); +DECLARE_APQ_GPIO_PINS(2); +DECLARE_APQ_GPIO_PINS(3); +DECLARE_APQ_GPIO_PINS(4); +DECLARE_APQ_GPIO_PINS(5); +DECLARE_APQ_GPIO_PINS(6); +DECLARE_APQ_GPIO_PINS(7); +DECLARE_APQ_GPIO_PINS(8); +DECLARE_APQ_GPIO_PINS(9); +DECLARE_APQ_GPIO_PINS(10); +DECLARE_APQ_GPIO_PINS(11); +DECLARE_APQ_GPIO_PINS(12); +DECLARE_APQ_GPIO_PINS(13); +DECLARE_APQ_GPIO_PINS(14); +DECLARE_APQ_GPIO_PINS(15); +DECLARE_APQ_GPIO_PINS(16); +DECLARE_APQ_GPIO_PINS(17); +DECLARE_APQ_GPIO_PINS(18); +DECLARE_APQ_GPIO_PINS(19); +DECLARE_APQ_GPIO_PINS(20); +DECLARE_APQ_GPIO_PINS(21); +DECLARE_APQ_GPIO_PINS(22); +DECLARE_APQ_GPIO_PINS(23); +DECLARE_APQ_GPIO_PINS(24); +DECLARE_APQ_GPIO_PINS(25); +DECLARE_APQ_GPIO_PINS(26); +DECLARE_APQ_GPIO_PINS(27); +DECLARE_APQ_GPIO_PINS(28); +DECLARE_APQ_GPIO_PINS(29); +DECLARE_APQ_GPIO_PINS(30); +DECLARE_APQ_GPIO_PINS(31); +DECLARE_APQ_GPIO_PINS(32); +DECLARE_APQ_GPIO_PINS(33); +DECLARE_APQ_GPIO_PINS(34); +DECLARE_APQ_GPIO_PINS(35); +DECLARE_APQ_GPIO_PINS(36); +DECLARE_APQ_GPIO_PINS(37); +DECLARE_APQ_GPIO_PINS(38); +DECLARE_APQ_GPIO_PINS(39); +DECLARE_APQ_GPIO_PINS(40); +DECLARE_APQ_GPIO_PINS(41); +DECLARE_APQ_GPIO_PINS(42); +DECLARE_APQ_GPIO_PINS(43); +DECLARE_APQ_GPIO_PINS(44); +DECLARE_APQ_GPIO_PINS(45); +DECLARE_APQ_GPIO_PINS(46); +DECLARE_APQ_GPIO_PINS(47); +DECLARE_APQ_GPIO_PINS(48); +DECLARE_APQ_GPIO_PINS(49); +DECLARE_APQ_GPIO_PINS(50); +DECLARE_APQ_GPIO_PINS(51); +DECLARE_APQ_GPIO_PINS(52); +DECLARE_APQ_GPIO_PINS(53); +DECLARE_APQ_GPIO_PINS(54); +DECLARE_APQ_GPIO_PINS(55); +DECLARE_APQ_GPIO_PINS(56); +DECLARE_APQ_GPIO_PINS(57); +DECLARE_APQ_GPIO_PINS(58); +DECLARE_APQ_GPIO_PINS(59); +DECLARE_APQ_GPIO_PINS(60); +DECLARE_APQ_GPIO_PINS(61); +DECLARE_APQ_GPIO_PINS(62); +DECLARE_APQ_GPIO_PINS(63); +DECLARE_APQ_GPIO_PINS(64); +DECLARE_APQ_GPIO_PINS(65); +DECLARE_APQ_GPIO_PINS(66); +DECLARE_APQ_GPIO_PINS(67); +DECLARE_APQ_GPIO_PINS(68); +DECLARE_APQ_GPIO_PINS(69); +DECLARE_APQ_GPIO_PINS(70); +DECLARE_APQ_GPIO_PINS(71); +DECLARE_APQ_GPIO_PINS(72); +DECLARE_APQ_GPIO_PINS(73); +DECLARE_APQ_GPIO_PINS(74); +DECLARE_APQ_GPIO_PINS(75); +DECLARE_APQ_GPIO_PINS(76); +DECLARE_APQ_GPIO_PINS(77); +DECLARE_APQ_GPIO_PINS(78); +DECLARE_APQ_GPIO_PINS(79); +DECLARE_APQ_GPIO_PINS(80); +DECLARE_APQ_GPIO_PINS(81); +DECLARE_APQ_GPIO_PINS(82); +DECLARE_APQ_GPIO_PINS(83); +DECLARE_APQ_GPIO_PINS(84); +DECLARE_APQ_GPIO_PINS(85); +DECLARE_APQ_GPIO_PINS(86); +DECLARE_APQ_GPIO_PINS(87); +DECLARE_APQ_GPIO_PINS(88); +DECLARE_APQ_GPIO_PINS(89); + +static const unsigned int sdc1_clk_pins[] = { 90 }; +static const unsigned int sdc1_cmd_pins[] = { 91 }; +static const unsigned int sdc1_data_pins[] = { 92 }; +static const unsigned int sdc3_clk_pins[] = { 93 }; +static const unsigned int sdc3_cmd_pins[] = { 94 }; +static const unsigned int sdc3_data_pins[] = { 95 }; + +#define FUNCTION(fname) \ + [APQ_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + APQ_MUX_NA, /* gpio mode */ \ + APQ_MUX_##f1, \ + APQ_MUX_##f2, \ + APQ_MUX_##f3, \ + APQ_MUX_##f4, \ + APQ_MUX_##f5, \ + APQ_MUX_##f6, \ + APQ_MUX_##f7, \ + APQ_MUX_##f8, \ + APQ_MUX_##f9, \ + APQ_MUX_##f10, \ + }, \ + .nfuncs = 11, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum apq8064_functions { + APQ_MUX_cam_mclk, + APQ_MUX_codec_mic_i2s, + APQ_MUX_codec_spkr_i2s, + APQ_MUX_gsbi1, + APQ_MUX_gsbi2, + APQ_MUX_gsbi3, + APQ_MUX_gsbi4, + APQ_MUX_gsbi4_cam_i2c, + APQ_MUX_gsbi5, + APQ_MUX_gsbi5_spi_cs1, + APQ_MUX_gsbi5_spi_cs2, + APQ_MUX_gsbi5_spi_cs3, + APQ_MUX_gsbi6, + APQ_MUX_gsbi6_spi_cs1, + APQ_MUX_gsbi6_spi_cs2, + APQ_MUX_gsbi6_spi_cs3, + APQ_MUX_gsbi7, + APQ_MUX_gsbi7_spi_cs1, + APQ_MUX_gsbi7_spi_cs2, + APQ_MUX_gsbi7_spi_cs3, + APQ_MUX_gsbi_cam_i2c, + APQ_MUX_hdmi, + APQ_MUX_mi2s, + APQ_MUX_riva_bt, + APQ_MUX_riva_fm, + APQ_MUX_riva_wlan, + APQ_MUX_sdc2, + APQ_MUX_sdc4, + APQ_MUX_slimbus, + APQ_MUX_spkr_i2s, + APQ_MUX_tsif1, + APQ_MUX_tsif2, + APQ_MUX_usb2_hsic, + APQ_MUX_NA, +}; + +static const char * const cam_mclk_groups[] = { + "gpio4" "gpio5" +}; +static const char * const codec_mic_i2s_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38" +}; +static const char * const codec_spkr_i2s_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42" +}; +static const char * const gsbi1_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21" +}; +static const char * const gsbi2_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char * const gsbi3_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9" +}; +static const char * const gsbi4_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const gsbi4_cam_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const gsbi5_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54" +}; +static const char * const gsbi5_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi5_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi5_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi6_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17" +}; +static const char * const gsbi6_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi6_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi6_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi7_groups[] = { + "gpio82", "gpio83", "gpio84", "gpio85" +}; +static const char * const gsbi7_spi_cs1_groups[] = { + "gpio47" +}; +static const char * const gsbi7_spi_cs2_groups[] = { + "gpio31" +}; +static const char * const gsbi7_spi_cs3_groups[] = { + "gpio32" +}; +static const char * const gsbi_cam_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; +static const char * const hdmi_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; +static const char * const mi2s_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33" +}; +static const char * const riva_bt_groups[] = { + "gpio16", "gpio17" +}; +static const char * const riva_fm_groups[] = { + "gpio14", "gpio15" +}; +static const char * const riva_wlan_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const sdc2_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62" +}; +static const char * const sdc4_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; +static const char * const slimbus_groups[] = { + "gpio40", "gpio41" +}; +static const char * const spkr_i2s_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50" +}; +static const char * const tsif1_groups[] = { + "gpio55", "gpio56", "gpio57" +}; +static const char * const tsif2_groups[] = { + "gpio58", "gpio59", "gpio60" +}; +static const char * const usb2_hsic_groups[] = { + "gpio88", "gpio89" +}; + +static const struct msm_function apq8064_functions[] = { + FUNCTION(cam_mclk), + FUNCTION(codec_mic_i2s), + FUNCTION(codec_spkr_i2s), + FUNCTION(gsbi1), + FUNCTION(gsbi2), + FUNCTION(gsbi3), + FUNCTION(gsbi4), + FUNCTION(gsbi4_cam_i2c), + FUNCTION(gsbi5), + FUNCTION(gsbi5_spi_cs1), + FUNCTION(gsbi5_spi_cs2), + FUNCTION(gsbi5_spi_cs3), + FUNCTION(gsbi6), + FUNCTION(gsbi6_spi_cs1), + FUNCTION(gsbi6_spi_cs2), + FUNCTION(gsbi6_spi_cs3), + FUNCTION(gsbi7), + FUNCTION(gsbi7_spi_cs1), + FUNCTION(gsbi7_spi_cs2), + FUNCTION(gsbi7_spi_cs3), + FUNCTION(gsbi_cam_i2c), + FUNCTION(hdmi), + FUNCTION(mi2s), + FUNCTION(riva_bt), + FUNCTION(riva_fm), + FUNCTION(riva_wlan), + FUNCTION(sdc2), + FUNCTION(sdc4), + FUNCTION(slimbus), + FUNCTION(spkr_i2s), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(usb2_hsic), +}; + +static const struct msm_pingroup apq8064_groups[] = { + PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi4, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c, NA), + PINGROUP(11, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, gsbi4_cam_i2c), + PINGROUP(12, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), + PINGROUP(13, gsbi4, NA, NA, NA, NA, gsbi4_cam_i2c, NA, NA, NA, NA), + PINGROUP(14, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, riva_fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, riva_bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA), + PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA), + PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, slimbus, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA), + PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, tsif1, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, tsif2, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, sdc2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, riva_wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, hdmi, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, gsbi7, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 90 + +static const struct msm_pinctrl_soc_data apq8064_pinctrl = { + .pins = apq8064_pins, + .npins = ARRAY_SIZE(apq8064_pins), + .functions = apq8064_functions, + .nfunctions = ARRAY_SIZE(apq8064_functions), + .groups = apq8064_groups, + .ngroups = ARRAY_SIZE(apq8064_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int apq8064_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &apq8064_pinctrl); +} + +static const struct of_device_id apq8064_pinctrl_of_match[] = { + { .compatible = "qcom,apq8064-pinctrl", }, + { }, +}; + +static struct platform_driver apq8064_pinctrl_driver = { + .driver = { + .name = "apq8064-pinctrl", + .owner = THIS_MODULE, + .of_match_table = apq8064_pinctrl_of_match, + }, + .probe = apq8064_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init apq8064_pinctrl_init(void) +{ + return platform_driver_register(&apq8064_pinctrl_driver); +} +arch_initcall(apq8064_pinctrl_init); + +static void __exit apq8064_pinctrl_exit(void) +{ + platform_driver_unregister(&apq8064_pinctrl_driver); +} +module_exit(apq8064_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm APQ8064 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, apq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c new file mode 100644 index 000000000000..acafea4c3a33 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c @@ -0,0 +1,653 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc ipq8064_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + + PINCTRL_PIN(69, "SDC3_CLK"), + PINCTRL_PIN(70, "SDC3_CMD"), + PINCTRL_PIN(71, "SDC3_DATA"), +}; + +#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_IPQ_GPIO_PINS(0); +DECLARE_IPQ_GPIO_PINS(1); +DECLARE_IPQ_GPIO_PINS(2); +DECLARE_IPQ_GPIO_PINS(3); +DECLARE_IPQ_GPIO_PINS(4); +DECLARE_IPQ_GPIO_PINS(5); +DECLARE_IPQ_GPIO_PINS(6); +DECLARE_IPQ_GPIO_PINS(7); +DECLARE_IPQ_GPIO_PINS(8); +DECLARE_IPQ_GPIO_PINS(9); +DECLARE_IPQ_GPIO_PINS(10); +DECLARE_IPQ_GPIO_PINS(11); +DECLARE_IPQ_GPIO_PINS(12); +DECLARE_IPQ_GPIO_PINS(13); +DECLARE_IPQ_GPIO_PINS(14); +DECLARE_IPQ_GPIO_PINS(15); +DECLARE_IPQ_GPIO_PINS(16); +DECLARE_IPQ_GPIO_PINS(17); +DECLARE_IPQ_GPIO_PINS(18); +DECLARE_IPQ_GPIO_PINS(19); +DECLARE_IPQ_GPIO_PINS(20); +DECLARE_IPQ_GPIO_PINS(21); +DECLARE_IPQ_GPIO_PINS(22); +DECLARE_IPQ_GPIO_PINS(23); +DECLARE_IPQ_GPIO_PINS(24); +DECLARE_IPQ_GPIO_PINS(25); +DECLARE_IPQ_GPIO_PINS(26); +DECLARE_IPQ_GPIO_PINS(27); +DECLARE_IPQ_GPIO_PINS(28); +DECLARE_IPQ_GPIO_PINS(29); +DECLARE_IPQ_GPIO_PINS(30); +DECLARE_IPQ_GPIO_PINS(31); +DECLARE_IPQ_GPIO_PINS(32); +DECLARE_IPQ_GPIO_PINS(33); +DECLARE_IPQ_GPIO_PINS(34); +DECLARE_IPQ_GPIO_PINS(35); +DECLARE_IPQ_GPIO_PINS(36); +DECLARE_IPQ_GPIO_PINS(37); +DECLARE_IPQ_GPIO_PINS(38); +DECLARE_IPQ_GPIO_PINS(39); +DECLARE_IPQ_GPIO_PINS(40); +DECLARE_IPQ_GPIO_PINS(41); +DECLARE_IPQ_GPIO_PINS(42); +DECLARE_IPQ_GPIO_PINS(43); +DECLARE_IPQ_GPIO_PINS(44); +DECLARE_IPQ_GPIO_PINS(45); +DECLARE_IPQ_GPIO_PINS(46); +DECLARE_IPQ_GPIO_PINS(47); +DECLARE_IPQ_GPIO_PINS(48); +DECLARE_IPQ_GPIO_PINS(49); +DECLARE_IPQ_GPIO_PINS(50); +DECLARE_IPQ_GPIO_PINS(51); +DECLARE_IPQ_GPIO_PINS(52); +DECLARE_IPQ_GPIO_PINS(53); +DECLARE_IPQ_GPIO_PINS(54); +DECLARE_IPQ_GPIO_PINS(55); +DECLARE_IPQ_GPIO_PINS(56); +DECLARE_IPQ_GPIO_PINS(57); +DECLARE_IPQ_GPIO_PINS(58); +DECLARE_IPQ_GPIO_PINS(59); +DECLARE_IPQ_GPIO_PINS(60); +DECLARE_IPQ_GPIO_PINS(61); +DECLARE_IPQ_GPIO_PINS(62); +DECLARE_IPQ_GPIO_PINS(63); +DECLARE_IPQ_GPIO_PINS(64); +DECLARE_IPQ_GPIO_PINS(65); +DECLARE_IPQ_GPIO_PINS(66); +DECLARE_IPQ_GPIO_PINS(67); +DECLARE_IPQ_GPIO_PINS(68); + +static const unsigned int sdc3_clk_pins[] = { 69 }; +static const unsigned int sdc3_cmd_pins[] = { 70 }; +static const unsigned int sdc3_data_pins[] = { 71 }; + +#define FUNCTION(fname) \ + [IPQ_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + IPQ_MUX_NA, /* gpio mode */ \ + IPQ_MUX_##f1, \ + IPQ_MUX_##f2, \ + IPQ_MUX_##f3, \ + IPQ_MUX_##f4, \ + IPQ_MUX_##f5, \ + IPQ_MUX_##f6, \ + IPQ_MUX_##f7, \ + IPQ_MUX_##f8, \ + IPQ_MUX_##f9, \ + IPQ_MUX_##f10, \ + }, \ + .nfuncs = 11, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum ipq8064_functions { + IPQ_MUX_mdio, + IPQ_MUX_mi2s, + IPQ_MUX_pdm, + IPQ_MUX_ssbi, + IPQ_MUX_spmi, + IPQ_MUX_audio_pcm, + IPQ_MUX_gsbi1, + IPQ_MUX_gsbi2, + IPQ_MUX_gsbi4, + IPQ_MUX_gsbi5, + IPQ_MUX_gsbi5_spi_cs1, + IPQ_MUX_gsbi5_spi_cs2, + IPQ_MUX_gsbi5_spi_cs3, + IPQ_MUX_gsbi6, + IPQ_MUX_gsbi7, + IPQ_MUX_nss_spi, + IPQ_MUX_sdc1, + IPQ_MUX_spdif, + IPQ_MUX_nand, + IPQ_MUX_tsif1, + IPQ_MUX_tsif2, + IPQ_MUX_usb_fs_n, + IPQ_MUX_usb_fs, + IPQ_MUX_usb2_hsic, + IPQ_MUX_rgmii2, + IPQ_MUX_sata, + IPQ_MUX_pcie1_rst, + IPQ_MUX_pcie1_prsnt, + IPQ_MUX_pcie1_pwrflt, + IPQ_MUX_pcie1_pwren_n, + IPQ_MUX_pcie1_pwren, + IPQ_MUX_pcie1_clk_req, + IPQ_MUX_pcie2_rst, + IPQ_MUX_pcie2_prsnt, + IPQ_MUX_pcie2_pwrflt, + IPQ_MUX_pcie2_pwren_n, + IPQ_MUX_pcie2_pwren, + IPQ_MUX_pcie2_clk_req, + IPQ_MUX_pcie3_rst, + IPQ_MUX_pcie3_prsnt, + IPQ_MUX_pcie3_pwrflt, + IPQ_MUX_pcie3_pwren_n, + IPQ_MUX_pcie3_pwren, + IPQ_MUX_pcie3_clk_req, + IPQ_MUX_ps_hold, + IPQ_MUX_NA, +}; + +static const char * const mdio_groups[] = { + "gpio0", "gpio1", "gpio10", "gpio11", +}; + +static const char * const mi2s_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio33", "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const pdm_groups[] = { + "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31", + "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58", + "gpio59", +}; + +static const char * const ssbi_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const spmi_groups[] = { + "gpio10", "gpio11", +}; + +static const char * const audio_pcm_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", +}; + +static const char * const gsbi1_groups[] = { + "gpio51", "gpio52", "gpio53", "gpio54", +}; + +static const char * const gsbi2_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char * const gsbi4_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; + +static const char * const gsbi5_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const gsbi5_spi_cs1_groups[] = { + "gpio6", "gpio61", +}; + +static const char * const gsbi5_spi_cs2_groups[] = { + "gpio7", "gpio62", +}; + +static const char * const gsbi5_spi_cs3_groups[] = { + "gpio2", +}; + +static const char * const gsbi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56", + "gpio57", "gpio58", +}; + +static const char * const gsbi7_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; + +static const char * const nss_spi_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56", + "gpio57", "gpio58", +}; + +static const char * const sdc1_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char * const spdif_groups[] = { + "gpio10", "gpio48", +}; + +static const char * const nand_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", +}; + +static const char * const tsif1_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const tsif2_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const usb_fs_n_groups[] = { + "gpio6", +}; + +static const char * const usb_fs_groups[] = { + "gpio6", "gpio7", "gpio8", +}; + +static const char * const usb2_hsic_groups[] = { + "gpio67", "gpio68", +}; + +static const char * const rgmii2_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const sata_groups[] = { + "gpio10", +}; + +static const char * const pcie1_rst_groups[] = { + "gpio3", +}; + +static const char * const pcie1_prsnt_groups[] = { + "gpio3", "gpio11", +}; + +static const char * const pcie1_pwren_n_groups[] = { + "gpio4", "gpio12", +}; + +static const char * const pcie1_pwren_groups[] = { + "gpio4", "gpio12", +}; + +static const char * const pcie1_pwrflt_groups[] = { + "gpio5", "gpio13", +}; + +static const char * const pcie1_clk_req_groups[] = { + "gpio5", +}; + +static const char * const pcie2_rst_groups[] = { + "gpio48", +}; + +static const char * const pcie2_prsnt_groups[] = { + "gpio11", "gpio48", +}; + +static const char * const pcie2_pwren_n_groups[] = { + "gpio12", "gpio49", +}; + +static const char * const pcie2_pwren_groups[] = { + "gpio12", "gpio49", +}; + +static const char * const pcie2_pwrflt_groups[] = { + "gpio13", "gpio50", +}; + +static const char * const pcie2_clk_req_groups[] = { + "gpio50", +}; + +static const char * const pcie3_rst_groups[] = { + "gpio63", +}; + +static const char * const pcie3_prsnt_groups[] = { + "gpio11", +}; + +static const char * const pcie3_pwren_n_groups[] = { + "gpio12", +}; + +static const char * const pcie3_pwren_groups[] = { + "gpio12", +}; + +static const char * const pcie3_pwrflt_groups[] = { + "gpio13", +}; + +static const char * const pcie3_clk_req_groups[] = { + "gpio65", +}; + +static const char * const ps_hold_groups[] = { + "gpio26", +}; + +static const struct msm_function ipq8064_functions[] = { + FUNCTION(mdio), + FUNCTION(ssbi), + FUNCTION(spmi), + FUNCTION(mi2s), + FUNCTION(pdm), + FUNCTION(audio_pcm), + FUNCTION(gsbi1), + FUNCTION(gsbi2), + FUNCTION(gsbi4), + FUNCTION(gsbi5), + FUNCTION(gsbi5_spi_cs1), + FUNCTION(gsbi5_spi_cs2), + FUNCTION(gsbi5_spi_cs3), + FUNCTION(gsbi6), + FUNCTION(gsbi7), + FUNCTION(nss_spi), + FUNCTION(sdc1), + FUNCTION(spdif), + FUNCTION(nand), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(usb_fs_n), + FUNCTION(usb_fs), + FUNCTION(usb2_hsic), + FUNCTION(rgmii2), + FUNCTION(sata), + FUNCTION(pcie1_rst), + FUNCTION(pcie1_prsnt), + FUNCTION(pcie1_pwren_n), + FUNCTION(pcie1_pwren), + FUNCTION(pcie1_pwrflt), + FUNCTION(pcie1_clk_req), + FUNCTION(pcie2_rst), + FUNCTION(pcie2_prsnt), + FUNCTION(pcie2_pwren_n), + FUNCTION(pcie2_pwren), + FUNCTION(pcie2_pwrflt), + FUNCTION(pcie2_clk_req), + FUNCTION(pcie3_rst), + FUNCTION(pcie3_prsnt), + FUNCTION(pcie3_pwren_n), + FUNCTION(pcie3_pwren), + FUNCTION(pcie3_pwrflt), + FUNCTION(pcie3_clk_req), + FUNCTION(ps_hold), +}; + +static const struct msm_pingroup ipq8064_groups[] = { + PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA), + PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA), + PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA), + PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA), + PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA), + PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA), + PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA), + PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3), + SDC_PINGROUP(sdc3_data, 0x204a, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 69 + +static const struct msm_pinctrl_soc_data ipq8064_pinctrl = { + .pins = ipq8064_pins, + .npins = ARRAY_SIZE(ipq8064_pins), + .functions = ipq8064_functions, + .nfunctions = ARRAY_SIZE(ipq8064_functions), + .groups = ipq8064_groups, + .ngroups = ARRAY_SIZE(ipq8064_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int ipq8064_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq8064_pinctrl); +} + +static const struct of_device_id ipq8064_pinctrl_of_match[] = { + { .compatible = "qcom,ipq8064-pinctrl", }, + { }, +}; + +static struct platform_driver ipq8064_pinctrl_driver = { + .driver = { + .name = "ipq8064-pinctrl", + .owner = THIS_MODULE, + .of_match_table = ipq8064_pinctrl_of_match, + }, + .probe = ipq8064_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq8064_pinctrl_init(void) +{ + return platform_driver_register(&ipq8064_pinctrl_driver); +} +arch_initcall(ipq8064_pinctrl_init); + +static void __exit ipq8064_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq8064_pinctrl_driver); +} +module_exit(ipq8064_pinctrl_exit); + +MODULE_AUTHOR("Andy Gross "); +MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c new file mode 100644 index 000000000000..90d383d3ce17 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -0,0 +1,922 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinconf.h" +#include "pinctrl-msm.h" +#include "../pinctrl-utils.h" + +#define MAX_NR_GPIO 300 + +/** + * struct msm_pinctrl - state for a pinctrl-msm device + * @dev: device handle. + * @pctrl: pinctrl handle. + * @chip: gpiochip handle. + * @irq: parent irq for the TLMM irq_chip. + * @lock: Spinlock to protect register resources as well + * as msm_pinctrl data structures. + * @enabled_irqs: Bitmap of currently enabled irqs. + * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge + * detection. + * @soc; Reference to soc_data of platform specific data. + * @regs: Base address for the TLMM register map. + */ +struct msm_pinctrl { + struct device *dev; + struct pinctrl_dev *pctrl; + struct gpio_chip chip; + int irq; + + spinlock_t lock; + + DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); + DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); + + const struct msm_pinctrl_soc_data *soc; + void __iomem *regs; +}; + +static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) +{ + return container_of(gc, struct msm_pinctrl, chip); +} + +static int msm_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->ngroups; +} + +static const char *msm_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->groups[group].name; +} + +static int msm_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctrl->soc->groups[group].pins; + *num_pins = pctrl->soc->groups[group].npins; + return 0; +} + +static const struct pinctrl_ops msm_pinctrl_ops = { + .get_groups_count = msm_get_groups_count, + .get_group_name = msm_get_group_name, + .get_group_pins = msm_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_dt_free_map, +}; + +static int msm_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->nfunctions; +} + +static const char *msm_get_function_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + return pctrl->soc->functions[function].name; +} + +static int msm_get_function_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctrl->soc->functions[function].groups; + *num_groups = pctrl->soc->functions[function].ngroups; + return 0; +} + +static int msm_pinmux_enable(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + int i; + + g = &pctrl->soc->groups[group]; + + if (WARN_ON(g->mux_bit < 0)) + return -EINVAL; + + for (i = 0; i < g->nfuncs; i++) { + if (g->funcs[i] == function) + break; + } + + if (WARN_ON(i == g->nfuncs)) + return -EINVAL; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->ctl_reg); + val &= ~(0x7 << g->mux_bit); + val |= i << g->mux_bit; + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static const struct pinmux_ops msm_pinmux_ops = { + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, + .get_function_groups = msm_get_function_groups, + .enable = msm_pinmux_enable, +}; + +static int msm_config_reg(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g, + unsigned param, + unsigned *mask, + unsigned *bit) +{ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_BUS_HOLD: + case PIN_CONFIG_BIAS_PULL_UP: + *bit = g->pull_bit; + *mask = 3; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *bit = g->drv_bit; + *mask = 7; + break; + case PIN_CONFIG_OUTPUT: + *bit = g->oe_bit; + *mask = 1; + break; + default: + dev_err(pctrl->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + + return 0; +} + +static int msm_config_get(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *config) +{ + dev_err(pctldev->dev, "pin_config_set op not supported\n"); + return -ENOTSUPP; +} + +static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned num_configs) +{ + dev_err(pctldev->dev, "pin_config_set op not supported\n"); + return -ENOTSUPP; +} + +#define MSM_NO_PULL 0 +#define MSM_PULL_DOWN 1 +#define MSM_KEEPER 2 +#define MSM_PULL_UP 3 + +static unsigned msm_regval_to_drive(u32 val) +{ + return (val + 1) * 2; +} + +static int msm_config_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned param = pinconf_to_config_param(*config); + unsigned mask; + unsigned arg; + unsigned bit; + int ret; + u32 val; + + g = &pctrl->soc->groups[group]; + + ret = msm_config_reg(pctrl, g, param, &mask, &bit); + if (ret < 0) + return ret; + + val = readl(pctrl->regs + g->ctl_reg); + arg = (val >> bit) & mask; + + /* Convert register value to pinconf value */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = arg == MSM_NO_PULL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = arg == MSM_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + arg = arg == MSM_KEEPER; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = arg == MSM_PULL_UP; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = msm_regval_to_drive(arg); + break; + case PIN_CONFIG_OUTPUT: + /* Pin is not output */ + if (!arg) + return -EINVAL; + + val = readl(pctrl->regs + g->io_reg); + arg = !!(val & BIT(g->in_bit)); + break; + default: + dev_err(pctrl->dev, "Unsupported config parameter: %x\n", + param); + return -EINVAL; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int msm_config_group_set(struct pinctrl_dev *pctldev, + unsigned group, + unsigned long *configs, + unsigned num_configs) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + unsigned param; + unsigned mask; + unsigned arg; + unsigned bit; + int ret; + u32 val; + int i; + + g = &pctrl->soc->groups[group]; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + ret = msm_config_reg(pctrl, g, param, &mask, &bit); + if (ret < 0) + return ret; + + /* Convert pinconf values to register values */ + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = MSM_NO_PULL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = MSM_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_BUS_HOLD: + arg = MSM_KEEPER; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = MSM_PULL_UP; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + /* Check for invalid values */ + if (arg > 16 || arg < 2 || (arg % 2) != 0) + arg = -1; + else + arg = (arg / 2) - 1; + break; + case PIN_CONFIG_OUTPUT: + /* set output value */ + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->io_reg); + if (arg) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + + /* enable output */ + arg = 1; + break; + default: + dev_err(pctrl->dev, "Unsupported config parameter: %x\n", + param); + return -EINVAL; + } + + /* Range-check user-supplied value */ + if (arg & ~mask) { + dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); + return -EINVAL; + } + + spin_lock_irqsave(&pctrl->lock, flags); + val = readl(pctrl->regs + g->ctl_reg); + val &= ~(mask << bit); + val |= arg << bit; + writel(val, pctrl->regs + g->ctl_reg); + spin_unlock_irqrestore(&pctrl->lock, flags); + } + + return 0; +} + +static const struct pinconf_ops msm_pinconf_ops = { + .pin_config_get = msm_config_get, + .pin_config_set = msm_config_set, + .pin_config_group_get = msm_config_group_get, + .pin_config_group_set = msm_config_group_set, +}; + +static struct pinctrl_desc msm_pinctrl_desc = { + .pctlops = &msm_pinctrl_ops, + .pmxops = &msm_pinmux_ops, + .confops = &msm_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->ctl_reg); + val &= ~BIT(g->oe_bit); + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->io_reg); + if (value) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + + val = readl(pctrl->regs + g->ctl_reg); + val |= BIT(g->oe_bit); + writel(val, pctrl->regs + g->ctl_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + u32 val; + + g = &pctrl->soc->groups[offset]; + + val = readl(pctrl->regs + g->io_reg); + return !!(val & BIT(g->in_bit)); +} + +static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[offset]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->io_reg); + if (value) + val |= BIT(g->out_bit); + else + val &= ~BIT(g->out_bit); + writel(val, pctrl->regs + g->io_reg); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + return pinctrl_request_gpio(gpio); +} + +static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + return pinctrl_free_gpio(gpio); +} + +#ifdef CONFIG_DEBUG_FS +#include + +static void msm_gpio_dbg_show_one(struct seq_file *s, + struct pinctrl_dev *pctldev, + struct gpio_chip *chip, + unsigned offset, + unsigned gpio) +{ + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); + unsigned func; + int is_out; + int drive; + int pull; + u32 ctl_reg; + + static const char * const pulls[] = { + "no pull", + "pull down", + "keeper", + "pull up" + }; + + g = &pctrl->soc->groups[offset]; + ctl_reg = readl(pctrl->regs + g->ctl_reg); + + is_out = !!(ctl_reg & BIT(g->oe_bit)); + func = (ctl_reg >> g->mux_bit) & 7; + drive = (ctl_reg >> g->drv_bit) & 7; + pull = (ctl_reg >> g->pull_bit) & 3; + + seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); + seq_printf(s, " %dmA", msm_regval_to_drive(drive)); + seq_printf(s, " %s", pulls[pull]); +} + +static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned gpio = chip->base; + unsigned i; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); + seq_puts(s, "\n"); + } +} + +#else +#define msm_gpio_dbg_show NULL +#endif + +static struct gpio_chip msm_gpio_template = { + .direction_input = msm_gpio_direction_input, + .direction_output = msm_gpio_direction_output, + .get = msm_gpio_get, + .set = msm_gpio_set, + .request = msm_gpio_request, + .free = msm_gpio_free, + .dbg_show = msm_gpio_dbg_show, +}; + +/* For dual-edge interrupts in software, since some hardware has no + * such support: + * + * At appropriate moments, this function may be called to flip the polarity + * settings of both-edge irq lines to try and catch the next edge. + * + * The attempt is considered successful if: + * - the status bit goes high, indicating that an edge was caught, or + * - the input value of the gpio doesn't change during the attempt. + * If the value changes twice during the process, that would cause the first + * test to fail but would force the second, as two opposite + * transitions would cause a detection no matter the polarity setting. + * + * The do-loop tries to sledge-hammer closed the timing hole between + * the initial value-read and the polarity-write - if the line value changes + * during that window, an interrupt is lost, the new polarity setting is + * incorrect, and the first success test will fail, causing a retry. + * + * Algorithm comes from Google's msmgpio driver. + */ +static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, + const struct msm_pingroup *g, + struct irq_data *d) +{ + int loop_limit = 100; + unsigned val, val2, intstat; + unsigned pol; + + do { + val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); + + pol = readl(pctrl->regs + g->intr_cfg_reg); + pol ^= BIT(g->intr_polarity_bit); + writel(pol, pctrl->regs + g->intr_cfg_reg); + + val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); + intstat = readl(pctrl->regs + g->intr_status_reg); + if (intstat || (val == val2)) + return; + } while (loop_limit-- > 0); + dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", + val, val2); +} + +static void msm_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_cfg_reg); + val &= ~BIT(g->intr_enable_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + + clear_bit(d->hwirq, pctrl->enabled_irqs); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_status_reg); + val &= ~BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + + val = readl(pctrl->regs + g->intr_cfg_reg); + val |= BIT(g->intr_enable_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + + set_bit(d->hwirq, pctrl->enabled_irqs); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void msm_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + val = readl(pctrl->regs + g->intr_status_reg); + if (g->intr_ack_high) + val |= BIT(g->intr_status_bit); + else + val &= ~BIT(g->intr_status_bit); + writel(val, pctrl->regs + g->intr_status_reg); + + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(pctrl, g, d); + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + +#define INTR_TARGET_PROC_APPS 4 + +static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + const struct msm_pingroup *g; + unsigned long flags; + u32 val; + + g = &pctrl->soc->groups[d->hwirq]; + + spin_lock_irqsave(&pctrl->lock, flags); + + /* + * For hw without possibility of detecting both edges + */ + if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) + set_bit(d->hwirq, pctrl->dual_edge_irqs); + else + clear_bit(d->hwirq, pctrl->dual_edge_irqs); + + /* Route interrupts to application cpu */ + val = readl(pctrl->regs + g->intr_target_reg); + val &= ~(7 << g->intr_target_bit); + val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; + writel(val, pctrl->regs + g->intr_target_reg); + + /* Update configuration for gpio. + * RAW_STATUS_EN is left on for all gpio irqs. Due to the + * internal circuitry of TLMM, toggling the RAW_STATUS + * could cause the INTR_STATUS to be set for EDGE interrupts. + */ + val = readl(pctrl->regs + g->intr_cfg_reg); + val |= BIT(g->intr_raw_status_bit); + if (g->intr_detection_width == 2) { + val &= ~(3 << g->intr_detection_bit); + val &= ~(1 << g->intr_polarity_bit); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val |= 1 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_FALLING: + val |= 2 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_BOTH: + val |= 3 << g->intr_detection_bit; + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_LEVEL_LOW: + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= BIT(g->intr_polarity_bit); + break; + } + } else if (g->intr_detection_width == 1) { + val &= ~(1 << g->intr_detection_bit); + val &= ~(1 << g->intr_polarity_bit); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val |= BIT(g->intr_detection_bit); + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_EDGE_FALLING: + val |= BIT(g->intr_detection_bit); + break; + case IRQ_TYPE_EDGE_BOTH: + val |= BIT(g->intr_detection_bit); + val |= BIT(g->intr_polarity_bit); + break; + case IRQ_TYPE_LEVEL_LOW: + break; + case IRQ_TYPE_LEVEL_HIGH: + val |= BIT(g->intr_polarity_bit); + break; + } + } else { + BUG(); + } + writel(val, pctrl->regs + g->intr_cfg_reg); + + if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) + msm_gpio_update_dual_edge_pos(pctrl, g, d); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + __irq_set_handler_locked(d->irq, handle_level_irq); + else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + __irq_set_handler_locked(d->irq, handle_edge_irq); + + return 0; +} + +static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + unsigned long flags; + + spin_lock_irqsave(&pctrl->lock, flags); + + irq_set_irq_wake(pctrl->irq, on); + + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static struct irq_chip msm_gpio_irq_chip = { + .name = "msmgpio", + .irq_mask = msm_gpio_irq_mask, + .irq_unmask = msm_gpio_irq_unmask, + .irq_ack = msm_gpio_irq_ack, + .irq_set_type = msm_gpio_irq_set_type, + .irq_set_wake = msm_gpio_irq_set_wake, +}; + +static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + const struct msm_pingroup *g; + struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); + struct irq_chip *chip = irq_get_chip(irq); + int irq_pin; + int handled = 0; + u32 val; + int i; + + chained_irq_enter(chip, desc); + + /* + * Each pin has it's own IRQ status register, so use + * enabled_irq bitmap to limit the number of reads. + */ + for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { + g = &pctrl->soc->groups[i]; + val = readl(pctrl->regs + g->intr_status_reg); + if (val & BIT(g->intr_status_bit)) { + irq_pin = irq_find_mapping(gc->irqdomain, i); + generic_handle_irq(irq_pin); + handled++; + } + } + + /* No interrupts were flagged */ + if (handled == 0) + handle_bad_irq(irq, desc); + + chained_irq_exit(chip, desc); +} + +static int msm_gpio_init(struct msm_pinctrl *pctrl) +{ + struct gpio_chip *chip; + int ret; + unsigned ngpio = pctrl->soc->ngpios; + + if (WARN_ON(ngpio > MAX_NR_GPIO)) + return -EINVAL; + + chip = &pctrl->chip; + chip->base = 0; + chip->ngpio = ngpio; + chip->label = dev_name(pctrl->dev); + chip->dev = pctrl->dev; + chip->owner = THIS_MODULE; + chip->of_node = pctrl->dev->of_node; + + ret = gpiochip_add(&pctrl->chip); + if (ret) { + dev_err(pctrl->dev, "Failed register gpiochip\n"); + return ret; + } + + ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); + if (ret) { + dev_err(pctrl->dev, "Failed to add pin range\n"); + return ret; + } + + ret = gpiochip_irqchip_add(chip, + &msm_gpio_irq_chip, + 0, + handle_edge_irq, + IRQ_TYPE_NONE); + if (ret) { + dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); + return -ENOSYS; + } + + gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, + msm_gpio_irq_handler); + + return 0; +} + +int msm_pinctrl_probe(struct platform_device *pdev, + const struct msm_pinctrl_soc_data *soc_data) +{ + struct msm_pinctrl *pctrl; + struct resource *res; + int ret; + + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) { + dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); + return -ENOMEM; + } + pctrl->dev = &pdev->dev; + pctrl->soc = soc_data; + pctrl->chip = msm_gpio_template; + + spin_lock_init(&pctrl->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pctrl->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->regs)) + return PTR_ERR(pctrl->regs); + + pctrl->irq = platform_get_irq(pdev, 0); + if (pctrl->irq < 0) { + dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); + return pctrl->irq; + } + + msm_pinctrl_desc.name = dev_name(&pdev->dev); + msm_pinctrl_desc.pins = pctrl->soc->pins; + msm_pinctrl_desc.npins = pctrl->soc->npins; + pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); + if (!pctrl->pctrl) { + dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); + return -ENODEV; + } + + ret = msm_gpio_init(pctrl); + if (ret) { + pinctrl_unregister(pctrl->pctrl); + return ret; + } + + platform_set_drvdata(pdev, pctrl); + + dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); + + return 0; +} +EXPORT_SYMBOL(msm_pinctrl_probe); + +int msm_pinctrl_remove(struct platform_device *pdev) +{ + struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&pctrl->chip); + if (ret) { + dev_err(&pdev->dev, "Failed to remove gpiochip\n"); + return ret; + } + + pinctrl_unregister(pctrl->pctrl); + + return 0; +} +EXPORT_SYMBOL(msm_pinctrl_remove); + diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h new file mode 100644 index 000000000000..7b2a227a590a --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __PINCTRL_MSM_H__ +#define __PINCTRL_MSM_H__ + +struct pinctrl_pin_desc; + +/** + * struct msm_function - a pinmux function + * @name: Name of the pinmux function. + * @groups: List of pingroups for this function. + * @ngroups: Number of entries in @groups. + */ +struct msm_function { + const char *name; + const char * const *groups; + unsigned ngroups; +}; + +/** + * struct msm_pingroup - Qualcomm pingroup definition + * @name: Name of the pingroup. + * @pins: A list of pins assigned to this pingroup. + * @npins: Number of entries in @pins. + * @funcs: A list of pinmux functions that can be selected for + * this group. The index of the selected function is used + * for programming the function selector. + * Entries should be indices into the groups list of the + * struct msm_pinctrl_soc_data. + * @ctl_reg: Offset of the register holding control bits for this group. + * @io_reg: Offset of the register holding input/output bits for this group. + * @intr_cfg_reg: Offset of the register holding interrupt configuration bits. + * @intr_status_reg: Offset of the register holding the status bits for this group. + * @intr_target_reg: Offset of the register specifying routing of the interrupts + * from this group. + * @mux_bit: Offset in @ctl_reg for the pinmux function selection. + * @pull_bit: Offset in @ctl_reg for the bias configuration. + * @drv_bit: Offset in @ctl_reg for the drive strength configuration. + * @oe_bit: Offset in @ctl_reg for controlling output enable. + * @in_bit: Offset in @io_reg for the input bit value. + * @out_bit: Offset in @io_reg for the output bit value. + * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group. + * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt + * status. + * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. + * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. + * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. + * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. + * @intr_detection_width: Number of bits used for specifying interrupt type, + * Should be 2 for SoCs that can detect both edges in hardware, + * otherwise 1. + */ +struct msm_pingroup { + const char *name; + const unsigned *pins; + unsigned npins; + + unsigned *funcs; + unsigned nfuncs; + + s16 ctl_reg; + s16 io_reg; + s16 intr_cfg_reg; + s16 intr_status_reg; + s16 intr_target_reg; + + unsigned mux_bit:5; + + unsigned pull_bit:5; + unsigned drv_bit:5; + + unsigned oe_bit:5; + unsigned in_bit:5; + unsigned out_bit:5; + + unsigned intr_enable_bit:5; + unsigned intr_status_bit:5; + unsigned intr_ack_high:1; + + unsigned intr_target_bit:5; + unsigned intr_raw_status_bit:5; + unsigned intr_polarity_bit:5; + unsigned intr_detection_bit:5; + unsigned intr_detection_width:5; +}; + +/** + * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration + * @pins: An array describing all pins the pin controller affects. + * @npins: The number of entries in @pins. + * @functions: An array describing all mux functions the SoC supports. + * @nfunctions: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The numbmer of entries in @groups. + * @ngpio: The number of pingroups the driver should expose as GPIOs. + */ +struct msm_pinctrl_soc_data { + const struct pinctrl_pin_desc *pins; + unsigned npins; + const struct msm_function *functions; + unsigned nfunctions; + const struct msm_pingroup *groups; + unsigned ngroups; + unsigned ngpios; +}; + +int msm_pinctrl_probe(struct platform_device *pdev, + const struct msm_pinctrl_soc_data *soc_data); +int msm_pinctrl_remove(struct platform_device *pdev); + +#endif diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c new file mode 100644 index 000000000000..564543bb2c1c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -0,0 +1,1254 @@ +/* + * Copyright (c) 2014, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8960_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), + PINCTRL_PIN(155, "SDC3_CLK"), + PINCTRL_PIN(156, "SDC3_CMD"), + PINCTRL_PIN(157, "SDC3_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); + +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; +static const unsigned int sdc3_clk_pins[] = { 155 }; +static const unsigned int sdc3_cmd_pins[] = { 156 }; +static const unsigned int sdc3_data_pins[] = { 157 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_NA, /* gpio mode */ \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7, \ + MSM_MUX_##f8, \ + MSM_MUX_##f9, \ + MSM_MUX_##f10, \ + MSM_MUX_##f11 \ + }, \ + .nfuncs = 12, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x400 + 0x4 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_ack_high = 1, \ + .intr_target_bit = 0, \ + .intr_raw_status_bit = 3, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 1, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +enum msm8960_functions { + MSM_MUX_audio_pcm, + MSM_MUX_bt, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_cam_mclk2, + MSM_MUX_codec_mic_i2s, + MSM_MUX_codec_spkr_i2s, + MSM_MUX_ext_gps, + MSM_MUX_fm, + MSM_MUX_gps_blanking, + MSM_MUX_gps_pps_in, + MSM_MUX_gps_pps_out, + MSM_MUX_gp_clk_0a, + MSM_MUX_gp_clk_0b, + MSM_MUX_gp_clk_1a, + MSM_MUX_gp_clk_1b, + MSM_MUX_gp_clk_2a, + MSM_MUX_gp_clk_2b, + MSM_MUX_gp_mn, + MSM_MUX_gp_pdm_0a, + MSM_MUX_gp_pdm_0b, + MSM_MUX_gp_pdm_1a, + MSM_MUX_gp_pdm_1b, + MSM_MUX_gp_pdm_2a, + MSM_MUX_gp_pdm_2b, + MSM_MUX_gsbi1, + MSM_MUX_gsbi1_spi_cs1_n, + MSM_MUX_gsbi1_spi_cs2a_n, + MSM_MUX_gsbi1_spi_cs2b_n, + MSM_MUX_gsbi1_spi_cs3_n, + MSM_MUX_gsbi2, + MSM_MUX_gsbi2_spi_cs1_n, + MSM_MUX_gsbi2_spi_cs2_n, + MSM_MUX_gsbi2_spi_cs3_n, + MSM_MUX_gsbi3, + MSM_MUX_gsbi4, + MSM_MUX_gsbi4_3d_cam_i2c_l, + MSM_MUX_gsbi4_3d_cam_i2c_r, + MSM_MUX_gsbi5, + MSM_MUX_gsbi5_3d_cam_i2c_l, + MSM_MUX_gsbi5_3d_cam_i2c_r, + MSM_MUX_gsbi6, + MSM_MUX_gsbi7, + MSM_MUX_gsbi8, + MSM_MUX_gsbi9, + MSM_MUX_gsbi10, + MSM_MUX_gsbi11, + MSM_MUX_gsbi11_spi_cs1a_n, + MSM_MUX_gsbi11_spi_cs1b_n, + MSM_MUX_gsbi11_spi_cs2a_n, + MSM_MUX_gsbi11_spi_cs2b_n, + MSM_MUX_gsbi11_spi_cs3_n, + MSM_MUX_gsbi12, + MSM_MUX_hdmi_cec, + MSM_MUX_hdmi_ddc_clock, + MSM_MUX_hdmi_ddc_data, + MSM_MUX_hdmi_hot_plug_detect, + MSM_MUX_hsic, + MSM_MUX_mdp_vsync, + MSM_MUX_mi2s, + MSM_MUX_mic_i2s, + MSM_MUX_pmb_clk, + MSM_MUX_pmb_ext_ctrl, + MSM_MUX_ps_hold, + MSM_MUX_rpm_wdog, + MSM_MUX_sdc2, + MSM_MUX_sdc4, + MSM_MUX_sdc5, + MSM_MUX_slimbus1, + MSM_MUX_slimbus2, + MSM_MUX_spkr_i2s, + MSM_MUX_ssbi1, + MSM_MUX_ssbi2, + MSM_MUX_ssbi_ext_gps, + MSM_MUX_ssbi_pmic2, + MSM_MUX_ssbi_qpa1, + MSM_MUX_ssbi_ts, + MSM_MUX_tsif1, + MSM_MUX_tsif2, + MSM_MUX_ts_eoc, + MSM_MUX_usb_fs1, + MSM_MUX_usb_fs1_oe, + MSM_MUX_usb_fs1_oe_n, + MSM_MUX_usb_fs2, + MSM_MUX_usb_fs2_oe, + MSM_MUX_usb_fs2_oe_n, + MSM_MUX_vfe_camif_timer1_a, + MSM_MUX_vfe_camif_timer1_b, + MSM_MUX_vfe_camif_timer2, + MSM_MUX_vfe_camif_timer3_a, + MSM_MUX_vfe_camif_timer3_b, + MSM_MUX_vfe_camif_timer4_a, + MSM_MUX_vfe_camif_timer4_b, + MSM_MUX_vfe_camif_timer4_c, + MSM_MUX_vfe_camif_timer5_a, + MSM_MUX_vfe_camif_timer5_b, + MSM_MUX_vfe_camif_timer6_a, + MSM_MUX_vfe_camif_timer6_b, + MSM_MUX_vfe_camif_timer6_c, + MSM_MUX_vfe_camif_timer7_a, + MSM_MUX_vfe_camif_timer7_b, + MSM_MUX_vfe_camif_timer7_c, + MSM_MUX_wlan, + MSM_MUX_NA, +}; + +static const char * const audio_pcm_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66" +}; + +static const char * const bt_groups[] = { + "gpio28", "gpio29", "gpio83" +}; + +static const char * const cam_mclk0_groups[] = { + "gpio5" +}; + +static const char * const cam_mclk1_groups[] = { + "gpio4" +}; + +static const char * const cam_mclk2_groups[] = { + "gpio2" +}; + +static const char * const codec_mic_i2s_groups[] = { + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58" +}; + +static const char * const codec_spkr_i2s_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62" +}; + +static const char * const ext_gps_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; + +static const char * const fm_groups[] = { + "gpio26", "gpio27" +}; + +static const char * const gps_blanking_groups[] = { + "gpio137" +}; + +static const char * const gps_pps_in_groups[] = { + "gpio37" +}; + +static const char * const gps_pps_out_groups[] = { + "gpio37" +}; + +static const char * const gp_clk_0a_groups[] = { + "gpio3" +}; + +static const char * const gp_clk_0b_groups[] = { + "gpio54" +}; + +static const char * const gp_clk_1a_groups[] = { + "gpio4" +}; + +static const char * const gp_clk_1b_groups[] = { + "gpio70" +}; + +static const char * const gp_clk_2a_groups[] = { + "gpio52" +}; + +static const char * const gp_clk_2b_groups[] = { + "gpio37" +}; + +static const char * const gp_mn_groups[] = { + "gpio2" +}; + +static const char * const gp_pdm_0a_groups[] = { + "gpio58" +}; + +static const char * const gp_pdm_0b_groups[] = { + "gpio39" +}; + +static const char * const gp_pdm_1a_groups[] = { + "gpio94" +}; + +static const char * const gp_pdm_1b_groups[] = { + "gpio64" +}; + +static const char * const gp_pdm_2a_groups[] = { + "gpio69" +}; + +static const char * const gp_pdm_2b_groups[] = { + "gpio53" +}; + +static const char * const gsbi1_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9" +}; + +static const char * const gsbi1_spi_cs1_n_groups[] = { + "gpio14" +}; + +static const char * const gsbi1_spi_cs2a_n_groups[] = { + "gpio15" +}; + +static const char * const gsbi1_spi_cs2b_n_groups[] = { + "gpio17" +}; + +static const char * const gsbi1_spi_cs3_n_groups[] = { + "gpio16" +}; + +static const char * const gsbi2_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13" +}; + +static const char * const gsbi2_spi_cs1_n_groups[] = { + "gpio52" +}; + +static const char * const gsbi2_spi_cs2_n_groups[] = { + "gpio68" +}; + +static const char * const gsbi2_spi_cs3_n_groups[] = { + "gpio56" +}; + +static const char * const gsbi3_groups[] = { + "gpio14", "gpio15", "gpio16", "gpio17" +}; + +static const char * const gsbi4_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21" +}; + +static const char * const gsbi4_3d_cam_i2c_l_groups[] = { + "gpio18", "gpio19" +}; + +static const char * const gsbi4_3d_cam_i2c_r_groups[] = { + "gpio20", "gpio21" +}; + +static const char * const gsbi5_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; + +static const char * const gsbi5_3d_cam_i2c_l_groups[] = { + "gpio22", "gpio23" +}; + +static const char * const gsbi5_3d_cam_i2c_r_groups[] = { + "gpio24", "gpio25" +}; + +static const char * const gsbi6_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29" +}; + +static const char * const gsbi7_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33" +}; + +static const char * const gsbi8_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37" +}; + +static const char * const gsbi9_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gsbi10_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74" +}; + +static const char * const gsbi11_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41" +}; + +static const char * const gsbi11_spi_cs1a_n_groups[] = { + "gpio36" +}; + +static const char * const gsbi11_spi_cs1b_n_groups[] = { + "gpio18" +}; + +static const char * const gsbi11_spi_cs2a_n_groups[] = { + "gpio37" +}; + +static const char * const gsbi11_spi_cs2b_n_groups[] = { + "gpio19" +}; + +static const char * const gsbi11_spi_cs3_n_groups[] = { + "gpio76" +}; + +static const char * const gsbi12_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45" +}; + +static const char * const hdmi_cec_groups[] = { + "gpio99" +}; + +static const char * const hdmi_ddc_clock_groups[] = { + "gpio100" +}; + +static const char * const hdmi_ddc_data_groups[] = { + "gpio101" +}; + +static const char * const hdmi_hot_plug_detect_groups[] = { + "gpio102" +}; + +static const char * const hsic_groups[] = { + "gpio150", "gpio151" +}; + +static const char * const mdp_vsync_groups[] = { + "gpio0", "gpio1", "gpio19" +}; + +static const char * const mi2s_groups[] = { + "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53" +}; + +static const char * const mic_i2s_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74" +}; + +static const char * const pmb_clk_groups[] = { + "gpio21", "gpio86", "gpio112" +}; + +static const char * const pmb_ext_ctrl_groups[] = { + "gpio4", "gpio5" +}; + +static const char * const ps_hold_groups[] = { + "gpio108" +}; + +static const char * const rpm_wdog_groups[] = { + "gpio12" +}; + +static const char * const sdc2_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98" +}; + +static const char * const sdc4_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const sdc5_groups[] = { + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const slimbus1_groups[] = { + "gpio50", "gpio51", "gpio60", "gpio61" +}; + +static const char * const slimbus2_groups[] = { + "gpio42", "gpio43" +}; + +static const char * const spkr_i2s_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70" +}; + +static const char * const ssbi1_groups[] = { + "gpio141", "gpio143" +}; + +static const char * const ssbi2_groups[] = { + "gpio140", "gpio142" +}; + +static const char * const ssbi_ext_gps_groups[] = { + "gpio23" +}; + +static const char * const ssbi_pmic2_groups[] = { + "gpio149" +}; + +static const char * const ssbi_qpa1_groups[] = { + "gpio131" +}; + +static const char * const ssbi_ts_groups[] = { + "gpio10" +}; + +static const char * const tsif1_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio82" +}; + +static const char * const tsif2_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81" +}; + +static const char * const ts_eoc_groups[] = { + "gpio11" +}; + +static const char * const usb_fs1_groups[] = { + "gpio32", "gpio33" +}; + +static const char * const usb_fs1_oe_groups[] = { + "gpio31" +}; + +static const char * const usb_fs1_oe_n_groups[] = { + "gpio31" +}; + +static const char * const usb_fs2_groups[] = { + "gpio34", "gpio35" +}; + +static const char * const usb_fs2_oe_groups[] = { + "gpio36" +}; + +static const char * const usb_fs2_oe_n_groups[] = { + "gpio36" +}; + +static const char * const vfe_camif_timer1_a_groups[] = { + "gpio2" +}; + +static const char * const vfe_camif_timer1_b_groups[] = { + "gpio38" +}; + +static const char * const vfe_camif_timer2_groups[] = { + "gpio3" +}; + +static const char * const vfe_camif_timer3_a_groups[] = { + "gpio4" +}; + +static const char * const vfe_camif_timer3_b_groups[] = { + "gpio151" +}; + +static const char * const vfe_camif_timer4_a_groups[] = { + "gpio65" +}; + +static const char * const vfe_camif_timer4_b_groups[] = { + "gpio150" +}; + +static const char * const vfe_camif_timer4_c_groups[] = { + "gpio10" +}; + +static const char * const vfe_camif_timer5_a_groups[] = { + "gpio66" +}; + +static const char * const vfe_camif_timer5_b_groups[] = { + "gpio39" +}; + +static const char * const vfe_camif_timer6_a_groups[] = { + "gpio71" +}; + +static const char * const vfe_camif_timer6_b_groups[] = { + "gpio0" +}; + +static const char * const vfe_camif_timer6_c_groups[] = { + "gpio18" +}; + +static const char * const vfe_camif_timer7_a_groups[] = { + "gpio67" +}; + +static const char * const vfe_camif_timer7_b_groups[] = { + "gpio1" +}; + +static const char * const vfe_camif_timer7_c_groups[] = { + "gpio19" +}; + +static const char * const wlan_groups[] = { + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const struct msm_function msm8960_functions[] = { + FUNCTION(audio_pcm), + FUNCTION(bt), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cam_mclk2), + FUNCTION(codec_mic_i2s), + FUNCTION(codec_spkr_i2s), + FUNCTION(ext_gps), + FUNCTION(fm), + FUNCTION(gps_blanking), + FUNCTION(gps_pps_in), + FUNCTION(gps_pps_out), + FUNCTION(gp_clk_0a), + FUNCTION(gp_clk_0b), + FUNCTION(gp_clk_1a), + FUNCTION(gp_clk_1b), + FUNCTION(gp_clk_2a), + FUNCTION(gp_clk_2b), + FUNCTION(gp_mn), + FUNCTION(gp_pdm_0a), + FUNCTION(gp_pdm_0b), + FUNCTION(gp_pdm_1a), + FUNCTION(gp_pdm_1b), + FUNCTION(gp_pdm_2a), + FUNCTION(gp_pdm_2b), + FUNCTION(gsbi1), + FUNCTION(gsbi1_spi_cs1_n), + FUNCTION(gsbi1_spi_cs2a_n), + FUNCTION(gsbi1_spi_cs2b_n), + FUNCTION(gsbi1_spi_cs3_n), + FUNCTION(gsbi2), + FUNCTION(gsbi2_spi_cs1_n), + FUNCTION(gsbi2_spi_cs2_n), + FUNCTION(gsbi2_spi_cs3_n), + FUNCTION(gsbi3), + FUNCTION(gsbi4), + FUNCTION(gsbi4_3d_cam_i2c_l), + FUNCTION(gsbi4_3d_cam_i2c_r), + FUNCTION(gsbi5), + FUNCTION(gsbi5_3d_cam_i2c_l), + FUNCTION(gsbi5_3d_cam_i2c_r), + FUNCTION(gsbi6), + FUNCTION(gsbi7), + FUNCTION(gsbi8), + FUNCTION(gsbi9), + FUNCTION(gsbi10), + FUNCTION(gsbi11), + FUNCTION(gsbi11_spi_cs1a_n), + FUNCTION(gsbi11_spi_cs1b_n), + FUNCTION(gsbi11_spi_cs2a_n), + FUNCTION(gsbi11_spi_cs2b_n), + FUNCTION(gsbi11_spi_cs3_n), + FUNCTION(gsbi12), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc_clock), + FUNCTION(hdmi_ddc_data), + FUNCTION(hdmi_hot_plug_detect), + FUNCTION(hsic), + FUNCTION(mdp_vsync), + FUNCTION(mi2s), + FUNCTION(mic_i2s), + FUNCTION(pmb_clk), + FUNCTION(pmb_ext_ctrl), + FUNCTION(ps_hold), + FUNCTION(rpm_wdog), + FUNCTION(sdc2), + FUNCTION(sdc4), + FUNCTION(sdc5), + FUNCTION(slimbus1), + FUNCTION(slimbus2), + FUNCTION(spkr_i2s), + FUNCTION(ssbi1), + FUNCTION(ssbi2), + FUNCTION(ssbi_ext_gps), + FUNCTION(ssbi_pmic2), + FUNCTION(ssbi_qpa1), + FUNCTION(ssbi_ts), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(ts_eoc), + FUNCTION(usb_fs1), + FUNCTION(usb_fs1_oe), + FUNCTION(usb_fs1_oe_n), + FUNCTION(usb_fs2), + FUNCTION(usb_fs2_oe), + FUNCTION(usb_fs2_oe_n), + FUNCTION(vfe_camif_timer1_a), + FUNCTION(vfe_camif_timer1_b), + FUNCTION(vfe_camif_timer2), + FUNCTION(vfe_camif_timer3_a), + FUNCTION(vfe_camif_timer3_b), + FUNCTION(vfe_camif_timer4_a), + FUNCTION(vfe_camif_timer4_b), + FUNCTION(vfe_camif_timer4_c), + FUNCTION(vfe_camif_timer5_a), + FUNCTION(vfe_camif_timer5_b), + FUNCTION(vfe_camif_timer6_a), + FUNCTION(vfe_camif_timer6_b), + FUNCTION(vfe_camif_timer6_c), + FUNCTION(vfe_camif_timer7_a), + FUNCTION(vfe_camif_timer7_b), + FUNCTION(vfe_camif_timer7_c), + FUNCTION(wlan), +}; + +static const struct msm_pingroup msm8960_groups[] = { + PINGROUP(0, mdp_vsync, vfe_camif_timer6_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(1, mdp_vsync, vfe_camif_timer7_b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(2, vfe_camif_timer1_a, gp_mn, NA, cam_mclk2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(3, vfe_camif_timer2, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(4, vfe_camif_timer3_a, cam_mclk1, gp_clk_1a, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(5, cam_mclk0, pmb_ext_ctrl, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(6, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(7, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(8, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(9, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(10, gsbi2, ssbi_ts, NA, vfe_camif_timer4_c, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(11, gsbi2, ts_eoc, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(12, gsbi2, rpm_wdog, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, gsbi3, gsbi1_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, gsbi3, gsbi1_spi_cs2a_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, gsbi3, gsbi1_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(17, gsbi3, gsbi1_spi_cs2b_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(18, gsbi4, gsbi11_spi_cs1b_n, NA, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer6_c, NA, NA, NA, NA, NA), + PINGROUP(19, gsbi4, gsbi11_spi_cs2b_n, NA, mdp_vsync, NA, gsbi4_3d_cam_i2c_l, vfe_camif_timer7_c, NA, NA, NA, NA), + PINGROUP(20, gsbi4, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, gsbi4, pmb_clk, gsbi4_3d_cam_i2c_r, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), + PINGROUP(23, gsbi5, ssbi_ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_l, NA), + PINGROUP(24, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), + PINGROUP(25, gsbi5, ext_gps, NA, NA, NA, NA, NA, NA, NA, gsbi5_3d_cam_i2c_r, NA), + PINGROUP(26, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(27, fm, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(28, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, bt, gsbi6, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(30, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(31, gsbi7, usb_fs1_oe, usb_fs1_oe_n, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, gsbi7, usb_fs1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, gsbi8, usb_fs2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, gsbi8, usb_fs2_oe, usb_fs2_oe_n, gsbi11_spi_cs1a_n, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, gsbi8, gps_pps_out, gps_pps_in, gsbi11_spi_cs2a_n, gp_clk_2b, NA, NA, NA, NA, NA, NA), + PINGROUP(38, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer1_b, NA), + PINGROUP(39, gsbi11, gp_pdm_0b, NA, NA, NA, NA, NA, NA, NA, NA, vfe_camif_timer5_b), + PINGROUP(40, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(41, gsbi11, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(42, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(43, gsbi12, slimbus2, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(44, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(45, gsbi12, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, mi2s, slimbus1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, mi2s, gp_clk_2a, gsbi2_spi_cs1_n, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, mi2s, gp_pdm_2b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, codec_mic_i2s, gsbi2_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, codec_mic_i2s, gp_pdm_0a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, slimbus1, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, codec_spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, audio_pcm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, audio_pcm, gp_pdm_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, audio_pcm, vfe_camif_timer4_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, audio_pcm, vfe_camif_timer5_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, spkr_i2s, vfe_camif_timer7_a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, spkr_i2s, gsbi2_spi_cs2_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, spkr_i2s, gp_pdm_2a, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, mic_i2s, gsbi10, vfe_camif_timer6_a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, mic_i2s, gsbi10, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, tsif1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, tsif1, gsbi11_spi_cs3_n, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, tsif2, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, tsif1, sdc5, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, bt, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, wlan, sdc4, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, wlan, sdc4, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, sdc2, gsbi9, gp_pdm_1a, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, sdc2, gsbi9, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, sdc2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, hdmi_cec, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, hdmi_ddc_clock, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, hdmi_ddc_data, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, hdmi_hot_plug_detect, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, pmb_clk, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(117, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(118, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(119, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(120, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(121, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(122, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(123, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(124, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(125, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(126, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(127, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, ssbi_qpa1, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(137, gps_blanking, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(142, ssbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, ssbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(145, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(146, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(147, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(148, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(149, ssbi_pmic2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(150, hsic, NA, vfe_camif_timer4_b, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(151, hsic, NA, vfe_camif_timer3_b, NA, NA, NA, NA, NA, NA, NA, NA), + + SDC_PINGROUP(sdc1_clk, 0x20a0, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x20a0, 11, 3), + SDC_PINGROUP(sdc1_data, 0x20a0, 9, 0), + + SDC_PINGROUP(sdc3_clk, 0x20a4, 14, 6), + SDC_PINGROUP(sdc3_cmd, 0x20a4, 11, 3), + SDC_PINGROUP(sdc3_data, 0x20a4, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 152 + +static const struct msm_pinctrl_soc_data msm8960_pinctrl = { + .pins = msm8960_pins, + .npins = ARRAY_SIZE(msm8960_pins), + .functions = msm8960_functions, + .nfunctions = ARRAY_SIZE(msm8960_functions), + .groups = msm8960_groups, + .ngroups = ARRAY_SIZE(msm8960_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8960_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8960_pinctrl); +} + +static const struct of_device_id msm8960_pinctrl_of_match[] = { + { .compatible = "qcom,msm8960-pinctrl", }, + { }, +}; + +static struct platform_driver msm8960_pinctrl_driver = { + .driver = { + .name = "msm8960-pinctrl", + .owner = THIS_MODULE, + .of_match_table = msm8960_pinctrl_of_match, + }, + .probe = msm8960_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8960_pinctrl_init(void) +{ + return platform_driver_register(&msm8960_pinctrl_driver); +} +arch_initcall(msm8960_pinctrl_init); + +static void __exit msm8960_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8960_pinctrl_driver); +} +module_exit(msm8960_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm MSM8960 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8960_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c new file mode 100644 index 000000000000..418306911a6f --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -0,0 +1,1040 @@ +/* + * Copyright (c) 2013, Sony Mobile Communications AB. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8x74_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + + PINCTRL_PIN(146, "SDC1_CLK"), + PINCTRL_PIN(147, "SDC1_CMD"), + PINCTRL_PIN(148, "SDC1_DATA"), + PINCTRL_PIN(149, "SDC2_CLK"), + PINCTRL_PIN(150, "SDC2_CMD"), + PINCTRL_PIN(151, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); + +static const unsigned int sdc1_clk_pins[] = { 146 }; +static const unsigned int sdc1_cmd_pins[] = { 147 }; +static const unsigned int sdc1_data_pins[] = { 148 }; +static const unsigned int sdc2_clk_pins[] = { 149 }; +static const unsigned int sdc2_cmd_pins[] = { 150 }; +static const unsigned int sdc2_data_pins[] = { 151 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_NA, /* gpio mode */ \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +/* + * TODO: Add the rest of the possible functions and fill out + * the pingroup table below. + */ +enum msm8x74_functions { + MSM_MUX_cci_i2c0, + MSM_MUX_cci_i2c1, + MSM_MUX_blsp_i2c1, + MSM_MUX_blsp_i2c2, + MSM_MUX_blsp_i2c3, + MSM_MUX_blsp_i2c4, + MSM_MUX_blsp_i2c5, + MSM_MUX_blsp_i2c6, + MSM_MUX_blsp_i2c7, + MSM_MUX_blsp_i2c8, + MSM_MUX_blsp_i2c9, + MSM_MUX_blsp_i2c10, + MSM_MUX_blsp_i2c11, + MSM_MUX_blsp_i2c12, + MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi1_cs1, + MSM_MUX_blsp_spi1_cs2, + MSM_MUX_blsp_spi1_cs3, + MSM_MUX_blsp_spi2, + MSM_MUX_blsp_spi2_cs1, + MSM_MUX_blsp_spi2_cs2, + MSM_MUX_blsp_spi2_cs3, + MSM_MUX_blsp_spi3, + MSM_MUX_blsp_spi4, + MSM_MUX_blsp_spi5, + MSM_MUX_blsp_spi6, + MSM_MUX_blsp_spi7, + MSM_MUX_blsp_spi8, + MSM_MUX_blsp_spi9, + MSM_MUX_blsp_spi10, + MSM_MUX_blsp_spi10_cs1, + MSM_MUX_blsp_spi10_cs2, + MSM_MUX_blsp_spi10_cs3, + MSM_MUX_blsp_spi11, + MSM_MUX_blsp_spi12, + MSM_MUX_blsp_uart1, + MSM_MUX_blsp_uart2, + MSM_MUX_blsp_uart3, + MSM_MUX_blsp_uart4, + MSM_MUX_blsp_uart5, + MSM_MUX_blsp_uart6, + MSM_MUX_blsp_uart7, + MSM_MUX_blsp_uart8, + MSM_MUX_blsp_uart9, + MSM_MUX_blsp_uart10, + MSM_MUX_blsp_uart11, + MSM_MUX_blsp_uart12, + MSM_MUX_blsp_uim1, + MSM_MUX_blsp_uim2, + MSM_MUX_blsp_uim3, + MSM_MUX_blsp_uim4, + MSM_MUX_blsp_uim5, + MSM_MUX_blsp_uim6, + MSM_MUX_blsp_uim7, + MSM_MUX_blsp_uim8, + MSM_MUX_blsp_uim9, + MSM_MUX_blsp_uim10, + MSM_MUX_blsp_uim11, + MSM_MUX_blsp_uim12, + MSM_MUX_uim1, + MSM_MUX_uim2, + MSM_MUX_uim_batt_alarm, + MSM_MUX_sdc3, + MSM_MUX_sdc4, + MSM_MUX_gcc_gp_clk1, + MSM_MUX_gcc_gp_clk2, + MSM_MUX_gcc_gp_clk3, + MSM_MUX_qua_mi2s, + MSM_MUX_pri_mi2s, + MSM_MUX_spkr_mi2s, + MSM_MUX_ter_mi2s, + MSM_MUX_sec_mi2s, + MSM_MUX_hdmi_cec, + MSM_MUX_hdmi_ddc, + MSM_MUX_hdmi_hpd, + MSM_MUX_edp_hpd, + MSM_MUX_mdp_vsync, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_cam_mclk2, + MSM_MUX_cam_mclk3, + MSM_MUX_cci_timer0, + MSM_MUX_cci_timer1, + MSM_MUX_cci_timer2, + MSM_MUX_cci_timer3, + MSM_MUX_cci_timer4, + MSM_MUX_cci_async_in0, + MSM_MUX_cci_async_in1, + MSM_MUX_cci_async_in2, + MSM_MUX_gp_pdm0, + MSM_MUX_gp_pdm1, + MSM_MUX_gp_pdm2, + MSM_MUX_gp0_clk, + MSM_MUX_gp1_clk, + MSM_MUX_gp_mn, + MSM_MUX_tsif1, + MSM_MUX_tsif2, + MSM_MUX_hsic, + MSM_MUX_grfc, + MSM_MUX_audio_ref_clk, + MSM_MUX_bt, + MSM_MUX_fm, + MSM_MUX_wlan, + MSM_MUX_slimbus, + MSM_MUX_NA, +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; +static const char * const blsp_spi1_cs1_groups[] = { "gpio8" }; +static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" }; +static const char * const blsp_spi1_cs3_groups[] = { "gpio10" }; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; +static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" }; +static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" }; +static const char * const blsp_spi2_cs3_groups[] = { "gpio66" }; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" }; +static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" }; + +static const char * const blsp_uart4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; +static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" }; +static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" }; +static const char * const blsp_spi4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22" +}; + +static const char * const blsp_uart5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; +static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" }; +static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" }; +static const char * const blsp_spi5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26" +}; + +static const char * const blsp_uart6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; +static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" }; +static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" }; +static const char * const blsp_spi6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30" +}; + +static const char * const blsp_uart7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; +static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" }; +static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" }; +static const char * const blsp_spi7_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const char * const blsp_uart8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; +static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" }; +static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" }; +static const char * const blsp_spi8_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48" +}; + +static const char * const blsp_uart9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" }; +static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" }; +static const char * const blsp_spi9_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const blsp_uart10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" }; +static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" }; +static const char * const blsp_spi10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56" +}; +static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" }; +static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" }; +static const char * const blsp_spi10_cs3_groups[] = { "gpio90" }; + +static const char * const blsp_uart11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; +static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" }; +static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" }; +static const char * const blsp_spi11_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84" +}; + +static const char * const blsp_uart12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; +static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" }; +static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" }; +static const char * const blsp_spi12_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88" +}; + +static const char * const uim1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100" +}; + +static const char * const uim2_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52" +}; + +static const char * const uim_batt_alarm_groups[] = { "gpio101" }; + +static const char * const sdc3_groups[] = { + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const sdc4_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const gp0_clk_groups[] = { "gpio26" }; +static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" }; +static const char * const gp_mn_groups[] = { "gpio29" }; +static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" }; +static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" }; +static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" }; + +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; + +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68" +}; + +static const char * const spkr_mi2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72" +}; + +static const char * const ter_mi2s_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio77" +}; + +static const char * const sec_mi2s_groups[] = { + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82" +}; + +static const char * const hdmi_cec_groups[] = { "gpio31" }; +static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" }; +static const char * const hdmi_hpd_groups[] = { "gpio34" }; +static const char * const edp_hpd_groups[] = { "gpio102" }; + +static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" }; +static const char * const cam_mclk0_groups[] = { "gpio15" }; +static const char * const cam_mclk1_groups[] = { "gpio16" }; +static const char * const cam_mclk2_groups[] = { "gpio17" }; +static const char * const cam_mclk3_groups[] = { "gpio18" }; + +static const char * const cci_timer0_groups[] = { "gpio23" }; +static const char * const cci_timer1_groups[] = { "gpio24" }; +static const char * const cci_timer2_groups[] = { "gpio25" }; +static const char * const cci_timer3_groups[] = { "gpio26" }; +static const char * const cci_timer4_groups[] = { "gpio27" }; +static const char * const cci_async_in0_groups[] = { "gpio28" }; +static const char * const cci_async_in1_groups[] = { "gpio26" }; +static const char * const cci_async_in2_groups[] = { "gpio27" }; + +static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" }; +static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" }; +static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" }; + +static const char * const tsif1_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92" +}; + +static const char * const tsif2_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96" +}; + +static const char * const hsic_groups[] = { "gpio144", "gpio145" }; +static const char * const grfc_groups[] = { + "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", + "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", + "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", + "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", + "gpio128", "gpio136", "gpio137", "gpio141", "gpio143" +}; + +static const char * const audio_ref_clk_groups[] = { "gpio69" }; + +static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" }; + +static const char * const fm_groups[] = { "gpio41", "gpio42" }; + +static const char * const wlan_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40" +}; + +static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; + +static const struct msm_function msm8x74_functions[] = { + FUNCTION(cci_i2c0), + FUNCTION(cci_i2c1), + FUNCTION(uim1), + FUNCTION(uim2), + FUNCTION(uim_batt_alarm), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim4), + FUNCTION(blsp_uim5), + FUNCTION(blsp_uim6), + FUNCTION(blsp_uim7), + FUNCTION(blsp_uim8), + FUNCTION(blsp_uim9), + FUNCTION(blsp_uim10), + FUNCTION(blsp_uim11), + FUNCTION(blsp_uim12), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c4), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_i2c6), + FUNCTION(blsp_i2c7), + FUNCTION(blsp_i2c8), + FUNCTION(blsp_i2c9), + FUNCTION(blsp_i2c10), + FUNCTION(blsp_i2c11), + FUNCTION(blsp_i2c12), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi1_cs1), + FUNCTION(blsp_spi1_cs2), + FUNCTION(blsp_spi1_cs3), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi2_cs1), + FUNCTION(blsp_spi2_cs2), + FUNCTION(blsp_spi2_cs3), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi4), + FUNCTION(blsp_spi5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_spi7), + FUNCTION(blsp_spi8), + FUNCTION(blsp_spi9), + FUNCTION(blsp_spi10), + FUNCTION(blsp_spi10_cs1), + FUNCTION(blsp_spi10_cs2), + FUNCTION(blsp_spi10_cs3), + FUNCTION(blsp_spi11), + FUNCTION(blsp_spi12), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart4), + FUNCTION(blsp_uart5), + FUNCTION(blsp_uart6), + FUNCTION(blsp_uart7), + FUNCTION(blsp_uart8), + FUNCTION(blsp_uart9), + FUNCTION(blsp_uart10), + FUNCTION(blsp_uart11), + FUNCTION(blsp_uart12), + FUNCTION(sdc3), + FUNCTION(sdc4), + FUNCTION(gcc_gp_clk1), + FUNCTION(gcc_gp_clk2), + FUNCTION(gcc_gp_clk3), + FUNCTION(qua_mi2s), + FUNCTION(pri_mi2s), + FUNCTION(spkr_mi2s), + FUNCTION(ter_mi2s), + FUNCTION(sec_mi2s), + FUNCTION(mdp_vsync), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(cam_mclk2), + FUNCTION(cam_mclk3), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cci_async_in0), + FUNCTION(cci_async_in1), + FUNCTION(cci_async_in2), + FUNCTION(hdmi_cec), + FUNCTION(hdmi_ddc), + FUNCTION(hdmi_hpd), + FUNCTION(edp_hpd), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gp0_clk), + FUNCTION(gp1_clk), + FUNCTION(gp_mn), + FUNCTION(tsif1), + FUNCTION(tsif2), + FUNCTION(hsic), + FUNCTION(grfc), + FUNCTION(audio_ref_clk), + FUNCTION(bt), + FUNCTION(fm), + FUNCTION(wlan), + FUNCTION(slimbus), +}; + +static const struct msm_pingroup msm8x74_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA), + PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA), + PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA), + PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA), + PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA), + PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA), + PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA), + PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA), + PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA), + PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA), + PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA), + PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA), + PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA), + PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA), + PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA), + PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA), + PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA), + PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA), + PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA), + PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA), + PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA), + PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA), + PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA), + PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA), + PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA), + PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA), + PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA), + PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA), + PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA), + PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA), + PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA), + PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA), + PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA), + PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA), + PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA), + PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA), + PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA), + PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA), + PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA), + PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA), + PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA), + PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA), + PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA), + PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA), + PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA), + PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA), + PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA), + PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA), + PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA), + PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA), + PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA), + PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA), + PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA), + PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(129, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(130, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(131, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(132, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(133, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(134, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(135, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(138, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(139, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(140, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(142, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA), + PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA), + PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 146 + +static const struct msm_pinctrl_soc_data msm8x74_pinctrl = { + .pins = msm8x74_pins, + .npins = ARRAY_SIZE(msm8x74_pins), + .functions = msm8x74_functions, + .nfunctions = ARRAY_SIZE(msm8x74_functions), + .groups = msm8x74_groups, + .ngroups = ARRAY_SIZE(msm8x74_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8x74_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8x74_pinctrl); +} + +static const struct of_device_id msm8x74_pinctrl_of_match[] = { + { .compatible = "qcom,msm8974-pinctrl", }, + { }, +}; + +static struct platform_driver msm8x74_pinctrl_driver = { + .driver = { + .name = "msm8x74-pinctrl", + .owner = THIS_MODULE, + .of_match_table = msm8x74_pinctrl_of_match, + }, + .probe = msm8x74_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8x74_pinctrl_init(void) +{ + return platform_driver_register(&msm8x74_pinctrl_driver); +} +arch_initcall(msm8x74_pinctrl_init); + +static void __exit msm8x74_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8x74_pinctrl_driver); +} +module_exit(msm8x74_pinctrl_exit); + +MODULE_AUTHOR("Bjorn Andersson "); +MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match); + -- cgit v1.2.1