From caf636c760b33c72ebf018ff03c1b0d79ea6656a Mon Sep 17 00:00:00 2001 From: Michael Chan Date: Wed, 22 Mar 2006 01:05:31 -0800 Subject: [TG3]: Fix SRAM access during tg3_init_one() 5700 and 5701 will not return correct SRAM data when the chip is in D3hot power state. tg3_get_eeprom_hw_cfg() must first put the device in D0 before reading SRAM. Thanks to Thomas Chenault at Dell for noticing this problem. Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/tg3.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers/net/tg3.c') diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index e03d1ae50c3e..cb687fcaae1f 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -9436,12 +9436,18 @@ static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp) return NULL; } -/* Since this function may be called in D3-hot power state during - * tg3_init_one(), only config cycles are allowed. - */ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) { u32 val; + u16 pmcsr; + + /* On some early chips the SRAM cannot be accessed in D3hot state, + * so need make sure we're in D0. + */ + pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); + pmcsr &= ~PCI_PM_CTRL_STATE_MASK; + pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); + msleep(1); /* Make sure register accesses (indirect or otherwise) * will function correctly. -- cgit v1.2.1