From c03ff9e8fa5fc0186158b99a89f613325ff352cf Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 1 Jul 2013 10:54:27 +1000 Subject: drm/nvc0-/gr: pull out a group of separately context-switched gpc regs Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/core/engine/graph/ctxnvc0.c | 47 ++++++++++++++-------- .../gpu/drm/nouveau/core/engine/graph/ctxnvc1.c | 9 ++++- .../gpu/drm/nouveau/core/engine/graph/ctxnvd9.c | 33 ++++----------- .../gpu/drm/nouveau/core/engine/graph/ctxnve4.c | 36 +++++------------ .../gpu/drm/nouveau/core/engine/graph/ctxnvf0.c | 33 ++++----------- drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h | 6 ++- 6 files changed, 68 insertions(+), 96 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c index a09ee65b0f99..087295db9707 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c @@ -749,7 +749,7 @@ nvc0_grctx_init_rop[] = { }; struct nvc0_graph_init -nvc0_grctx_init_gpc[] = { +nvc0_grctx_init_gpc_0[] = { { 0x418380, 1, 0x04, 0x00000016 }, { 0x418400, 1, 0x04, 0x38004e00 }, { 0x418404, 1, 0x04, 0x71e0ffff }, @@ -779,6 +779,26 @@ nvc0_grctx_init_gpc[] = { { 0x418924, 1, 0x04, 0x00000000 }, { 0x418928, 1, 0x04, 0x00ffff00 }, { 0x41892c, 1, 0x04, 0x0000ff00 }, + { 0x418b00, 1, 0x04, 0x00000000 }, + { 0x418b08, 1, 0x04, 0x0a418820 }, + { 0x418b0c, 1, 0x04, 0x062080e6 }, + { 0x418b10, 1, 0x04, 0x020398a4 }, + { 0x418b14, 1, 0x04, 0x0e629062 }, + { 0x418b18, 1, 0x04, 0x0a418820 }, + { 0x418b1c, 1, 0x04, 0x000000e6 }, + { 0x418bb8, 1, 0x04, 0x00000103 }, + { 0x418c08, 1, 0x04, 0x00000001 }, + { 0x418c10, 8, 0x04, 0x00000000 }, + { 0x418c80, 1, 0x04, 0x20200004 }, + { 0x418c8c, 1, 0x04, 0x00000001 }, + { 0x419000, 1, 0x04, 0x00000780 }, + { 0x419004, 2, 0x04, 0x00000000 }, + { 0x419014, 1, 0x04, 0x00000004 }, + {} +}; + +struct nvc0_graph_init +nvc0_grctx_init_gpc_1[] = { { 0x418a00, 3, 0x04, 0x00000000 }, { 0x418a0c, 1, 0x04, 0x00010000 }, { 0x418a10, 3, 0x04, 0x00000000 }, @@ -803,21 +823,6 @@ nvc0_grctx_init_gpc[] = { { 0x418ae0, 3, 0x04, 0x00000000 }, { 0x418aec, 1, 0x04, 0x00010000 }, { 0x418af0, 3, 0x04, 0x00000000 }, - { 0x418b00, 1, 0x04, 0x00000000 }, - { 0x418b08, 1, 0x04, 0x0a418820 }, - { 0x418b0c, 1, 0x04, 0x062080e6 }, - { 0x418b10, 1, 0x04, 0x020398a4 }, - { 0x418b14, 1, 0x04, 0x0e629062 }, - { 0x418b18, 1, 0x04, 0x0a418820 }, - { 0x418b1c, 1, 0x04, 0x000000e6 }, - { 0x418bb8, 1, 0x04, 0x00000103 }, - { 0x418c08, 1, 0x04, 0x00000001 }, - { 0x418c10, 8, 0x04, 0x00000000 }, - { 0x418c80, 1, 0x04, 0x20200004 }, - { 0x418c8c, 1, 0x04, 0x00000001 }, - { 0x419000, 1, 0x04, 0x00000780 }, - { 0x419004, 2, 0x04, 0x00000000 }, - { 0x419014, 1, 0x04, 0x00000004 }, {} }; @@ -1044,7 +1049,8 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) for (i = 0; oclass->mmio[i]; i++) nvc0_graph_mmio(priv, oclass->mmio[i]); - nvc0_graph_mmio(priv, oclass->gpc); + for (i = 0; oclass->gpc[i]; i++) + nvc0_graph_mmio(priv, oclass->gpc[i]); nvc0_graph_mmio(priv, oclass->tpc); nv_wr32(priv, 0x404154, 0x00000000); @@ -1188,6 +1194,13 @@ nvc0_grctx_init_mmio[] = { NULL }; +struct nvc0_graph_init * +nvc0_grctx_init_gpc[] = { + nvc0_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + NULL +}; + struct nvc0_graph_init nvc0_grctx_init_mthd_magic[] = { { 0x3410, 1, 0x04, 0x00000000 }, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c index 75047154b74d..09e17f9eb508 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c @@ -601,7 +601,7 @@ nvc1_grctx_init_rop[] = { }; static struct nvc0_graph_init -nvc1_grctx_init_gpc[] = { +nvc1_grctx_init_gpc_0[] = { { 0x418380, 1, 0x04, 0x00000016 }, { 0x418400, 1, 0x04, 0x38004e00 }, { 0x418404, 1, 0x04, 0x71e0ffff }, @@ -772,6 +772,13 @@ nvc1_grctx_init_mmio[] = { NULL }; +struct nvc0_graph_init * +nvc1_grctx_init_gpc[] = { + nvc1_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + NULL +}; + static struct nvc0_graph_mthd nvc1_grctx_init_mthd[] = { { 0x9097, nvc1_grctx_init_9097, }, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c index 4be543e411cd..e4f1a8c6f68c 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c @@ -358,7 +358,7 @@ nvd9_grctx_init_rop[] = { }; static struct nvc0_graph_init -nvd9_grctx_init_gpc[] = { +nvd9_grctx_init_gpc_0[] = { { 0x418380, 1, 0x04, 0x00000016 }, { 0x418400, 1, 0x04, 0x38004e00 }, { 0x418404, 1, 0x04, 0x71e0ffff }, @@ -385,30 +385,6 @@ nvd9_grctx_init_gpc[] = { { 0x418924, 1, 0x04, 0x00000000 }, { 0x418928, 1, 0x04, 0x00ffff00 }, { 0x41892c, 1, 0x04, 0x0000ff00 }, - { 0x418a00, 3, 0x04, 0x00000000 }, - { 0x418a0c, 1, 0x04, 0x00010000 }, - { 0x418a10, 3, 0x04, 0x00000000 }, - { 0x418a20, 3, 0x04, 0x00000000 }, - { 0x418a2c, 1, 0x04, 0x00010000 }, - { 0x418a30, 3, 0x04, 0x00000000 }, - { 0x418a40, 3, 0x04, 0x00000000 }, - { 0x418a4c, 1, 0x04, 0x00010000 }, - { 0x418a50, 3, 0x04, 0x00000000 }, - { 0x418a60, 3, 0x04, 0x00000000 }, - { 0x418a6c, 1, 0x04, 0x00010000 }, - { 0x418a70, 3, 0x04, 0x00000000 }, - { 0x418a80, 3, 0x04, 0x00000000 }, - { 0x418a8c, 1, 0x04, 0x00010000 }, - { 0x418a90, 3, 0x04, 0x00000000 }, - { 0x418aa0, 3, 0x04, 0x00000000 }, - { 0x418aac, 1, 0x04, 0x00010000 }, - { 0x418ab0, 3, 0x04, 0x00000000 }, - { 0x418ac0, 3, 0x04, 0x00000000 }, - { 0x418acc, 1, 0x04, 0x00010000 }, - { 0x418ad0, 3, 0x04, 0x00000000 }, - { 0x418ae0, 3, 0x04, 0x00000000 }, - { 0x418aec, 1, 0x04, 0x00010000 }, - { 0x418af0, 3, 0x04, 0x00000000 }, { 0x418b00, 1, 0x04, 0x00000006 }, { 0x418b08, 1, 0x04, 0x0a418820 }, { 0x418b0c, 1, 0x04, 0x062080e6 }, @@ -492,6 +468,13 @@ nvd9_grctx_init_mmio[] = { nvd9_grctx_init_rop, }; +struct nvc0_graph_init * +nvd9_grctx_init_gpc[] = { + nvd9_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + NULL +}; + struct nvc0_graph_init nvd9_grctx_init_mthd_magic[] = { { 0x3410, 1, 0x04, 0x80002006 }, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c index 4f6041490986..1c68fb11b889 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c @@ -699,7 +699,7 @@ nve4_grctx_init_rop[] = { }; static struct nvc0_graph_init -nve4_grctx_init_gpc[] = { +nve4_grctx_init_gpc_0[] = { { 0x418380, 1, 0x04, 0x00000016 }, { 0x418400, 1, 0x04, 0x38004e00 }, { 0x418404, 1, 0x04, 0x71e0ffff }, @@ -726,30 +726,6 @@ nve4_grctx_init_gpc[] = { { 0x418924, 1, 0x04, 0x00000000 }, { 0x418928, 1, 0x04, 0x00ffff00 }, { 0x41892c, 1, 0x04, 0x0000ff00 }, - { 0x418a00, 3, 0x04, 0x00000000 }, - { 0x418a0c, 1, 0x04, 0x00010000 }, - { 0x418a10, 3, 0x04, 0x00000000 }, - { 0x418a20, 3, 0x04, 0x00000000 }, - { 0x418a2c, 1, 0x04, 0x00010000 }, - { 0x418a30, 3, 0x04, 0x00000000 }, - { 0x418a40, 3, 0x04, 0x00000000 }, - { 0x418a4c, 1, 0x04, 0x00010000 }, - { 0x418a50, 3, 0x04, 0x00000000 }, - { 0x418a60, 3, 0x04, 0x00000000 }, - { 0x418a6c, 1, 0x04, 0x00010000 }, - { 0x418a70, 3, 0x04, 0x00000000 }, - { 0x418a80, 3, 0x04, 0x00000000 }, - { 0x418a8c, 1, 0x04, 0x00010000 }, - { 0x418a90, 3, 0x04, 0x00000000 }, - { 0x418aa0, 3, 0x04, 0x00000000 }, - { 0x418aac, 1, 0x04, 0x00010000 }, - { 0x418ab0, 3, 0x04, 0x00000000 }, - { 0x418ac0, 3, 0x04, 0x00000000 }, - { 0x418acc, 1, 0x04, 0x00010000 }, - { 0x418ad0, 3, 0x04, 0x00000000 }, - { 0x418ae0, 3, 0x04, 0x00000000 }, - { 0x418aec, 1, 0x04, 0x00010000 }, - { 0x418af0, 3, 0x04, 0x00000000 }, { 0x418b00, 1, 0x04, 0x00000006 }, { 0x418b08, 1, 0x04, 0x0a418820 }, { 0x418b0c, 1, 0x04, 0x062080e6 }, @@ -937,7 +913,8 @@ nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) for (i = 0; oclass->mmio[i]; i++) nvc0_graph_mmio(priv, oclass->mmio[i]); - nvc0_graph_mmio(priv, oclass->gpc); + for (i = 0; oclass->gpc[i]; i++) + nvc0_graph_mmio(priv, oclass->gpc[i]); nvc0_graph_mmio(priv, oclass->tpc); nv_wr32(priv, 0x404154, 0x00000000); @@ -1004,6 +981,13 @@ nve4_grctx_init_mmio[] = { NULL }; +struct nvc0_graph_init * +nve4_grctx_init_gpc[] = { + nve4_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + NULL +}; + static struct nvc0_graph_mthd nve4_grctx_init_mthd[] = { { 0xa097, nve4_grctx_init_a097, }, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c index 8aae1f3415f5..a692389cd9cf 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c @@ -104,7 +104,7 @@ nvf0_grctx_init_unk88xx[] = { }; static struct nvc0_graph_init -nvf0_grctx_init_gpc[] = { +nvf0_grctx_init_gpc_0[] = { { 0x418380, 1, 0x04, 0x00000016 }, { 0x418400, 1, 0x04, 0x38004e00 }, { 0x418404, 1, 0x04, 0x71e0ffff }, @@ -133,30 +133,6 @@ nvf0_grctx_init_gpc[] = { { 0x418924, 1, 0x04, 0x00000000 }, { 0x418928, 1, 0x04, 0x00ffff00 }, { 0x41892c, 1, 0x04, 0x0000ff00 }, - { 0x418a00, 3, 0x04, 0x00000000 }, - { 0x418a0c, 1, 0x04, 0x00010000 }, - { 0x418a10, 3, 0x04, 0x00000000 }, - { 0x418a20, 3, 0x04, 0x00000000 }, - { 0x418a2c, 1, 0x04, 0x00010000 }, - { 0x418a30, 3, 0x04, 0x00000000 }, - { 0x418a40, 3, 0x04, 0x00000000 }, - { 0x418a4c, 1, 0x04, 0x00010000 }, - { 0x418a50, 3, 0x04, 0x00000000 }, - { 0x418a60, 3, 0x04, 0x00000000 }, - { 0x418a6c, 1, 0x04, 0x00010000 }, - { 0x418a70, 3, 0x04, 0x00000000 }, - { 0x418a80, 3, 0x04, 0x00000000 }, - { 0x418a8c, 1, 0x04, 0x00010000 }, - { 0x418a90, 3, 0x04, 0x00000000 }, - { 0x418aa0, 3, 0x04, 0x00000000 }, - { 0x418aac, 1, 0x04, 0x00010000 }, - { 0x418ab0, 3, 0x04, 0x00000000 }, - { 0x418ac0, 3, 0x04, 0x00000000 }, - { 0x418acc, 1, 0x04, 0x00010000 }, - { 0x418ad0, 3, 0x04, 0x00000000 }, - { 0x418ae0, 3, 0x04, 0x00000000 }, - { 0x418aec, 1, 0x04, 0x00010000 }, - { 0x418af0, 3, 0x04, 0x00000000 }, { 0x418b00, 1, 0x04, 0x00000006 }, { 0x418b08, 1, 0x04, 0x0a418820 }, { 0x418b0c, 1, 0x04, 0x062080e6 }, @@ -259,6 +235,13 @@ nvf0_grctx_init_mmio[] = { NULL }; +struct nvc0_graph_init * +nvf0_grctx_init_gpc[] = { + nvf0_grctx_init_gpc_0, + nvc0_grctx_init_gpc_1, + NULL +}; + static struct nvc0_graph_mthd nvf0_grctx_init_mthd[] = { { 0xa197, nvc1_grctx_init_9097, }, diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h index f7d0df7c84ad..52d70ba5ffb5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h @@ -152,7 +152,7 @@ struct nvc0_grctx_oclass { void (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *); /* mmio context data */ struct nvc0_graph_init **mmio; - struct nvc0_graph_init *gpc; + struct nvc0_graph_init **gpc; struct nvc0_graph_init *tpc; /* indirect context data, generated with icmds/mthds */ struct nvc0_graph_init *icmd; @@ -223,7 +223,9 @@ extern struct nvc0_graph_init nvc0_grctx_init_unk60xx[]; extern struct nvc0_graph_init nvc0_grctx_init_unk64xx[]; extern struct nvc0_graph_init nvc0_grctx_init_unk78xx[]; extern struct nvc0_graph_init nvc0_grctx_init_unk80xx[]; -extern struct nvc0_graph_init nvc0_grctx_init_gpc[]; +extern struct nvc0_graph_init nvc0_grctx_init_gpc_0[]; +extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[]; +extern struct nvc0_graph_init *nvc0_grctx_init_gpc[]; extern struct nvc0_graph_init nvc0_grctx_init_tpc[]; extern struct nvc0_graph_init nvc0_grctx_init_icmd[]; extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; // -- cgit v1.2.1