From f266f04d33e5265e2f61ffc9d2b2f97214804995 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 28 Aug 2014 10:59:05 -0400 Subject: drm/radeon: add RADEON_GEM_NO_CPU_ACCESS BO creation flag (v4) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allows pinning of buffers in the non-CPU visible portion of vram. v2: incorporate Michel's comments. v3: rebase on Michel's patch v4: rebase on Michel's v2 patch Signed-off-by: Alex Deucher Reviewed-by: Michel Dänzer --- drivers/gpu/drm/radeon/radeon_object.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/radeon/radeon_object.c') diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 3dbbd65336d5..8abee5fa93bd 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -313,6 +313,7 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, for (i = 0; i < bo->placement.num_placement; i++) { /* force to pin into visible video ram */ if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && + !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) bo->placements[i].lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; -- cgit v1.2.3