From 276836d46e535c8ca299a1ea8302879dbdd3e93a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:10 +1000 Subject: drm/nouveau/gr: switch to device pri macros Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 6b9c84f8f12d..719ebfb6e640 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -37,32 +37,34 @@ gm20b_gr_sclass[] = { static void gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; u32 val; /* TODO this needs to be removed once secure boot works */ if (1) { - nv_wr32(gr, 0x100ce4, 0xffffffff); + nvkm_wr32(device, 0x100ce4, 0xffffffff); } /* TODO update once secure boot works */ - val = nv_rd32(gr, 0x100c80); + val = nvkm_rd32(device, 0x100c80); val &= 0xf000087f; - nv_wr32(gr, 0x418880, val); - nv_wr32(gr, 0x418890, 0); - nv_wr32(gr, 0x418894, 0); + nvkm_wr32(device, 0x418880, val); + nvkm_wr32(device, 0x418890, 0); + nvkm_wr32(device, 0x418894, 0); - nv_wr32(gr, 0x4188b0, nv_rd32(gr, 0x100cc4)); - nv_wr32(gr, 0x4188b4, nv_rd32(gr, 0x100cc8)); - nv_wr32(gr, 0x4188b8, nv_rd32(gr, 0x100ccc)); + nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); + nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); + nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); - nv_wr32(gr, 0x4188ac, nv_rd32(gr, 0x100800)); + nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800)); } static void gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) { - nv_wr32(gr, 0x419e44, 0xdffffe); - nv_wr32(gr, 0x419e4c, 0x5); + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_wr32(device, 0x419e44, 0xdffffe); + nvkm_wr32(device, 0x419e4c, 0x5); } struct nvkm_oclass * -- cgit v1.2.1