From 5a2c675c891960f86c025d4ab3d3904364bf4f96 Mon Sep 17 00:00:00 2001 From: Tim Small Date: Thu, 19 Jul 2007 01:49:42 -0700 Subject: drivers/edac: new i82443bxgz MC driver This is a NEW EDAC Memory Controller driver for the 440BX chipset (I82443BXGX) created and submitted by Timm Small Signed-off-by: Tim Small Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/i82443bxgx_edac.c | 400 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 400 insertions(+) create mode 100644 drivers/edac/i82443bxgx_edac.c (limited to 'drivers/edac/i82443bxgx_edac.c') diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c new file mode 100644 index 000000000000..ecf2ba82989c --- /dev/null +++ b/drivers/edac/i82443bxgx_edac.c @@ -0,0 +1,400 @@ +/* + * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel + * module (C) 2006 Tim Small + * + * This file may be distributed under the terms of the GNU General + * Public License. + * + * Written by Tim Small , based on work by Linux + * Networx, Thayne Harbaugh, Dan Hollis and + * others. + * + * 440GX fix by Jason Uhlenkott . + * + * Written with reference to 82443BX Host Bridge Datasheet: + * http://www.intel.com/design/chipsets/440/documentation.htm + * references to this document given in []. + * + * This module doesn't support the 440LX, but it may be possible to + * make it do so (the 440LX's register definitions are different, but + * not completely so - I haven't studied them in enough detail to know + * how easy this would be). + */ + +#include +#include + +#include +#include + +#include + +#include "edac_mc.h" + +#define I82443_REVISION "0.1" + +#define EDAC_MOD_STR "i82443bxgx_edac" + + +/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory + * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory + * rows" "The 82443BX supports multiple-bit error detection and + * single-bit error correction when ECC mode is enabled and + * single/multi-bit error detection when correction is disabled. + * During writes to the DRAM, the 82443BX generates ECC for the data + * on a QWord basis. Partial QWord writes require a read-modify-write + * cycle when ECC is enabled." +*/ + +/* "Additionally, the 82443BX ensures that the data is corrected in + * main memory so that accumulation of errors is prevented. Another + * error within the same QWord would result in a double-bit error + * which is unrecoverable. This is known as hardware scrubbing since + * it requires no software intervention to correct the data in memory." + */ + +/* [Also see page 100 (section 4.3), "DRAM Interface"] + * [Also see page 112 (section 4.6.1.4), ECC] + */ + +#define I82443BXGX_NR_CSROWS 8 +#define I82443BXGX_NR_CHANS 1 +#define I82443BXGX_NR_DIMMS 4 + + + +/* 82443 PCI Device 0 */ +#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI + * config space offset */ +#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if + * row is non-ECC */ +#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */ + +#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */ +#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */ +#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */ +#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */ +#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */ + +#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6 + + +/* 82443 PCI Device 0 */ +#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI + * config space offset, Error Address + * Pointer Register */ +#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */ +#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */ +#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC)*/ + +#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI + * config space offset. */ +#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */ +#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */ + +#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI + * config space offset. */ +#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */ +#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */ +#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */ +#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */ + + +#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI + * config space offset. */ +#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */ +#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */ +#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */ +#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */ + + +#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI + * config space offset. */ + + +/* FIXME - don't poll when ECC disabled? */ + + +struct i82443bxgx_edacmc_error_info { + u32 eap; +}; + + +static void i82443bxgx_edacmc_get_error_info (struct mem_ctl_info *mci, + struct i82443bxgx_edacmc_error_info *info) +{ + struct pci_dev *pdev; + pdev = to_pci_dev(mci->dev); + pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap); + if (info->eap & I82443BXGX_EAP_OFFSET_SBE) + /* Clear error to allow next error to be reported [p.61] */ + pci_write_bits32(pdev, I82443BXGX_EAP, + I82443BXGX_EAP_OFFSET_SBE, + I82443BXGX_EAP_OFFSET_SBE); + + if (info->eap & I82443BXGX_EAP_OFFSET_MBE) + /* Clear error to allow next error to be reported [p.61] */ + pci_write_bits32(pdev, I82443BXGX_EAP, + I82443BXGX_EAP_OFFSET_MBE, + I82443BXGX_EAP_OFFSET_MBE); +} + + +static int i82443bxgx_edacmc_process_error_info (struct mem_ctl_info *mci, + struct i82443bxgx_edacmc_error_info *info, int handle_errors) +{ + int error_found = 0; + u32 eapaddr, page, pageoffset; + + /* bits 30:12 hold the 4kb block in which the error occurred + * [p.61] */ + eapaddr = (info->eap & 0xfffff000); + page = eapaddr >> PAGE_SHIFT; + pageoffset = eapaddr - (page << PAGE_SHIFT); + + if (info->eap & I82443BXGX_EAP_OFFSET_SBE) { + error_found = 1; + if (handle_errors) + edac_mc_handle_ce( + mci, page, pageoffset, + /* 440BX/GX don't make syndrome information available */ + 0, + edac_mc_find_csrow_by_page(mci, page), + 0, /* channel */ + mci->ctl_name); + } + + if (info->eap & I82443BXGX_EAP_OFFSET_MBE) { + error_found = 1; + if (handle_errors) + edac_mc_handle_ue( + mci, page, pageoffset, + edac_mc_find_csrow_by_page(mci, page), + mci->ctl_name); + } + + return error_found; +} + + +static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) +{ + struct i82443bxgx_edacmc_error_info info; + + debugf1("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__); + i82443bxgx_edacmc_get_error_info(mci, &info); + i82443bxgx_edacmc_process_error_info(mci, &info, 1); +} + + +static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, + struct pci_dev *pdev, + enum edac_type edac_mode, + enum mem_type mtype) +{ + struct csrow_info *csrow; + int index; + u8 drbar, dramc; + u32 row_base, row_high_limit, row_high_limit_last; + + pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); + row_high_limit_last = 0; + for (index = 0; index < mci->nr_csrows; index++) { + csrow = &mci->csrows[index]; + pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); + debugf1("MC%d: " __FILE__ ": %s() Row=%d DRB = %#0x\n", + mci->mc_idx, __func__, index, drbar); + row_high_limit = ((u32) drbar << 23); + /* find the DRAM Chip Select Base address and mask */ + debugf1("MC%d: " __FILE__ ": %s() Row=%d, " + "Boundry Address=%#0x, Last = %#0x \n", + mci->mc_idx, __func__, index, row_high_limit, + row_high_limit_last); + + /* 440GX goes to 2GB, represented with a DRB of 0. */ + if (row_high_limit_last && !row_high_limit) + row_high_limit = 1UL << 31; + + /* This row is empty [p.49] */ + if (row_high_limit == row_high_limit_last) + continue; + row_base = row_high_limit_last; + csrow->first_page = row_base >> PAGE_SHIFT; + csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; + csrow->nr_pages = csrow->last_page - csrow->first_page + 1; + /* EAP reports in 4kilobyte granularity [61] */ + csrow->grain = 1 << 12; + csrow->mtype = mtype; + /* I don't think 440BX can tell you device type? FIXME? */ + csrow->dtype = DEV_UNKNOWN; + /* Mode is global to all rows on 440BX */ + csrow->edac_mode = edac_mode; + row_high_limit_last = row_high_limit; + } +} + + +static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) +{ + struct mem_ctl_info *mci; + u8 dramc; + u32 nbxcfg, ecc_mode; + enum mem_type mtype; + enum edac_type edac_mode; + + debugf0("MC: " __FILE__ ": %s()\n", __func__); + + /* Something is really hosed if PCI config space reads from + the MC aren't working. */ + if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg)) + return -EIO; + + mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS); + + if (mci == NULL) + return -ENOMEM; + + debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); + mci->dev = &pdev->dev; + mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; + pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); + switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) { + case I82443BXGX_DRAMC_DRAM_IS_EDO: + mtype = MEM_EDO; + break; + case I82443BXGX_DRAMC_DRAM_IS_SDRAM: + mtype = MEM_SDR; + break; + case I82443BXGX_DRAMC_DRAM_IS_RSDRAM: + mtype = MEM_RDR; + break; + default: + debugf0("Unknown/reserved DRAM type value in DRAMC register!\n"); + mtype = -MEM_UNKNOWN; + } + + if ((mtype == MEM_SDR) || (mtype == MEM_RDR)) + mci->edac_cap = mci->edac_ctl_cap; + else + mci->edac_cap = EDAC_FLAG_NONE; + + mci->scrub_cap = SCRUB_FLAG_HW_SRC; + pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg); + ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) & + (BIT(0) | BIT(1))); + + mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB) + ? SCRUB_HW_SRC + : SCRUB_NONE; + + switch(ecc_mode) { + case I82443BXGX_NBXCFG_INTEGRITY_NONE: + edac_mode = EDAC_NONE; + break; + case I82443BXGX_NBXCFG_INTEGRITY_EC: + edac_mode = EDAC_EC; + break; + case I82443BXGX_NBXCFG_INTEGRITY_ECC: + case I82443BXGX_NBXCFG_INTEGRITY_SCRUB: + edac_mode = EDAC_SECDED; + break; + default: + debugf0("%s(): Unknown/reserved ECC state in NBXCFG register!\n", + __func__); + edac_mode = EDAC_UNKNOWN; + break; + } + + i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype); + + /* Many BIOSes don't clear error flags on boot, so do this + * here, or we get "phantom" errors occuring at module-load + * time. */ + pci_write_bits32(pdev, I82443BXGX_EAP, + (I82443BXGX_EAP_OFFSET_SBE | I82443BXGX_EAP_OFFSET_MBE), + (I82443BXGX_EAP_OFFSET_SBE | I82443BXGX_EAP_OFFSET_MBE)); + + mci->mod_name = EDAC_MOD_STR; + mci->mod_ver = I82443_REVISION; + mci->ctl_name = "I82443BXGX"; + mci->edac_check = i82443bxgx_edacmc_check; + mci->ctl_page_to_phys = NULL; + + if (edac_mc_add_mc(mci, 0)) { + debugf3("%s(): failed edac_mc_add_mc()\n", __func__); + goto fail; + } + + debugf3("MC: " __FILE__ ": %s(): success\n", __func__); + return 0; + +fail: + edac_mc_free(mci); + return -ENODEV; +} +EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1); + +/* returns count (>= 0), or negative on error */ +static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + debugf0("MC: " __FILE__ ": %s()\n", __func__); + + /* don't need to call pci_device_enable() */ + return i82443bxgx_edacmc_probe1(pdev, ent->driver_data); +} + + +static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) +{ + struct mem_ctl_info *mci; + + debugf0(__FILE__ ": %s()\n", __func__); + + if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL ) + return; + + edac_mc_free(mci); +} +EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one); + + +static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = { + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)}, + {0,} /* 0 terminated list. */ +}; + +MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl); + + +static struct pci_driver i82443bxgx_edacmc_driver = { + .name = EDAC_MOD_STR, + .probe = i82443bxgx_edacmc_init_one, + .remove = __devexit_p(i82443bxgx_edacmc_remove_one), + .id_table = i82443bxgx_pci_tbl, +}; + + +static int __init i82443bxgx_edacmc_init(void) +{ + return pci_register_driver(&i82443bxgx_edacmc_driver); +} + + +static void __exit i82443bxgx_edacmc_exit(void) +{ + pci_unregister_driver(&i82443bxgx_edacmc_driver); +} + + +module_init(i82443bxgx_edacmc_init); +module_exit(i82443bxgx_edacmc_exit); + + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tim Small - WPAD"); +MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers"); -- cgit v1.2.1 From 20bcb7a81dee21bfa3408f03f46b2891c9b5c84b Mon Sep 17 00:00:00 2001 From: Douglas Thompson Date: Thu, 19 Jul 2007 01:49:47 -0700 Subject: drivers/edac: mod use edac_core.h In the refactoring of edac_mc.c into several subsystem files, the header file edac_mc.h became meaningless. A new header file edac_core.h was created. All the files that previously included "edac_mc.h" are changed to include "edac_core.h". Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/i82443bxgx_edac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/edac/i82443bxgx_edac.c') diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c index ecf2ba82989c..a94bb38ea8e4 100644 --- a/drivers/edac/i82443bxgx_edac.c +++ b/drivers/edac/i82443bxgx_edac.c @@ -29,7 +29,7 @@ #include -#include "edac_mc.h" +#include "edac_core.h" #define I82443_REVISION "0.1" -- cgit v1.2.1 From c4192705fec85219086231a1c0fa61e8776e2c3b Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Thu, 19 Jul 2007 01:49:47 -0700 Subject: drivers/edac: add dev_name getter function Move dev_name() macro to a more generic interface since it's not possible to determine whether a device is pci, platform, or of_device easily. Now each low level driver sets the name into the control structure, and the EDAC core references the control structure for the information. Better abstraction. Signed-off-by: Dave Jiang Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/i82443bxgx_edac.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/edac/i82443bxgx_edac.c') diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c index a94bb38ea8e4..f88ea075ff2d 100644 --- a/drivers/edac/i82443bxgx_edac.c +++ b/drivers/edac/i82443bxgx_edac.c @@ -318,6 +318,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) mci->mod_name = EDAC_MOD_STR; mci->mod_ver = I82443_REVISION; mci->ctl_name = "I82443BXGX"; + mci->dev_name = pci_name(pdev); mci->edac_check = i82443bxgx_edacmc_check; mci->ctl_page_to_phys = NULL; -- cgit v1.2.1 From 11116601092c42364892d3f59c8f4a8a30916867 Mon Sep 17 00:00:00 2001 From: Douglas Thompson Date: Thu, 19 Jul 2007 01:50:07 -0700 Subject: drivers/edac: Lindent i82443bxgx Run i82443bxgx.c file through Lindent for cleanup Signed-off-by: Douglas Thompson Signed-off-by: Dave Jiang Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/i82443bxgx_edac.c | 160 +++++++++++++++++++---------------------- 1 file changed, 72 insertions(+), 88 deletions(-) (limited to 'drivers/edac/i82443bxgx_edac.c') diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c index f88ea075ff2d..c0070aba87bb 100644 --- a/drivers/edac/i82443bxgx_edac.c +++ b/drivers/edac/i82443bxgx_edac.c @@ -35,7 +35,6 @@ #define EDAC_MOD_STR "i82443bxgx_edac" - /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory * rows" "The 82443BX supports multiple-bit error detection and @@ -61,67 +60,60 @@ #define I82443BXGX_NR_CHANS 1 #define I82443BXGX_NR_DIMMS 4 - - /* 82443 PCI Device 0 */ -#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI - * config space offset */ -#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if - * row is non-ECC */ -#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */ - -#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */ -#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */ -#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */ -#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */ -#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */ +#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI + * config space offset */ +#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if + * row is non-ECC */ +#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */ + +#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */ +#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */ +#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */ +#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */ +#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */ #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6 - /* 82443 PCI Device 0 */ -#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI - * config space offset, Error Address - * Pointer Register */ -#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */ -#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */ -#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC)*/ - -#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI +#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI + * config space offset, Error Address + * Pointer Register */ +#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */ +#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */ +#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */ + +#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI * config space offset. */ -#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */ -#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */ +#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */ +#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */ -#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI +#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI * config space offset. */ -#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */ -#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */ -#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */ -#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */ - +#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */ +#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */ +#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */ +#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */ -#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI - * config space offset. */ -#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */ -#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */ +#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI + * config space offset. */ +#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */ +#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */ #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */ -#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */ - - -#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI - * config space offset. */ +#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */ +#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI + * config space offset. */ /* FIXME - don't poll when ECC disabled? */ - struct i82443bxgx_edacmc_error_info { u32 eap; }; - -static void i82443bxgx_edacmc_get_error_info (struct mem_ctl_info *mci, - struct i82443bxgx_edacmc_error_info *info) +static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci, + struct i82443bxgx_edacmc_error_info + *info) { struct pci_dev *pdev; pdev = to_pci_dev(mci->dev); @@ -139,9 +131,10 @@ static void i82443bxgx_edacmc_get_error_info (struct mem_ctl_info *mci, I82443BXGX_EAP_OFFSET_MBE); } - -static int i82443bxgx_edacmc_process_error_info (struct mem_ctl_info *mci, - struct i82443bxgx_edacmc_error_info *info, int handle_errors) +static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci, + struct + i82443bxgx_edacmc_error_info + *info, int handle_errors) { int error_found = 0; u32 eapaddr, page, pageoffset; @@ -152,31 +145,26 @@ static int i82443bxgx_edacmc_process_error_info (struct mem_ctl_info *mci, page = eapaddr >> PAGE_SHIFT; pageoffset = eapaddr - (page << PAGE_SHIFT); - if (info->eap & I82443BXGX_EAP_OFFSET_SBE) { + if (info->eap & I82443BXGX_EAP_OFFSET_SBE) { error_found = 1; if (handle_errors) - edac_mc_handle_ce( - mci, page, pageoffset, - /* 440BX/GX don't make syndrome information available */ - 0, - edac_mc_find_csrow_by_page(mci, page), - 0, /* channel */ - mci->ctl_name); + edac_mc_handle_ce(mci, page, pageoffset, + /* 440BX/GX don't make syndrome information available */ + 0, edac_mc_find_csrow_by_page(mci, page), 0, /* channel */ + mci->ctl_name); } - if (info->eap & I82443BXGX_EAP_OFFSET_MBE) { + if (info->eap & I82443BXGX_EAP_OFFSET_MBE) { error_found = 1; if (handle_errors) - edac_mc_handle_ue( - mci, page, pageoffset, - edac_mc_find_csrow_by_page(mci, page), - mci->ctl_name); + edac_mc_handle_ue(mci, page, pageoffset, + edac_mc_find_csrow_by_page(mci, page), + mci->ctl_name); } return error_found; } - static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) { struct i82443bxgx_edacmc_error_info info; @@ -186,11 +174,10 @@ static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) i82443bxgx_edacmc_process_error_info(mci, &info, 1); } - static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, - struct pci_dev *pdev, - enum edac_type edac_mode, - enum mem_type mtype) + struct pci_dev *pdev, + enum edac_type edac_mode, + enum mem_type mtype) { struct csrow_info *csrow; int index; @@ -233,8 +220,7 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, } } - -static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) +static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) { struct mem_ctl_info *mci; u8 dramc; @@ -260,7 +246,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) { - case I82443BXGX_DRAMC_DRAM_IS_EDO: + case I82443BXGX_DRAMC_DRAM_IS_EDO: mtype = MEM_EDO; break; case I82443BXGX_DRAMC_DRAM_IS_SDRAM: @@ -270,7 +256,8 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) mtype = MEM_RDR; break; default: - debugf0("Unknown/reserved DRAM type value in DRAMC register!\n"); + debugf0 + ("Unknown/reserved DRAM type value in DRAMC register!\n"); mtype = -MEM_UNKNOWN; } @@ -282,13 +269,12 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) mci->scrub_cap = SCRUB_FLAG_HW_SRC; pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg); ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) & - (BIT(0) | BIT(1))); + (BIT(0) | BIT(1))); mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB) - ? SCRUB_HW_SRC - : SCRUB_NONE; + ? SCRUB_HW_SRC : SCRUB_NONE; - switch(ecc_mode) { + switch (ecc_mode) { case I82443BXGX_NBXCFG_INTEGRITY_NONE: edac_mode = EDAC_NONE; break; @@ -300,8 +286,9 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) edac_mode = EDAC_SECDED; break; default: - debugf0("%s(): Unknown/reserved ECC state in NBXCFG register!\n", - __func__); + debugf0 + ("%s(): Unknown/reserved ECC state in NBXCFG register!\n", + __func__); edac_mode = EDAC_UNKNOWN; break; } @@ -312,8 +299,10 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) * here, or we get "phantom" errors occuring at module-load * time. */ pci_write_bits32(pdev, I82443BXGX_EAP, - (I82443BXGX_EAP_OFFSET_SBE | I82443BXGX_EAP_OFFSET_MBE), - (I82443BXGX_EAP_OFFSET_SBE | I82443BXGX_EAP_OFFSET_MBE)); + (I82443BXGX_EAP_OFFSET_SBE | + I82443BXGX_EAP_OFFSET_MBE), + (I82443BXGX_EAP_OFFSET_SBE | + I82443BXGX_EAP_OFFSET_MBE)); mci->mod_name = EDAC_MOD_STR; mci->mod_ver = I82443_REVISION; @@ -330,36 +319,36 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) debugf3("MC: " __FILE__ ": %s(): success\n", __func__); return 0; -fail: + fail: edac_mc_free(mci); return -ENODEV; } + EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1); /* returns count (>= 0), or negative on error */ static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev, - const struct pci_device_id *ent) + const struct pci_device_id *ent) { debugf0("MC: " __FILE__ ": %s()\n", __func__); /* don't need to call pci_device_enable() */ - return i82443bxgx_edacmc_probe1(pdev, ent->driver_data); + return i82443bxgx_edacmc_probe1(pdev, ent->driver_data); } - static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) { struct mem_ctl_info *mci; debugf0(__FILE__ ": %s()\n", __func__); - if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL ) + if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) return; edac_mc_free(mci); } -EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one); +EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one); static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = { {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)}, @@ -371,7 +360,6 @@ static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = { MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl); - static struct pci_driver i82443bxgx_edacmc_driver = { .name = EDAC_MOD_STR, .probe = i82443bxgx_edacmc_init_one, @@ -379,23 +367,19 @@ static struct pci_driver i82443bxgx_edacmc_driver = { .id_table = i82443bxgx_pci_tbl, }; - static int __init i82443bxgx_edacmc_init(void) { return pci_register_driver(&i82443bxgx_edacmc_driver); } - static void __exit i82443bxgx_edacmc_exit(void) { pci_unregister_driver(&i82443bxgx_edacmc_driver); } - module_init(i82443bxgx_edacmc_init); module_exit(i82443bxgx_edacmc_exit); - MODULE_LICENSE("GPL"); MODULE_AUTHOR("Tim Small - WPAD"); MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers"); -- cgit v1.2.1 From 456a2f9552e7849475f4aea1a9aa4c0e54b3ddda Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Thu, 19 Jul 2007 01:50:10 -0700 Subject: drivers/edac: drivers to use new PCI operation Move x86 drivers to new pci controller setup Signed-off-by: Dave Jiang Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/i82443bxgx_edac.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/edac/i82443bxgx_edac.c') diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c index c0070aba87bb..d190104081ca 100644 --- a/drivers/edac/i82443bxgx_edac.c +++ b/drivers/edac/i82443bxgx_edac.c @@ -111,6 +111,8 @@ struct i82443bxgx_edacmc_error_info { u32 eap; }; +static struct edac_pci_ctl_info *i82443bxgx_pci; + static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci, struct i82443bxgx_edacmc_error_info *info) @@ -316,6 +318,17 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) goto fail; } + /* allocating generic PCI control info */ + i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); + if (!i82443bxgx_pci) { + printk(KERN_WARNING + "%s(): Unable to create PCI control\n", + __func__); + printk(KERN_WARNING + "%s(): PCI error report via EDAC not setup\n", + __func__); + } + debugf3("MC: " __FILE__ ": %s(): success\n", __func__); return 0; @@ -342,6 +355,9 @@ static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) debugf0(__FILE__ ": %s()\n", __func__); + if (i82443bxgx_pci) + edac_pci_release_generic_ctl(i82443bxgx_pci); + if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) return; -- cgit v1.2.1 From 052dfb45ccb5ea354a426b52556bcfee75b9d2f5 Mon Sep 17 00:00:00 2001 From: Douglas Thompson Date: Thu, 19 Jul 2007 01:50:13 -0700 Subject: drivers/edac: cleanup spaces-gotos after Lindent messup This patch fixes some remnant spaces inserted by the use of Lindent. Seems Lindent adds some spaces when it shoulded. These have been fixed. In addition, goto targets have issues, these have been fixed in this patch. Signed-off-by: Douglas Thompson Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/i82443bxgx_edac.c | 47 +++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 23 deletions(-) (limited to 'drivers/edac/i82443bxgx_edac.c') diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c index d190104081ca..445ed56558f1 100644 --- a/drivers/edac/i82443bxgx_edac.c +++ b/drivers/edac/i82443bxgx_edac.c @@ -114,8 +114,8 @@ struct i82443bxgx_edacmc_error_info { static struct edac_pci_ctl_info *i82443bxgx_pci; static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci, - struct i82443bxgx_edacmc_error_info - *info) + struct i82443bxgx_edacmc_error_info + *info) { struct pci_dev *pdev; pdev = to_pci_dev(mci->dev); @@ -151,17 +151,18 @@ static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci, error_found = 1; if (handle_errors) edac_mc_handle_ce(mci, page, pageoffset, - /* 440BX/GX don't make syndrome information available */ - 0, edac_mc_find_csrow_by_page(mci, page), 0, /* channel */ - mci->ctl_name); + /* 440BX/GX don't make syndrome information + * available */ + 0, edac_mc_find_csrow_by_page(mci, page), 0, + mci->ctl_name); } if (info->eap & I82443BXGX_EAP_OFFSET_MBE) { error_found = 1; if (handle_errors) edac_mc_handle_ue(mci, page, pageoffset, - edac_mc_find_csrow_by_page(mci, page), - mci->ctl_name); + edac_mc_find_csrow_by_page(mci, page), + mci->ctl_name); } return error_found; @@ -177,9 +178,9 @@ static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) } static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, - struct pci_dev *pdev, - enum edac_type edac_mode, - enum mem_type mtype) + struct pci_dev *pdev, + enum edac_type edac_mode, + enum mem_type mtype) { struct csrow_info *csrow; int index; @@ -233,7 +234,8 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) debugf0("MC: " __FILE__ ": %s()\n", __func__); /* Something is really hosed if PCI config space reads from - the MC aren't working. */ + * the MC aren't working. + */ if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg)) return -EIO; @@ -258,8 +260,8 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) mtype = MEM_RDR; break; default: - debugf0 - ("Unknown/reserved DRAM type value in DRAMC register!\n"); + debugf0("Unknown/reserved DRAM type value " + "in DRAMC register!\n"); mtype = -MEM_UNKNOWN; } @@ -271,10 +273,10 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) mci->scrub_cap = SCRUB_FLAG_HW_SRC; pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg); ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) & - (BIT(0) | BIT(1))); + (BIT(0) | BIT(1))); mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB) - ? SCRUB_HW_SRC : SCRUB_NONE; + ? SCRUB_HW_SRC : SCRUB_NONE; switch (ecc_mode) { case I82443BXGX_NBXCFG_INTEGRITY_NONE: @@ -288,9 +290,8 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) edac_mode = EDAC_SECDED; break; default: - debugf0 - ("%s(): Unknown/reserved ECC state in NBXCFG register!\n", - __func__); + debugf0("%s(): Unknown/reserved ECC state " + "in NBXCFG register!\n", __func__); edac_mode = EDAC_UNKNOWN; break; } @@ -301,10 +302,10 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) * here, or we get "phantom" errors occuring at module-load * time. */ pci_write_bits32(pdev, I82443BXGX_EAP, - (I82443BXGX_EAP_OFFSET_SBE | - I82443BXGX_EAP_OFFSET_MBE), - (I82443BXGX_EAP_OFFSET_SBE | - I82443BXGX_EAP_OFFSET_MBE)); + (I82443BXGX_EAP_OFFSET_SBE | + I82443BXGX_EAP_OFFSET_MBE), + (I82443BXGX_EAP_OFFSET_SBE | + I82443BXGX_EAP_OFFSET_MBE)); mci->mod_name = EDAC_MOD_STR; mci->mod_ver = I82443_REVISION; @@ -332,7 +333,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) debugf3("MC: " __FILE__ ": %s(): success\n", __func__); return 0; - fail: +fail: edac_mc_free(mci); return -ENODEV; } -- cgit v1.2.1 From b8f6f9755248026f21282e25cac49a1af698056c Mon Sep 17 00:00:00 2001 From: Doug Thompson Date: Thu, 19 Jul 2007 01:50:26 -0700 Subject: drivers/edac: fix edac_mc init apis Refactoring of sysfs code necessitated the refactoring of the edac_mc_alloc() and edac_mc_add_mc() apis, of moving the index value to the alloc() function. This patch alters the in tree drivers to utilize this new api signature. Having the index value performed later created a chicken-and-the-egg issue. Moving it to the alloc() function allows for creating the necessary sysfs entries with the proper index number Cc: Alan Cox alan@lxorguk.ukuu.org.uk Signed-off-by: Doug Thompson Cc: Greg KH Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/edac/i82443bxgx_edac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/edac/i82443bxgx_edac.c') diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c index 445ed56558f1..83bfe37c4bbb 100644 --- a/drivers/edac/i82443bxgx_edac.c +++ b/drivers/edac/i82443bxgx_edac.c @@ -239,7 +239,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg)) return -EIO; - mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS); + mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS, 0); if (mci == NULL) return -ENOMEM; @@ -314,7 +314,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) mci->edac_check = i82443bxgx_edacmc_check; mci->ctl_page_to_phys = NULL; - if (edac_mc_add_mc(mci, 0)) { + if (edac_mc_add_mc(mci)) { debugf3("%s(): failed edac_mc_add_mc()\n", __func__); goto fail; } -- cgit v1.2.1