From 0d4649684ca6cbc536fcc509e7aac0b34bb4146a Mon Sep 17 00:00:00 2001 From: John Crispin Date: Fri, 23 Aug 2013 08:31:32 +0200 Subject: MIPS: ralink: mt7620: Add spi clock definition Register a clock device for the SPI block of the MT7620 SoC. The clock device will be used by the SPI host controller driver to determine the base clock of the controller. Signed-off-by: John Crispin Signed-off-by: Gabor Juhos Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5754/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/mt7620.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips') diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 7759c5a59a5d..d217509e5300 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -318,6 +318,7 @@ void __init ralink_clk_init(void) ralink_clk_add("10000100.timer", periph_rate); ralink_clk_add("10000120.watchdog", periph_rate); ralink_clk_add("10000500.uart", periph_rate); + ralink_clk_add("10000b00.spi", sys_rate); ralink_clk_add("10000c00.uartlite", periph_rate); } -- cgit v1.2.1