From c83a917112ccab57044e4c8aede4c0a765c1041c Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 29 Nov 2012 11:41:17 +0800 Subject: blackfin: dmc: Improve DDR2 write through in DMC effict controller. Signed-off-by: Sonic Zhang Signed-off-by: Steven Miao --- arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/blackfin/mach-bf609/include/mach') diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h index 4954cf3f7e16..102ee4025ac9 100644 --- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h +++ b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h @@ -312,6 +312,8 @@ #define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) #define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) #define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) +#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL) +#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val) #define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) #define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) #define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL) -- cgit v1.2.1