From 3924996bab2845bdf9a9d16ff7c20445de1ab55d Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Thu, 21 Oct 2010 15:48:33 -0400 Subject: [ARM] Kirkwood: restrict the scope of the PCIe reset workaround Commit 21f0ba90a447 "orion/kirkwood: reset PCIe unit on boot" made the reset of the PCIe unit unconditional. While this may fix problems on some targets, this also causes problems on other targets. Saeed Bishara said about the original problem: "We couln't pinpoint the root cause of this issue, actually we failed to reproduce that issue." So let's restrict the reset of the PCIe unit only to the target where the original problem was observed. Signed-off-by: Nicolas Pitre --- arch/arm/plat-orion/include/plat/pcie.h | 3 +++ arch/arm/plat-orion/pcie.c | 5 ----- 2 files changed, 3 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-orion') diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h index 3ebfef72b4e7..cc99163e73fd 100644 --- a/arch/arm/plat-orion/include/plat/pcie.h +++ b/arch/arm/plat-orion/include/plat/pcie.h @@ -11,12 +11,15 @@ #ifndef __PLAT_PCIE_H #define __PLAT_PCIE_H +struct pci_bus; + u32 orion_pcie_dev_id(void __iomem *base); u32 orion_pcie_rev(void __iomem *base); int orion_pcie_link_up(void __iomem *base); int orion_pcie_x4_mode(void __iomem *base); int orion_pcie_get_local_bus_nr(void __iomem *base); void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); +void orion_pcie_reset(void __iomem *base); void orion_pcie_setup(void __iomem *base, struct mbus_dram_target_info *dram); int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c index 779553a1595e..af2d733c50b5 100644 --- a/arch/arm/plat-orion/pcie.c +++ b/arch/arm/plat-orion/pcie.c @@ -181,11 +181,6 @@ void __init orion_pcie_setup(void __iomem *base, u16 cmd; u32 mask; - /* - * soft reset PCIe unit - */ - orion_pcie_reset(base); - /* * Point PCIe unit MBUS decode windows to DRAM space. */ -- cgit v1.2.1 From 1d0ac3cdf3d31ba84499c3a914aa2b54eecbf2af Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 13 Dec 2010 13:21:33 +0000 Subject: ARM: orion: update clock source registration In d7e81c2 (clocksource: Add clocksource_register_hz/khz interface) new interfaces were added which simplify (and optimize) the selection of the divisor shift/mult constants. Switch over to using this new interface. Acked-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/plat-orion/time.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/arm/plat-orion') diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 715a30177f28..11e2583e85e4 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -102,7 +102,6 @@ static cycle_t orion_clksrc_read(struct clocksource *cs) static struct clocksource orion_clksrc = { .name = "orion_clocksource", - .shift = 20, .rating = 300, .read = orion_clksrc_read, .mask = CLOCKSOURCE_MASK(32), @@ -245,8 +244,7 @@ void __init orion_time_init(unsigned int irq, unsigned int tclk) writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); u = readl(TIMER_CTRL); writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); - orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); - clocksource_register(&orion_clksrc); + clocksource_register_hz(&orion_clksrc, tclk); /* * Setup clockevent timer (interrupt-driven.) -- cgit v1.2.1 From 5e06b6492e53ab2a4e467763a9ee9f70b032c301 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Dec 2010 19:19:25 +0000 Subject: ARM: ensure all sched_clock() implementations are notrace marked ftrace requires sched_clock() to be notrace. Ensure that all implementations are so marked. Also make sure that they include linux/sched.h Also ensure OMAP clocksource read functions are marked notrace as they're used for sched_clock() too. Tested-by: Santosh Shilimkar Tested-by: Will Deacon Tested-by: Mikael Pettersson Tested-by: Eric Miao Tested-by: Olof Johansson Signed-off-by: Russell King --- arch/arm/plat-orion/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/plat-orion') diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 11e2583e85e4..123f96f4194f 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -55,7 +55,7 @@ static u32 ticks_per_jiffy; static unsigned long tclk2ns_scale; -unsigned long long sched_clock(void) +unsigned long long notrace sched_clock(void) { unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL)); return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR; -- cgit v1.2.1 From f06a1624621527ef597ae4b3b795553fc1b2eff2 Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 15 Dec 2010 21:55:06 +0000 Subject: ARM: orion: convert sched_clock() to use new infrastructure Convert orion platforms to use the new sched_clock() infrastructure for extending 32bit counters to full 64-bit nanoseconds. Acked-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/plat-orion/time.c | 44 +++++++++----------------------------------- 1 file changed, 9 insertions(+), 35 deletions(-) (limited to 'arch/arm/plat-orion') diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 123f96f4194f..c3da2478b2aa 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -13,11 +13,11 @@ #include #include -#include #include #include #include #include +#include #include #include #include @@ -44,52 +44,26 @@ static u32 ticks_per_jiffy; /* * Orion's sched_clock implementation. It has a resolution of - * at least 7.5ns (133MHz TCLK) and a maximum value of 834 days. - * - * Because the hardware timer period is quite short (21 secs if - * 200MHz TCLK) and because cnt32_to_63() needs to be called at - * least once per half period to work properly, a kernel timer is - * set up to ensure this requirement is always met. + * at least 7.5ns (133MHz TCLK). */ -#define TCLK2NS_SCALE_FACTOR 8 - -static unsigned long tclk2ns_scale; +static DEFINE_CLOCK_DATA(cd); unsigned long long notrace sched_clock(void) { - unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL)); - return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR; + u32 cyc = 0xffffffff - readl(TIMER0_VAL); + return cyc_to_sched_clock(&cd, cyc, (u32)~0); } -static struct timer_list cnt32_to_63_keepwarm_timer; -static void cnt32_to_63_keepwarm(unsigned long data) +static void notrace orion_update_sched_clock(void) { - mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); - (void) sched_clock(); + u32 cyc = 0xffffffff - readl(TIMER0_VAL); + update_sched_clock(&cd, cyc, (u32)~0); } static void __init setup_sched_clock(unsigned long tclk) { - unsigned long long v; - unsigned long data; - - v = NSEC_PER_SEC; - v <<= TCLK2NS_SCALE_FACTOR; - v += tclk/2; - do_div(v, tclk); - /* - * We want an even value to automatically clear the top bit - * returned by cnt32_to_63() without an additional run time - * instruction. So if the LSB is 1 then round it up. - */ - if (v & 1) - v++; - tclk2ns_scale = v; - - data = (0xffffffffUL / tclk / 2 - 2) * HZ; - setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); - mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); + init_sched_clock(&cd, orion_update_sched_clock, 32, tclk); } /* -- cgit v1.2.1 From 3b0c8d40387482d6a446da9ef0c97fede20a7b89 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Mon, 29 Nov 2010 11:17:38 +0100 Subject: ARM: plat-orion: irq_data conversion. Signed-off-by: Lennert Buytenhek Acked-by: Nicolas Pitre --- arch/arm/plat-orion/gpio.c | 37 ++++++++++++++++++------------------- arch/arm/plat-orion/irq.c | 18 +++++++++--------- 2 files changed, 27 insertions(+), 28 deletions(-) (limited to 'arch/arm/plat-orion') diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index e814803d4741..5f3522314815 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -232,20 +232,19 @@ EXPORT_SYMBOL(orion_gpio_set_blink); * polarity LEVEL mask * ****************************************************************************/ - -static void gpio_irq_ack(u32 irq) +static void gpio_irq_ack(struct irq_data *d) { - int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; + int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { - int pin = irq_to_gpio(irq); + int pin = irq_to_gpio(d->irq); writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin)); } } -static void gpio_irq_mask(u32 irq) +static void gpio_irq_mask(struct irq_data *d) { - int pin = irq_to_gpio(irq); - int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; + int pin = irq_to_gpio(d->irq); + int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); u32 u = readl(reg); @@ -253,10 +252,10 @@ static void gpio_irq_mask(u32 irq) writel(u, reg); } -static void gpio_irq_unmask(u32 irq) +static void gpio_irq_unmask(struct irq_data *d) { - int pin = irq_to_gpio(irq); - int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK; + int pin = irq_to_gpio(d->irq); + int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ? GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin); u32 u = readl(reg); @@ -264,20 +263,20 @@ static void gpio_irq_unmask(u32 irq) writel(u, reg); } -static int gpio_irq_set_type(u32 irq, u32 type) +static int gpio_irq_set_type(struct irq_data *d, u32 type) { - int pin = irq_to_gpio(irq); + int pin = irq_to_gpio(d->irq); struct irq_desc *desc; u32 u; u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)); if (!u) { printk(KERN_ERR "orion gpio_irq_set_type failed " - "(irq %d, pin %d).\n", irq, pin); + "(irq %d, pin %d).\n", d->irq, pin); return -EINVAL; } - desc = irq_desc + irq; + desc = irq_desc + d->irq; /* * Set edge/level type. @@ -287,7 +286,7 @@ static int gpio_irq_set_type(u32 irq, u32 type) } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { desc->handle_irq = handle_level_irq; } else { - printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); + printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type); return -EINVAL; } @@ -325,10 +324,10 @@ static int gpio_irq_set_type(u32 irq, u32 type) struct irq_chip orion_gpio_irq_chip = { .name = "orion_gpio_irq", - .ack = gpio_irq_ack, - .mask = gpio_irq_mask, - .unmask = gpio_irq_unmask, - .set_type = gpio_irq_set_type, + .irq_ack = gpio_irq_ack, + .irq_mask = gpio_irq_mask, + .irq_unmask = gpio_irq_unmask, + .irq_set_type = gpio_irq_set_type, }; void orion_gpio_irq_handler(int pinoff) diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 3f9d34fc738c..7d0c7eb59f09 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -14,31 +14,31 @@ #include #include -static void orion_irq_mask(u32 irq) +static void orion_irq_mask(struct irq_data *d) { - void __iomem *maskaddr = get_irq_chip_data(irq); + void __iomem *maskaddr = irq_data_get_irq_chip_data(d); u32 mask; mask = readl(maskaddr); - mask &= ~(1 << (irq & 31)); + mask &= ~(1 << (d->irq & 31)); writel(mask, maskaddr); } -static void orion_irq_unmask(u32 irq) +static void orion_irq_unmask(struct irq_data *d) { - void __iomem *maskaddr = get_irq_chip_data(irq); + void __iomem *maskaddr = irq_data_get_irq_chip_data(d); u32 mask; mask = readl(maskaddr); - mask |= 1 << (irq & 31); + mask |= 1 << (d->irq & 31); writel(mask, maskaddr); } static struct irq_chip orion_irq_chip = { .name = "orion_irq", - .mask = orion_irq_mask, - .mask_ack = orion_irq_mask, - .unmask = orion_irq_unmask, + .irq_mask = orion_irq_mask, + .irq_mask_ack = orion_irq_mask, + .irq_unmask = orion_irq_unmask, }; void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) -- cgit v1.2.1